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git01.mediatek.com / filogic / uboot / c609719b8d1b2dca590e0ed499016d041203e403 / . / include / configs / OCRTC.h
blob: 5971fb42e8968e3256f0623369865884f846782c [file] [log] [blame]
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame^]1/*
2 * (C) Copyright 2001
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_405GP 1 /* This is a PPC405 CPU */
37#define CONFIG_4xx 1 /* ...member of PPC4xx family */
38#define CONFIG_OCRTC 1 /* ...on a OCRTC board */
39
40#define CONFIG_BOARD_PRE_INIT 1 /* call board_pre_init() */
41
42#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
43
44#define CONFIG_BAUDRATE 9600
45#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
46
47#undef CONFIG_BOOTARGS
48#define CONFIG_BOOTCOMMAND "go fff00100"
49
50#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
51#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
52
53#define CONFIG_MII 1 /* MII PHY management */
54#define CONFIG_PHY_ADDR 0 /* PHY address */
55
56#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
57 CFG_CMD_PCI | \
58 CFG_CMD_IRQ | \
59 CFG_CMD_ASKENV | \
60 CFG_CMD_ELF | \
61 CFG_CMD_EEPROM )
62
63#define CONFIG_MAC_PARTITION
64#define CONFIG_DOS_PARTITION
65
66/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
67#include <cmd_confdefs.h>
68
69#undef CONFIG_WATCHDOG /* watchdog disabled */
70
71#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
72
73/*
74 * Miscellaneous configurable options
75 */
76#define CFG_LONGHELP /* undef to save memory */
77#define CFG_PROMPT "=> " /* Monitor Command Prompt */
78#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
79#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
80#else
81#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
82#endif
83#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
84#define CFG_MAXARGS 16 /* max number of command args */
85#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
86
87#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
88
89#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
90#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
91
92#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
93#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
94#define CFG_BASE_BAUD 691200
95
96/* The following table includes the supported baudrates */
97#define CFG_BAUDRATE_TABLE \
98 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
99 57600, 115200, 230400, 460800, 921600 }
100
101#define CFG_LOAD_ADDR 0x100000 /* default load address */
102#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
103
104#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
105
106#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
107
108/*-----------------------------------------------------------------------
109 * PCI stuff
110 *-----------------------------------------------------------------------
111 */
112#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
113#define PCI_HOST_FORCE 1 /* configure as pci host */
114#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
115
116#define CONFIG_PCI /* include pci support */
117#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
118#define CONFIG_PCI_PNP /* do pci plug-and-play */
119 /* resource configuration */
120
121#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
122
123#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
124#define CFG_PCI_SUBSYS_DEVICEID 0x0410 /* PCI Device ID: OCRTC */
125#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
126#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
127#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
128#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
129#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
130#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
131#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
132
133/*-----------------------------------------------------------------------
134 * Start addresses for the final memory configuration
135 * (Set up by the startup code)
136 * Please note that CFG_SDRAM_BASE _must_ start at 0
137 */
138#define CFG_SDRAM_BASE 0x00000000
139#define CFG_FLASH_BASE 0xFFFD0000
140#define CFG_MONITOR_BASE CFG_FLASH_BASE
141#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */
142#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
143
144/*
145 * For booting Linux, the board info and command line data
146 * have to be in the first 8 MB of memory, since this is
147 * the maximum mapped by the Linux kernel during initialization.
148 */
149#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
150/*-----------------------------------------------------------------------
151 * FLASH organization
152 */
153#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
154#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
155
156#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
157#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
158
159#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
160#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
161#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
162/*
163 * The following defines are added for buggy IOP480 byte interface.
164 * All other boards should use the standard values (CPCI405 etc.)
165 */
166#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
167#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
168#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
169
170#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
171
172#if 0 /* Use NVRAM for environment variables */
173/*-----------------------------------------------------------------------
174 * NVRAM organization
175 */
176#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
177#define CFG_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
178#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */
179#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
180#define CFG_ENV_ADDR \
181 (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */
182#define CFG_NVRAM_VXWORKS_OFFS 0x6900 /* Offset for VxWorks eth-addr */
183
184#else /* Use EEPROM for environment variables */
185
186#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
187#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
188#define CFG_ENV_SIZE 0x300 /* 768 bytes may be used for env vars */
189 /* total size of a CAT24WC08 is 1024 bytes */
190#endif
191
192/*-----------------------------------------------------------------------
193 * I2C EEPROM (CAT24WC08) for environment
194 */
195#define CONFIG_HARD_I2C /* I2c with hardware support */
196#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
197#define CFG_I2C_SLAVE 0x7F
198
199#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
200#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
201/* mask of address bits that overflow into the "EEPROM chip address" */
202#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
203#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
204 /* 16 byte page write mode using*/
205 /* last 4 bits of the address */
206#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
207#define CFG_EEPROM_PAGE_WRITE_ENABLE
208
209/*-----------------------------------------------------------------------
210 * Cache Configuration
211 */
212#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
213#define CFG_CACHELINE_SIZE 32 /* ... */
214#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
215#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
216#endif
217
218/*
219 * Init Memory Controller:
220 *
221 * BR0/1 and OR0/1 (FLASH)
222 */
223
224#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
225#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
226
227/*-----------------------------------------------------------------------
228 * External Bus Controller (EBC) Setup
229 */
230
231/* Memory Bank 0 (Flash Bank 0) initialization */
232#define CFG_EBC_PB0AP 0x92015480
233#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
234
235/* Memory Bank 1 (Flash Bank 1) initialization */
236#define CFG_EBC_PB1AP 0x92015480
237#define CFG_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
238
239/* Memory Bank 2 (PLD - FPGA-boot) initialization */
240#define CFG_EBC_PB2AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
241 /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
242#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
243
244/* Memory Bank 3 (PLD - OSL) initialization */
245#define CFG_EBC_PB3AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
246 /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
247#define CFG_EBC_PB3CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
248
249/* Memory Bank 4 (Spartan2 1) initialization */
250#define CFG_EBC_PB4AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
251 /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
252#define CFG_EBC_PB4CR 0xF209C000 /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/
253
254/* Memory Bank 5 (Spartan2 2) initialization */
255#define CFG_EBC_PB5AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
256 /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
257#define CFG_EBC_PB5CR 0xF309C000 /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/
258
259/* Memory Bank 6 (Virtex 1) initialization */
260#define CFG_EBC_PB6AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
261 /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
262#define CFG_EBC_PB6CR 0xF409A000 /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/
263
264/* Memory Bank 7 (Virtex 2) initialization */
265#define CFG_EBC_PB7AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
266 /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
267#define CFG_EBC_PB7CR 0xF509A000 /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/
268
269
270#define CFG_ETHERNET_MAC_ADDR 0x00000000 /* Pass Ethernet MAC to VxWorks */
271
272/*-----------------------------------------------------------------------
273 * Definitions for initial stack pointer and data area (in DPRAM)
274 */
275
276/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
277#define CFG_TEMP_STACK_OCM 1
278
279/* On Chip Memory location */
280#define CFG_OCM_DATA_ADDR 0xF8000000
281#define CFG_OCM_DATA_SIZE 0x1000
282
283#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
284#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
285#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
286#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
287#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
288
289
290/*
291 * Internal Definitions
292 *
293 * Boot Flags
294 */
295#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
296#define BOOTFLAG_WARM 0x02 /* Software reboot */
297
298#endif /* __CONFIG_H */