wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame^] | 1 | /* |
| 2 | * (C) Copyright 2002 |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #include <config.h> |
| 25 | #include <common.h> |
| 26 | #include <command.h> |
| 27 | #include <asm/io.h> |
| 28 | #include <linux/mtd/doc2000.h> |
| 29 | #include <watchdog.h> |
| 30 | #include <pci.h> |
| 31 | |
| 32 | #include "hardware.h" |
| 33 | #include "pcippc2.h" |
| 34 | #include "sconsole.h" |
| 35 | #include "fpga_serial.h" |
| 36 | |
| 37 | #if defined(CONFIG_WATCHDOG) |
| 38 | |
| 39 | static int pcippc2_wdt_init_done = 0; |
| 40 | |
| 41 | void pcippc2_wdt_init (void); |
| 42 | |
| 43 | #endif |
| 44 | |
| 45 | /* Check board identity |
| 46 | */ |
| 47 | int checkboard (void) |
| 48 | { |
| 49 | #ifdef CONFIG_PCIPPC2 |
| 50 | puts ("Board: Gespac PCIPPC-2\n"); |
| 51 | #else |
| 52 | puts ("Board: Gespac PCIPPC-6\n"); |
| 53 | #endif |
| 54 | return 0; |
| 55 | } |
| 56 | |
| 57 | /* RAM size is stored in CPC0_RGBAN1 |
| 58 | */ |
| 59 | u32 pcippc2_sdram_size (void) |
| 60 | { |
| 61 | return in32 (REG (CPC0, RGBAN1)); |
| 62 | } |
| 63 | |
| 64 | long initdram (int board_type) |
| 65 | { |
| 66 | return cpc710_ram_init (); |
| 67 | } |
| 68 | |
| 69 | void do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) |
| 70 | { |
| 71 | out32 (REG (CPC0, SPOR), 0); |
| 72 | iobarrier_rw (); |
| 73 | while (1); |
| 74 | } |
| 75 | |
| 76 | int board_pre_init (void) |
| 77 | { |
| 78 | out32 (REG (CPC0, RSTR), 0xC0000000); |
| 79 | iobarrier_rw (); |
| 80 | |
| 81 | out32 (REG (CPC0, RSTR), 0xF0000000); |
| 82 | iobarrier_rw (); |
| 83 | |
| 84 | out32 (REG (CPC0, UCTL), 0x00F80000); |
| 85 | |
| 86 | out32 (REG (CPC0, SIOC0), 0x30000000); |
| 87 | |
| 88 | out32 (REG (CPC0, ABCNTL), 0x00000000); |
| 89 | |
| 90 | out32 (REG (CPC0, SESR), 0x00000000); |
| 91 | out32 (REG (CPC0, SEAR), 0x00000000); |
| 92 | |
| 93 | /* Detect IBM Avignon CPC710 Revision */ |
| 94 | if ((in32 (REG (CPC0, UCTL)) & 0x000000F0) == CPC710_TYPE_100P) |
| 95 | out32 (REG (CPC0, PGCHP), 0xA0000040); |
| 96 | else |
| 97 | out32 (REG (CPC0, PGCHP), 0x80800040); |
| 98 | |
| 99 | |
| 100 | out32 (REG (CPC0, ATAS), 0x709C2508); |
| 101 | |
| 102 | iobarrier_rw (); |
| 103 | |
| 104 | return 0; |
| 105 | } |
| 106 | |
| 107 | void after_reloc (ulong dest_addr) |
| 108 | { |
| 109 | DECLARE_GLOBAL_DATA_PTR; |
| 110 | |
| 111 | /* Jump to the main U-Boot board init code |
| 112 | */ |
| 113 | board_init_r (gd, dest_addr); |
| 114 | } |
| 115 | |
| 116 | int misc_init_r (void) |
| 117 | { |
| 118 | pcippc2_fpga_init (); |
| 119 | |
| 120 | #if defined(CONFIG_WATCHDOG) |
| 121 | pcippc2_wdt_init (); |
| 122 | #endif |
| 123 | |
| 124 | fpga_serial_init (sconsole_get_baudrate ()); |
| 125 | |
| 126 | sconsole_putc = fpga_serial_putc; |
| 127 | sconsole_puts = fpga_serial_puts; |
| 128 | sconsole_getc = fpga_serial_getc; |
| 129 | sconsole_tstc = fpga_serial_tstc; |
| 130 | sconsole_setbrg = fpga_serial_setbrg; |
| 131 | |
| 132 | sconsole_flush (); |
| 133 | return (0); |
| 134 | } |
| 135 | |
| 136 | void pci_init (void) |
| 137 | { |
| 138 | cpc710_pci_init (); |
| 139 | |
| 140 | /* FPGA requires no retry timeouts to be enabled |
| 141 | */ |
| 142 | cpc710_pci_enable_timeout (); |
| 143 | } |
| 144 | |
| 145 | void doc_init (void) |
| 146 | { |
| 147 | doc_probe (pcippc2_fpga1_phys + HW_FPGA1_DOC); |
| 148 | } |
| 149 | |
| 150 | #if defined(CONFIG_WATCHDOG) |
| 151 | |
| 152 | void pcippc2_wdt_init (void) |
| 153 | { |
| 154 | out16r (FPGA (WDT, PROG), 0xffff); |
| 155 | out8 (FPGA (WDT, CTRL), 0x1); |
| 156 | |
| 157 | pcippc2_wdt_init_done = 1; |
| 158 | } |
| 159 | |
| 160 | void pcippc2_wdt_done (void) |
| 161 | { |
| 162 | out8 (FPGA (WDT, CTRL), 0x0); |
| 163 | |
| 164 | pcippc2_wdt_init_done = 0; |
| 165 | } |
| 166 | |
| 167 | void pcippc2_wdt_reset (void) |
| 168 | { |
| 169 | if (pcippc2_wdt_init_done == 1) |
| 170 | out8 (FPGA (WDT, REFRESH), 0x56); |
| 171 | } |
| 172 | |
| 173 | void watchdog_reset (void) |
| 174 | { |
| 175 | int re_enable = disable_interrupts (); |
| 176 | |
| 177 | pcippc2_wdt_reset (); |
| 178 | if (re_enable) |
| 179 | enable_interrupts (); |
| 180 | } |
| 181 | |
| 182 | #if (CONFIG_COMMANDS & CFG_CMD_BSP) |
| 183 | int do_wd (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) |
| 184 | { |
| 185 | switch (argc) { |
| 186 | case 1: |
| 187 | printf ("Watchdog timer status is %s\n", |
| 188 | pcippc2_wdt_init_done == 1 ? "on" : "off"); |
| 189 | |
| 190 | return 0; |
| 191 | case 2: |
| 192 | if (!strcmp(argv[1],"on")) { |
| 193 | pcippc2_wdt_init(); |
| 194 | printf("Watchdog timer now is on\n"); |
| 195 | |
| 196 | return 0; |
| 197 | |
| 198 | } else if (!strcmp(argv[1],"off")) { |
| 199 | pcippc2_wdt_done(); |
| 200 | printf("Watchdog timer now is off\n"); |
| 201 | |
| 202 | return 0; |
| 203 | |
| 204 | } else |
| 205 | break; |
| 206 | default: |
| 207 | break; |
| 208 | } |
| 209 | printf ("Usage:\n%s\n", cmdtp->usage); |
| 210 | return 1; |
| 211 | } |
| 212 | |
| 213 | #endif /* CFG_CMD_BSP */ |
| 214 | #endif /* CONFIG_WATCHDOG */ |