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git01.mediatek.com / filogic / uboot / c609719b8d1b2dca590e0ed499016d041203e403 / . / board / netvia / netvia.c
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wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame^]1/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
26 * U-Boot port on NetVia board
27 */
28
29#include <common.h>
30#include "mpc8xx.h"
31
32/* some sane bit macros */
33#define _BD(_b) (1U << (31-(_b)))
34#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
35
36#define _BW(_b) (1U << (15-(_b)))
37#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
38
39#define _BB(_b) (1U << (7-(_b)))
40#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
41
42#define _B(_b) _BD(_b)
43#define _BR(_l, _h) _BDR(_l, _h)
44
45/* ------------------------------------------------------------------------- */
46
47/* ------------------------------------------------------------------------- */
48
49#define _NOT_USED_ 0xFFFFFFFF
50
51/* ------------------------------------------------------------------------- */
52
53#define CS_0000 0x00000000
54#define CS_0001 0x10000000
55#define CS_0010 0x20000000
56#define CS_0011 0x30000000
57#define CS_0100 0x40000000
58#define CS_0101 0x50000000
59#define CS_0110 0x60000000
60#define CS_0111 0x70000000
61#define CS_1000 0x80000000
62#define CS_1001 0x90000000
63#define CS_1010 0xA0000000
64#define CS_1011 0xB0000000
65#define CS_1100 0xC0000000
66#define CS_1101 0xD0000000
67#define CS_1110 0xE0000000
68#define CS_1111 0xF0000000
69
70#define BS_0000 0x00000000
71#define BS_0001 0x01000000
72#define BS_0010 0x02000000
73#define BS_0011 0x03000000
74#define BS_0100 0x04000000
75#define BS_0101 0x05000000
76#define BS_0110 0x06000000
77#define BS_0111 0x07000000
78#define BS_1000 0x08000000
79#define BS_1001 0x09000000
80#define BS_1010 0x0A000000
81#define BS_1011 0x0B000000
82#define BS_1100 0x0C000000
83#define BS_1101 0x0D000000
84#define BS_1110 0x0E000000
85#define BS_1111 0x0F000000
86
87#define A10_AAAA 0x00000000
88#define A10_AAA0 0x00200000
89#define A10_AAA1 0x00300000
90#define A10_000A 0x00800000
91#define A10_0000 0x00A00000
92#define A10_0001 0x00B00000
93#define A10_111A 0x00C00000
94#define A10_1110 0x00E00000
95#define A10_1111 0x00F00000
96
97#define RAS_0000 0x00000000
98#define RAS_0001 0x00040000
99#define RAS_1110 0x00080000
100#define RAS_1111 0x000C0000
101
102#define CAS_0000 0x00000000
103#define CAS_0001 0x00010000
104#define CAS_1110 0x00020000
105#define CAS_1111 0x00030000
106
107#define WE_0000 0x00000000
108#define WE_0001 0x00004000
109#define WE_1110 0x00008000
110#define WE_1111 0x0000C000
111
112#define GPL4_0000 0x00000000
113#define GPL4_0001 0x00001000
114#define GPL4_1110 0x00002000
115#define GPL4_1111 0x00003000
116
117#define GPL5_0000 0x00000000
118#define GPL5_0001 0x00000400
119#define GPL5_1110 0x00000800
120#define GPL5_1111 0x00000C00
121#define LOOP 0x00000080
122
123#define EXEN 0x00000040
124
125#define AMX_COL 0x00000000
126#define AMX_ROW 0x00000020
127#define AMX_MAR 0x00000030
128
129#define NA 0x00000008
130
131#define UTA 0x00000004
132
133#define TODT 0x00000002
134
135#define LAST 0x00000001
136
137const uint sdram_table[0x40] = {
138 /* RSS */
139 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
140 CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
141 CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
142 CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
143 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
144 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
145 _NOT_USED_, _NOT_USED_,
146
147 /* RBS */
148 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
149 CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
150 CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
151 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
152 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
153 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
154 CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */
155 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */
156 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
157 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
158
159 /* WSS */
160 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,
161 CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,
162 CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA,
163 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,
164 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
165
166 /* WBS */
167 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
168 CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
169 CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */
170 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
171 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
172 CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
173 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
174 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
175 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
176 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
177 _NOT_USED_, _NOT_USED_, _NOT_USED_,
178
179 /* UPT */
180 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
181 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | LOOP,
182 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,
183 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,
184 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | LOOP,
185 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | LAST,
186 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
187 _NOT_USED_, _NOT_USED_,
188
189 /* EXC */
190 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL,
191 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST,
192
193 /* REG */
194 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1110 | AMX_MAR,
195 CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | TODT | LAST,
196};
197
198/* ------------------------------------------------------------------------- */
199
200
201/*
202 * Check Board Identity:
203 *
204 * Test ETX ID string (ETX_xxx...)
205 *
206 * Return 1 always.
207 */
208
209int checkboard(void)
210{
211 printf ("NETVIA\n");
212 return (0);
213}
214
215/* ------------------------------------------------------------------------- */
216
217/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
218#define MAR_SDRAM_INIT 0x000000C8LU
219
220#define MCR_OP(x) ((unsigned long)((x) & 3) << (31-1))
221#define MCR_OP_MASK MCR_OP(3)
222
223#define MCR_UM(x) ((unsigned long)((x) & 1) << (31 - 8))
224#define MCR_UM_MASK MCR_UM(1)
225#define MCR_UM_UPMA MCR_UM(0)
226#define MCR_UM_UPMB MCR_UM(1)
227
228#define MCR_MB(x) ((unsigned long)((x) & 7) << (31 - 18))
229#define MCR_MB_MASK MCR_MB(7)
230#define MCR_MB_CS(x) MCR_MB(x)
231
232#define MCR_MCLF(x) ((unsigned long)((x) & 15) << (31 - 23))
233#define MCR_MCLF_MASK MCR_MCLF(15)
234
235long int initdram(int board_type)
236{
237 volatile immap_t *immap = (immap_t *) CFG_IMMR;
238 volatile memctl8xx_t *memctl = &immap->im_memctl;
239 long int size;
240
241 upmconfig(UPMA, (uint *) sdram_table, sizeof(sdram_table) / sizeof(uint));
242
243 /*
244 * Preliminary prescaler for refresh
245 */
246 memctl->memc_mptpr = CFG_MPTPR_1BK_8K;
247
248 memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */
249
250 /*
251 * Map controller bank 3 to the SDRAM bank at preliminary address.
252 */
253 memctl->memc_or3 = CFG_OR3_PRELIM;
254 memctl->memc_br3 = CFG_BR3_PRELIM;
255
256 memctl->memc_mamr = CFG_MAMR_9COL & ~MAMR_PTAE; /* no refresh yet */
257
258 udelay(200);
259
260 /* perform SDRAM initialisation sequence */
261 memctl->memc_mcr = MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS3 | MCR_MCLF(1) | MCR_MAD(0x3C); /* precharge all */
262 udelay(1);
263 memctl->memc_mcr = MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS3 | MCR_MCLF(0) | MCR_MAD(0x30); /* refresh 16 times(0) */
264 udelay(1);
265 memctl->memc_mcr = MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS3 | MCR_MCLF(1) | MCR_MAD(0x3E); /* exception program (write mar) */
266 udelay(1);
267
268 memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
269
270 udelay(1000);
271
272 memctl->memc_mamr = CFG_MAMR_9COL;
273
274 size = SDRAM_MAX_SIZE;
275
276 udelay(10000);
277
278 /* do the ram test */
279 {
280 register unsigned long *rp;
281 register unsigned long v;
282
283 /* first fill */
284 for (rp = (unsigned long *)0; rp < (unsigned long *)SDRAM_MAX_SIZE; )
285 *rp++ = (unsigned long)rp;
286
287 /* now check */
288 for (rp = (unsigned long *)0; rp < (unsigned long *)SDRAM_MAX_SIZE; rp++) {
289 if ((v = *rp) != (unsigned long)rp) {
290 printf("ERROR at 0x%lx (0x%lx)\n", (unsigned long)rp, v);
291 return -1;
292 }
293 }
294
295 }
296
297 return (size);
298}
299
300/* ------------------------------------------------------------------------- */
301
302int misc_init_r(void)
303{
304 return(0);
305}
306
307/* ------------------------------------------------------------------------- */
308
309/* bits that can have a special purpose or can be configured as inputs/outputs */
310#define PA_MASK (_BWR(4, 9) | _BWR(12, 15))
311#define PA_ODR_MASK (_BW(9) | _BW(12) | _BW(14))
312#define PA_ODR_VAL 0
313#define PA_GP_INMASK 0
314#define PA_GP_OUTMASK (_BW(5) | _BW(14) | _BW(15))
315#define PA_SP_OUTMASK 0
316#define PA_GP_OUTVAL _BW(5)
317#define PA_SP_OUTVAL 0
318
319#define PB_MASK (_BR(16, 19) | _BR(22, 31))
320#define PB_ODR_MASK PB_MASK
321#define PB_ODR_VAL 0
322#define PB_GP_INMASK 0
323#define PB_GP_OUTMASK (_BR(16, 19) | _BR(26, 27) | _B(31))
324#define PB_SP_OUTMASK _BR(28, 30)
325#define PB_SP_OUTVAL _BR(28, 30)
326#define PB_GP_OUTVAL (_BR(16, 19) | _BR(26, 27) | _B(31))
327
328#define PC_MASK _BWR(4, 15)
329#define PC_SO_MASK (_BWR(6, 11) | _BWR(14, 15))
330#define PC_SO_VAL 0
331#define PC_INT_MASK PC_MASK
332#define PC_INT_VAL 0
333#define PC_GP_INMASK (_BWR(5, 7) | _BWR(9, 10) | _BW(13))
334#define PC_GP_OUTMASK _BW(12)
335#define PC_SP_OUTMASK 0
336#define PC_SP_OUTVAL _BW(12)
337#define PC_GP_OUTVAL 0
338
339#define PD_MASK _BWR(0, 15)
340#define PD_GP_INMASK 0
341#define PD_GP_OUTMASK _BWR(3, 15)
342#define PD_SP_OUTMASK 0
343#define PD_GP_OUTVAL (_BW(3) | _BW(5) | _BW(7) | _BWR(8, 15))
344#define PD_SP_OUTVAL 0
345
346int board_pre_init(void)
347{
348 register volatile immap_t *immap = (immap_t *) CFG_IMMR;
349 register volatile iop8xx_t *ioport = &immap->im_ioport;
350 register volatile cpm8xx_t *cpm = &immap->im_cpm;
351
352 ioport->iop_padat = (ioport->iop_padat & ~PA_MASK) | PA_SP_OUTVAL | PA_GP_OUTVAL;
353 ioport->iop_paodr = (ioport->iop_paodr & ~PA_ODR_MASK) | PA_ODR_VAL;
354 ioport->iop_padir = (ioport->iop_padir & ~PA_GP_INMASK)| PA_SP_OUTMASK | PA_GP_OUTMASK;
355 ioport->iop_papar = (ioport->iop_papar & ~(PA_GP_INMASK & PA_GP_OUTMASK));
356
357 cpm->cp_pbdat = (ioport->iop_padat & ~PB_MASK) | PB_SP_OUTVAL | PB_GP_OUTVAL;
358 cpm->cp_pbodr = (ioport->iop_paodr & ~PB_ODR_MASK) | PB_ODR_VAL;
359 cpm->cp_pbdir = (ioport->iop_padir & ~PB_GP_INMASK)| PB_SP_OUTMASK | PB_GP_OUTMASK;
360 cpm->cp_pbpar = (ioport->iop_papar & ~(PB_GP_INMASK & PB_GP_OUTMASK));
361
362 ioport->iop_pcdat = (ioport->iop_pcdat & ~PC_MASK) | PC_SP_OUTVAL | PC_GP_OUTVAL;
363 ioport->iop_pcdir = (ioport->iop_pcdir & ~PC_GP_INMASK)| PC_SP_OUTMASK | PC_GP_OUTMASK;
364 ioport->iop_pcso = (ioport->iop_pcso & ~PC_SO_MASK) | PC_SO_VAL;
365 ioport->iop_pcint = (ioport->iop_pcint & ~PC_INT_MASK) | PC_INT_VAL;
366 ioport->iop_pcpar = (ioport->iop_pcpar & ~(PC_GP_INMASK & PC_GP_OUTMASK));
367
368 ioport->iop_pddat = (ioport->iop_pddat & ~PD_MASK) | PD_SP_OUTVAL | PD_GP_OUTVAL;
369 ioport->iop_pddir = (ioport->iop_pddir & ~PD_GP_INMASK)| PD_SP_OUTMASK | PD_GP_OUTMASK;
370 ioport->iop_pdpar = (ioport->iop_pdpar & ~(PD_GP_INMASK & PD_GP_OUTMASK));
371
372 return 0;
373}
374