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git01.mediatek.com / filogic / uboot / c5b3ce734b960bd2c43c6b6b7b9d768bedc45063 / . / arch / arm / dts / phycore-imx8mm.dts
blob: c46d3c72ced9ef6c6e4f54298409dd87db0fbf31 [file] [log] [blame]
Teresa Remmet82750c22020-08-21 09:55:53 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 2019-2020 PHYTEC Messtechnik GmbH
4 * Author: Teresa Remmet <t.remmet@phytec.de>
5 */
6
7/dts-v1/;
8
9#include <dt-bindings/net/ti-dp83867.h>
10#include "imx8mm.dtsi"
11
12/ {
13 model = "PHYTEC phyCORE-i.MX8MM";
14 compatible = "phytec,imx8mm-phycore-som", "fsl,imx8mm";
15
16 chosen {
17 stdout-patch = &uart3;
18 };
19
20 reg_usdhc2_vmmc: regulator-usdhc2 {
21 compatible = "regulator-fixed";
22 regulator-name = "VSD_3V3";
23 regulator-min-microvolt = <3300000>;
24 regulator-max-microvolt = <3300000>;
25 startup-delay-us = <100>;
26 off-on-delay-us = <12000>;
27 };
28};
29
30/* ethernet */
31&fec1 {
32 pinctrl-names = "default";
33 pinctrl-0 = <&pinctrl_fec1>;
34 phy-mode = "rgmii-id";
35 phy-handle = <&ethphy0>;
36 phy-reset-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
37 phy-reset-duration = <1>;
38 phy-reset-post-delay = <1>;
39 status = "okay";
40
41 mdio {
42 #address-cells = <1>;
43 #size-cells = <0>;
44
45 ethphy0: ethernet-phy@0 {
46 compatible = "ethernet-phy-ieee802.3-c22";
47 reg = <0x0>;
48 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
49 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
50 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
51 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
52 enet-phy-lane-no-swap;
53 };
54 };
55};
56
57/* i2c eeprom */
58&i2c1 {
59 clock-frequency = <400000>;
60 pinctrl-names = "default", "gpio";
61 pinctrl-0 = <&pinctrl_i2c1>;
62 pinctrl-1 = <&pinctrl_i2c1_gpio>;
63 scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
64 sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
65 status = "okay";
66
67 /* M24C32-D */
68 i2c_eeprom: eeprom@51 {
69 compatible = "atmel,24c32";
70 reg = <0x51>;
71 u-boot,i2c-offset-len = <2>;
72 };
73
74 /* M24C32-D Identification page */
75 i2c_eeprom_id: eeprom@59 {
76 compatible = "atmel,24c32";
77 reg = <0x59>;
78 u-boot,i2c-offset-len = <2>;
79 };
80};
81
82/* debug console */
83&uart3 {
84 pinctrl-names = "default";
85 pinctrl-0 = <&pinctrl_uart3>;
86 status = "okay";
87};
88
89/* sd-card */
90&usdhc2 {
91 pinctrl-names = "default", "state_100mhz", "state_200mhz";
92 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
93 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
94 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
95 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
96 bus-width = <4>;
97 vmmc-supply = <&reg_usdhc2_vmmc>;
98 status = "okay";
99};
100
101/* eMMC */
102&usdhc3 {
103 pinctrl-names = "default", "state_100mhz", "state_200mhz";
104 pinctrl-0 = <&pinctrl_usdhc3>;
105 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
106 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
107 bus-width = <8>;
108 non-removable;
109 status = "okay";
110};
111
112/* watchdog */
113&wdog1 {
114 pinctrl-names = "default";
115 pinctrl-0 = <&pinctrl_wdog>;
116 fsl,ext-reset-output;
117 status = "okay";
118};
119
120&iomuxc {
121 pinctrl-names = "default";
122
123 pinctrl_fec1: fec1grp {
124 fsl,pins = <
125 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
126 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
127 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
128 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
129 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
130 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
131 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
132 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
133 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
134 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
135 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
136 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
137 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
138 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
139 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
140 >;
141 };
142
143 pinctrl_i2c1: i2c1grp {
144 fsl,pins = <
145 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
146 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
147 >;
148 };
149
150 pinctrl_i2c1_gpio: i2c1grp-gpio {
151 fsl,pins = <
152 MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1c3
153 MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1c3
154 >;
155 };
156
157 pinctrl_uart3: uart3grp {
158 fsl,pins = <
159 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49
160 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49
161 >;
162 };
163
164 pinctrl_usdhc2_gpio: usdhc2grpgpio {
165 fsl,pins = <
166 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
167 >;
168 };
169
170 pinctrl_usdhc2: usdhc2grp {
171 fsl,pins = <
172 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
173 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
174 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
175 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
176 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
177 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
178 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
179 >;
180 };
181
182 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
183 fsl,pins = <
184 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
185 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
186 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
187 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
188 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
189 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
190 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
191 >;
192 };
193
194 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
195 fsl,pins = <
196 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
197 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
198 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
199 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
200 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
201 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
202 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
203 >;
204 };
205
206 pinctrl_usdhc3: usdhc3grp {
207 fsl,pins = <
208 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190
209 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
210 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
211 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
212 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
213 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
214 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
215 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
216 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
217 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
218 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
219 >;
220 };
221
222 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
223 fsl,pins = <
224 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194
225 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
226 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
227 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
228 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
229 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
230 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
231 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
232 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
233 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
234 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
235 >;
236 };
237
238 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
239 fsl,pins = <
240 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196
241 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
242 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
243 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
244 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
245 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
246 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
247 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
248 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
249 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
250 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
251 >;
252 };
253
254 pinctrl_wdog: wdoggrp {
255 fsl,pins = <
256 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
257 >;
258 };
259};