| Dalon Westergreen | 7a0fe0d | 2017-04-18 08:11:16 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2017, Intel Corporation |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | #ifndef __CONFIG_TERASIC_DE10_H__ |
| 7 | #define __CONFIG_TERASIC_DE10_H__ |
| 8 | |
| 9 | #include <asm/arch/base_addr_ac5.h> |
| 10 | |
| Dalon Westergreen | 7a0fe0d | 2017-04-18 08:11:16 -0700 | [diff] [blame] | 11 | /* Memory configurations */ |
| 12 | #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */ |
| 13 | |
| 14 | /* Booting Linux */ |
| 15 | #define CONFIG_LOADADDR 0x01000000 |
| 16 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
| 17 | |
| 18 | /* Ethernet on SoC (EMAC) */ |
| Dalon Westergreen | 7a0fe0d | 2017-04-18 08:11:16 -0700 | [diff] [blame] | 19 | |
| Dalon Westergreen | 7a0fe0d | 2017-04-18 08:11:16 -0700 | [diff] [blame] | 20 | /* The rest of the configuration is shared */ |
| 21 | #include <configs/socfpga_common.h> |
| 22 | |
| 23 | #endif /* __CONFIG_TERASIC_DE10_H__ */ |