Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / c53591c20125eae7c0aff08c980aad6ca95be838 / . / configs / chromebit_mickey_defconfig
blob: c74a006bc9f8e768717448b516d88c02fcfdce8f [file] [log] [blame]
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]1CONFIG_ARM=y
2CONFIG_ARCH_ROCKCHIP=y
3CONFIG_SYS_MALLOC_F_LEN=0x2000
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]4CONFIG_ROCKCHIP_RK3288=y
Tom Rini9834b902017-03-13 13:48:42 -0400[diff] [blame]5# CONFIG_SPL_MMC_SUPPORT is not set
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]6CONFIG_TARGET_CHROMEBIT_MICKEY=y
7CONFIG_SPL_SPI_FLASH_SUPPORT=y
8CONFIG_SPL_SPI_SUPPORT=y
9CONFIG_SPL_STACK_R_ADDR=0x80000
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]10CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-mickey"
Tom Rini256aa742017-06-19 09:47:40 -0400[diff] [blame]11CONFIG_DEBUG_UART=y
Tom Rinib5bf5622017-08-25 17:50:27 -0400[diff] [blame]12# CONFIG_ANDROID_BOOT_IMAGE is not set
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]13# CONFIG_DISPLAY_CPUINFO is not set
14CONFIG_SPL_STACK_R=y
15CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
Tom Rinib5bf5622017-08-25 17:50:27 -0400[diff] [blame]16CONFIG_FASTBOOT_FLASH=y
17CONFIG_FASTBOOT_FLASH_MMC_DEV=0
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]18CONFIG_CMD_GPIO=y
Patrick Delaunay73287092017-01-27 11:00:42 +0100[diff] [blame]19CONFIG_CMD_GPT=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]20CONFIG_CMD_I2C=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]21CONFIG_CMD_MMC=y
22CONFIG_CMD_SF=y
Simon Glass86b1b652017-08-04 16:34:46 -0600[diff] [blame]23CONFIG_CMD_SF_TEST=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]24CONFIG_CMD_SPI=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]25# CONFIG_CMD_SETEXPR is not set
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]26CONFIG_CMD_CACHE=y
27CONFIG_CMD_TIME=y
28CONFIG_CMD_PMIC=y
29CONFIG_CMD_REGULATOR=y
Patrick Delaunayf7e07722017-01-27 11:00:37 +0100[diff] [blame]30# CONFIG_SPL_DOS_PARTITION is not set
Patrick Delaunay21d3bce2017-01-27 11:00:38 +0100[diff] [blame]31# CONFIG_SPL_ISO_PARTITION is not set
Patrick Delaunay8a4f2bd2017-01-27 11:00:41 +0100[diff] [blame]32# CONFIG_SPL_EFI_PARTITION is not set
Patrick Delaunay73287092017-01-27 11:00:42 +0100[diff] [blame]33CONFIG_SPL_PARTITION_UUIDS=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]34CONFIG_SPL_OF_CONTROL=y
35CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
Masahiro Yamada74f09b82016-12-07 22:10:25 +0900[diff] [blame]36CONFIG_SPL_OF_PLATDATA=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]37CONFIG_REGMAP=y
38CONFIG_SPL_REGMAP=y
39CONFIG_SYSCON=y
40CONFIG_SPL_SYSCON=y
41# CONFIG_SPL_SIMPLE_BUS is not set
42CONFIG_CLK=y
43CONFIG_SPL_CLK=y
44CONFIG_ROCKCHIP_GPIO=y
45CONFIG_I2C_CROS_EC_TUNNEL=y
46CONFIG_SYS_I2C_ROCKCHIP=y
47CONFIG_I2C_MUX=y
Masahiro Yamada74f09b82016-12-07 22:10:25 +0900[diff] [blame]48CONFIG_DM_KEYBOARD=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]49CONFIG_CROS_EC_KEYB=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]50CONFIG_CROS_EC=y
51CONFIG_CROS_EC_SPI=y
52CONFIG_PWRSEQ=y
Masahiro Yamada7942e912017-01-10 13:32:04 +0900[diff] [blame]53CONFIG_MMC_DW=y
Masahiro Yamadadc607f82017-01-10 13:32:03 +0900[diff] [blame]54CONFIG_MMC_DW_ROCKCHIP=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]55CONFIG_PINCTRL=y
56CONFIG_SPL_PINCTRL=y
57# CONFIG_SPL_PINCTRL_FULL is not set
Philipp Tomsicha1dcf3c2017-04-19 16:46:37 +0200[diff] [blame]58CONFIG_PINCTRL_ROCKCHIP_RK3288=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]59CONFIG_DM_PMIC=y
60# CONFIG_SPL_PMIC_CHILDREN is not set
Jacob Chen614704b2017-05-02 14:54:52 +0800[diff] [blame]61CONFIG_PMIC_RK8XX=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]62CONFIG_SPL_DM_REGULATOR=y
63CONFIG_DM_REGULATOR_FIXED=y
Jacob Chen614704b2017-05-02 14:54:52 +0800[diff] [blame]64CONFIG_REGULATOR_RK8XX=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]65CONFIG_PWM_ROCKCHIP=y
66CONFIG_RAM=y
67CONFIG_SPL_RAM=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]68CONFIG_DEBUG_UART_BASE=0xff690000
69CONFIG_DEBUG_UART_CLOCK=24000000
70CONFIG_DEBUG_UART_SHIFT=2
71CONFIG_SYS_NS16550=y
72CONFIG_ROCKCHIP_SERIAL=y
73CONFIG_ROCKCHIP_SPI=y
74CONFIG_SYSRESET=y
Tom Rini504997e2017-08-25 17:50:26 -0400[diff] [blame]75CONFIG_USB=y
76CONFIG_USB_GADGET=y
Maxime Ripard7f78b9d2017-09-07 08:58:08 +0200[diff] [blame]77CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
78CONFIG_USB_GADGET_VENDOR_NUM=0x2207
79CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
Tom Rini504997e2017-08-25 17:50:26 -0400[diff] [blame]80CONFIG_USB_GADGET_DWC2_OTG=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]81CONFIG_DM_VIDEO=y
82CONFIG_DISPLAY=y
83CONFIG_VIDEO_ROCKCHIP=y
eric.gao@rock-chips.com735ddea2017-04-17 22:24:23 +0800[diff] [blame]84CONFIG_DISPLAY_ROCKCHIP_HDMI=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]85CONFIG_USE_TINY_PRINTF=y
86CONFIG_CMD_DHRYSTONE=y
87CONFIG_ERRNO_STR=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]88# CONFIG_SPL_OF_LIBFDT is not set