| Vignesh Raghavendra | bf9bca7 | 2022-05-25 13:38:49 +0530 | [diff] [blame] | 1 | CONFIG_ARM=y |
| 2 | CONFIG_ARCH_K3=y |
| 3 | CONFIG_SYS_MALLOC_F_LEN=0x8000 |
| 4 | CONFIG_SPL_LIBCOMMON_SUPPORT=y |
| 5 | CONFIG_SPL_LIBGENERIC_SUPPORT=y |
| 6 | CONFIG_NR_DRAM_BANKS=2 |
| 7 | CONFIG_SOC_K3_AM625=y |
| 8 | CONFIG_K3_ATF_LOAD_ADDR=0x9e780000 |
| 9 | CONFIG_TARGET_AM625_A53_EVM=y |
| 10 | CONFIG_DEFAULT_DEVICE_TREE="k3-am625-sk" |
| 11 | CONFIG_SPL_TEXT_BASE=0x80080000 |
| 12 | CONFIG_SPL_MMC=y |
| 13 | CONFIG_SPL_SERIAL=y |
| 14 | CONFIG_SPL_STACK_R_ADDR=0x82000000 |
| 15 | CONFIG_SPL_FS_FAT=y |
| 16 | CONFIG_SPL_LIBDISK_SUPPORT=y |
| Dhruva Gole | c52e8d3 | 2022-10-27 20:23:11 +0530 | [diff] [blame^] | 17 | CONFIG_SPL_SPI=y |
| Vignesh Raghavendra | bf9bca7 | 2022-05-25 13:38:49 +0530 | [diff] [blame] | 18 | CONFIG_DISTRO_DEFAULTS=y |
| 19 | CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y |
| 20 | CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000 |
| 21 | # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set |
| 22 | CONFIG_SPL_LOAD_FIT=y |
| 23 | CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 |
| 24 | CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern" |
| 25 | CONFIG_SPL_MAX_SIZE=0x58000 |
| 26 | CONFIG_SPL_HAS_BSS_LINKER_SECTION=y |
| 27 | CONFIG_SPL_BSS_START_ADDR=0x80a00000 |
| 28 | CONFIG_SPL_BSS_MAX_SIZE=0x80000 |
| 29 | CONFIG_SPL_SYS_MALLOC_SIMPLE=y |
| 30 | CONFIG_SPL_STACK_R=y |
| 31 | CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y |
| 32 | CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 |
| 33 | CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" |
| 34 | CONFIG_SPL_DM_MAILBOX=y |
| Dhruva Gole | c52e8d3 | 2022-10-27 20:23:11 +0530 | [diff] [blame^] | 35 | CONFIG_SPL_DM_SPI=y |
| 36 | CONFIG_SPL_DM_SPI_FLASH=y |
| Vignesh Raghavendra | bf9bca7 | 2022-05-25 13:38:49 +0530 | [diff] [blame] | 37 | CONFIG_SPL_POWER_DOMAIN=y |
| Dhruva Gole | c52e8d3 | 2022-10-27 20:23:11 +0530 | [diff] [blame^] | 38 | # CONFIG_SPL_SPI_FLASH_TINY is not set |
| 39 | CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y |
| 40 | CONFIG_SPL_SPI_FLASH_SUPPORT=y |
| 41 | CONFIG_SPL_SPI_LOAD=y |
| 42 | CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000 |
| Vignesh Raghavendra | bf9bca7 | 2022-05-25 13:38:49 +0530 | [diff] [blame] | 43 | CONFIG_SPL_YMODEM_SUPPORT=y |
| Tom Rini | f3c2f99 | 2022-06-25 19:29:46 -0400 | [diff] [blame] | 44 | CONFIG_SYS_BOOTM_LEN=0x800000 |
| Vignesh Raghavendra | bf9bca7 | 2022-05-25 13:38:49 +0530 | [diff] [blame] | 45 | CONFIG_CMD_MMC=y |
| 46 | CONFIG_OF_CONTROL=y |
| 47 | CONFIG_SPL_OF_CONTROL=y |
| 48 | CONFIG_MULTI_DTB_FIT=y |
| 49 | CONFIG_SPL_MULTI_DTB_FIT=y |
| 50 | CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y |
| 51 | CONFIG_NET_RANDOM_ETHADDR=y |
| Vignesh Raghavendra | bf9bca7 | 2022-05-25 13:38:49 +0530 | [diff] [blame] | 52 | CONFIG_SPL_DM=y |
| 53 | CONFIG_SPL_DM_SEQ_ALIAS=y |
| 54 | CONFIG_REGMAP=y |
| 55 | CONFIG_SPL_REGMAP=y |
| 56 | CONFIG_SPL_OF_TRANSLATE=y |
| 57 | CONFIG_CLK=y |
| 58 | CONFIG_SPL_CLK=y |
| 59 | CONFIG_CLK_TI_SCI=y |
| 60 | CONFIG_TI_SCI_PROTOCOL=y |
| 61 | CONFIG_DM_MAILBOX=y |
| 62 | CONFIG_K3_SEC_PROXY=y |
| 63 | CONFIG_MMC_SDHCI=y |
| 64 | CONFIG_MMC_SDHCI_ADMA=y |
| 65 | CONFIG_SPL_MMC_SDHCI_ADMA=y |
| 66 | CONFIG_MMC_SDHCI_AM654=y |
| Dhruva Gole | c52e8d3 | 2022-10-27 20:23:11 +0530 | [diff] [blame^] | 67 | CONFIG_DM_SPI_FLASH=y |
| 68 | CONFIG_SF_DEFAULT_MODE=0x3 |
| 69 | CONFIG_SF_DEFAULT_SPEED=25000000 |
| 70 | CONFIG_SPI_FLASH_SFDP_SUPPORT=y |
| 71 | CONFIG_SPI_FLASH_SOFT_RESET=y |
| 72 | CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y |
| 73 | CONFIG_SPI_FLASH_SPANSION=y |
| 74 | CONFIG_SPI_FLASH_S28HS512T=y |
| Vignesh Raghavendra | bf9bca7 | 2022-05-25 13:38:49 +0530 | [diff] [blame] | 75 | CONFIG_PINCTRL=y |
| 76 | CONFIG_SPL_PINCTRL=y |
| 77 | CONFIG_PINCTRL_SINGLE=y |
| 78 | CONFIG_POWER_DOMAIN=y |
| 79 | CONFIG_TI_SCI_POWER_DOMAIN=y |
| 80 | CONFIG_K3_SYSTEM_CONTROLLER=y |
| 81 | CONFIG_REMOTEPROC_TI_K3_ARM64=y |
| 82 | CONFIG_DM_RESET=y |
| 83 | CONFIG_RESET_TI_SCI=y |
| 84 | CONFIG_DM_SERIAL=y |
| 85 | CONFIG_SOC_DEVICE=y |
| 86 | CONFIG_SOC_DEVICE_TI_K3=y |
| 87 | CONFIG_SOC_TI=y |
| Dhruva Gole | c52e8d3 | 2022-10-27 20:23:11 +0530 | [diff] [blame^] | 88 | CONFIG_SPI=y |
| 89 | CONFIG_DM_SPI=y |
| 90 | CONFIG_CADENCE_QSPI=y |
| Vignesh Raghavendra | bf9bca7 | 2022-05-25 13:38:49 +0530 | [diff] [blame] | 91 | CONFIG_SYSRESET=y |
| 92 | CONFIG_SPL_SYSRESET=y |
| 93 | CONFIG_SYSRESET_TI_SCI=y |
| 94 | CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 |
| 95 | CONFIG_OF_LIBFDT_OVERLAY=y |