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git01.mediatek.com / filogic / uboot / c49678e1b8478d239cb84efb4e9ed766b0e8f89d / . / board / sunxi / dram_sun4i_auto.c
blob: 547d1c0cb4dea3fe2a261b47f0e9c8769f302824 [file] [log] [blame]
Hans de Goede7f15c692014-07-26 16:51:08 +0200[diff] [blame]1#include <common.h>
Simon Glass97589732020-05-10 11:40:02 -0600[diff] [blame]2#include <init.h>
Hans de Goede7f15c692014-07-26 16:51:08 +0200[diff] [blame]3#include <asm/arch/dram.h>
4
5static struct dram_para dram_para = {
Hans de Goede59d9fc72015-01-17 14:24:55 +0100[diff] [blame]6 .clock = CONFIG_DRAM_CLK,
Giulio Benetti0fe7a5f2021-12-03 00:57:54 +0100[diff] [blame]7 .type = DRAM_MEMORY_TYPE_DDR3,
Hans de Goede7f15c692014-07-26 16:51:08 +0200[diff] [blame]8 .rank_num = 1,
Hans de Goede59d9fc72015-01-17 14:24:55 +0100[diff] [blame]9 .density = 0,
10 .io_width = 0,
11 .bus_width = 0,
Hans de Goede59d9fc72015-01-17 14:24:55 +0100[diff] [blame]12 .zq = CONFIG_DRAM_ZQ,
Hans de Goedeffdc05c2015-05-13 15:00:46 +0200[diff] [blame]13 .odt_en = IS_ENABLED(CONFIG_DRAM_ODT_EN),
Hans de Goede59d9fc72015-01-17 14:24:55 +0100[diff] [blame]14 .size = 0,
Siarhei Siamashka9900db12015-02-01 00:27:05 +0200[diff] [blame]15#ifdef CONFIG_DRAM_TIMINGS_VENDOR_MAGIC
16 .cas = 6,
Hans de Goede7f15c692014-07-26 16:51:08 +0200[diff] [blame]17 .tpr0 = 0x30926692,
18 .tpr1 = 0x1090,
19 .tpr2 = 0x1a0c8,
Siarhei Siamashka9900db12015-02-01 00:27:05 +0200[diff] [blame]20 .emr2 = 0,
21#else
22# include "dram_timings_sun4i.h"
Siarhei Siamashka47359bb2015-02-01 00:27:06 +0200[diff] [blame]23 .active_windowing = 1,
Siarhei Siamashka9900db12015-02-01 00:27:05 +0200[diff] [blame]24#endif
Siarhei Siamashka47359bb2015-02-01 00:27:06 +0200[diff] [blame]25 .tpr3 = CONFIG_DRAM_TPR3,
Hans de Goede7f15c692014-07-26 16:51:08 +0200[diff] [blame]26 .tpr4 = 0,
27 .tpr5 = 0,
Hans de Goede59d9fc72015-01-17 14:24:55 +0100[diff] [blame]28 .emr1 = CONFIG_DRAM_EMR1,
Hans de Goede7f15c692014-07-26 16:51:08 +0200[diff] [blame]29 .emr3 = 0,
Siarhei Siamashka47359bb2015-02-01 00:27:06 +0200[diff] [blame]30 .dqs_gating_delay = CONFIG_DRAM_DQS_GATING_DELAY,
Hans de Goede7f15c692014-07-26 16:51:08 +0200[diff] [blame]31};
32
33unsigned long sunxi_dram_init(void)
34{
35 return dramc_init(&dram_para);
36}