Blame - drivers/ram/k3-ddrss/am62a/lpddr4_pi_macros.h - filogic/uboot

Bryan Brattlof

85b5cc8

2022-10-24 16:53:28 -0500

[diff] [blame]

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/* SPDX-License-Identifier: BSD-3-Clause */

/*

* Cadence DDR Driver

*

*/

#ifndef REG_LPDDR4_PI_MACROS_H_

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#define REG_LPDDR4_PI_MACROS_H_

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#define LPDDR4__DENALI_PI_0_READ_MASK 0x00000F01U

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#define LPDDR4__DENALI_PI_0_WRITE_MASK 0x00000F01U

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#define LPDDR4__DENALI_PI_0__PI_START_MASK 0x00000001U

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#define LPDDR4__DENALI_PI_0__PI_START_SHIFT 0U

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#define LPDDR4__DENALI_PI_0__PI_START_WIDTH 1U

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#define LPDDR4__DENALI_PI_0__PI_START_WOCLR 0U

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#define LPDDR4__DENALI_PI_0__PI_START_WOSET 0U

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#define LPDDR4__PI_START__REG DENALI_PI_0

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#define LPDDR4__PI_START__FLD LPDDR4__DENALI_PI_0__PI_START

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#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_MASK 0x00000F00U

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#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_SHIFT 8U

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#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_WIDTH 4U

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#define LPDDR4__PI_DRAM_CLASS__REG DENALI_PI_0

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#define LPDDR4__PI_DRAM_CLASS__FLD LPDDR4__DENALI_PI_0__PI_DRAM_CLASS

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#define LPDDR4__DENALI_PI_1_READ_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_1_WRITE_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_1__PI_VERSION_0_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_1__PI_VERSION_0_SHIFT 0U

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#define LPDDR4__DENALI_PI_1__PI_VERSION_0_WIDTH 32U

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#define LPDDR4__PI_VERSION_0__REG DENALI_PI_1

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#define LPDDR4__PI_VERSION_0__FLD LPDDR4__DENALI_PI_1__PI_VERSION_0

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#define LPDDR4__DENALI_PI_2_READ_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_2_WRITE_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_2__PI_VERSION_1_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_2__PI_VERSION_1_SHIFT 0U

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#define LPDDR4__DENALI_PI_2__PI_VERSION_1_WIDTH 32U

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#define LPDDR4__PI_VERSION_1__REG DENALI_PI_2

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#define LPDDR4__PI_VERSION_1__FLD LPDDR4__DENALI_PI_2__PI_VERSION_1

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#define LPDDR4__DENALI_PI_3_READ_MASK 0x0101FFFFU

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#define LPDDR4__DENALI_PI_3_WRITE_MASK 0x0101FFFFU

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#define LPDDR4__DENALI_PI_3__PI_ID_MASK 0x0000FFFFU

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#define LPDDR4__DENALI_PI_3__PI_ID_SHIFT 0U

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#define LPDDR4__DENALI_PI_3__PI_ID_WIDTH 16U

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#define LPDDR4__PI_ID__REG DENALI_PI_3

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#define LPDDR4__PI_ID__FLD LPDDR4__DENALI_PI_3__PI_ID

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#define LPDDR4__DENALI_PI_3__PI_RELEASE_DFI_MASK 0x00010000U

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#define LPDDR4__DENALI_PI_3__PI_RELEASE_DFI_SHIFT 16U

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#define LPDDR4__DENALI_PI_3__PI_RELEASE_DFI_WIDTH 1U

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#define LPDDR4__DENALI_PI_3__PI_RELEASE_DFI_WOCLR 0U

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#define LPDDR4__DENALI_PI_3__PI_RELEASE_DFI_WOSET 0U

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#define LPDDR4__PI_RELEASE_DFI__REG DENALI_PI_3

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#define LPDDR4__PI_RELEASE_DFI__FLD LPDDR4__DENALI_PI_3__PI_RELEASE_DFI

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#define LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ_MASK 0x01000000U

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#define LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ_SHIFT 24U

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#define LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ_WIDTH 1U

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#define LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ_WOCLR 0U

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#define LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ_WOSET 0U

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#define LPDDR4__PI_NORMAL_LVL_SEQ__REG DENALI_PI_3

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#define LPDDR4__PI_NORMAL_LVL_SEQ__FLD LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ

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#define LPDDR4__DENALI_PI_4_READ_MASK 0xFFFF0301U

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#define LPDDR4__DENALI_PI_4_WRITE_MASK 0xFFFF0301U

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#define LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN_MASK 0x00000001U

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#define LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN_SHIFT 0U

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#define LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN_WIDTH 1U

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#define LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN_WOCLR 0U

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#define LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN_WOSET 0U

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#define LPDDR4__PI_INIT_LVL_EN__REG DENALI_PI_4

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#define LPDDR4__PI_INIT_LVL_EN__FLD LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN

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#define LPDDR4__DENALI_PI_4__PI_NOTCARE_PHYUPD_MASK 0x00000300U

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#define LPDDR4__DENALI_PI_4__PI_NOTCARE_PHYUPD_SHIFT 8U

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#define LPDDR4__DENALI_PI_4__PI_NOTCARE_PHYUPD_WIDTH 2U

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#define LPDDR4__PI_NOTCARE_PHYUPD__REG DENALI_PI_4

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#define LPDDR4__PI_NOTCARE_PHYUPD__FLD LPDDR4__DENALI_PI_4__PI_NOTCARE_PHYUPD

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#define LPDDR4__DENALI_PI_4__PI_TCMD_GAP_MASK 0xFFFF0000U

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#define LPDDR4__DENALI_PI_4__PI_TCMD_GAP_SHIFT 16U

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#define LPDDR4__DENALI_PI_4__PI_TCMD_GAP_WIDTH 16U

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#define LPDDR4__PI_TCMD_GAP__REG DENALI_PI_4

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#define LPDDR4__PI_TCMD_GAP__FLD LPDDR4__DENALI_PI_4__PI_TCMD_GAP

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#define LPDDR4__DENALI_PI_5_READ_MASK 0x030100FFU

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#define LPDDR4__DENALI_PI_5_WRITE_MASK 0x030100FFU

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#define LPDDR4__DENALI_PI_5__PI_RESERVED0_MASK 0x000000FFU

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#define LPDDR4__DENALI_PI_5__PI_RESERVED0_SHIFT 0U

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#define LPDDR4__DENALI_PI_5__PI_RESERVED0_WIDTH 8U

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#define LPDDR4__PI_RESERVED0__REG DENALI_PI_5

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#define LPDDR4__PI_RESERVED0__FLD LPDDR4__DENALI_PI_5__PI_RESERVED0

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#define LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ_MASK 0x00000100U

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#define LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ_SHIFT 8U

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#define LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ_WIDTH 1U

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#define LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ_WOCLR 0U

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#define LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ_WOSET 0U

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#define LPDDR4__PI_TRAIN_ALL_FREQ_REQ__REG DENALI_PI_5

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#define LPDDR4__PI_TRAIN_ALL_FREQ_REQ__FLD LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ

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#define LPDDR4__DENALI_PI_5__PI_DFI_VERSION_MASK 0x00010000U

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#define LPDDR4__DENALI_PI_5__PI_DFI_VERSION_SHIFT 16U

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#define LPDDR4__DENALI_PI_5__PI_DFI_VERSION_WIDTH 1U

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#define LPDDR4__DENALI_PI_5__PI_DFI_VERSION_WOCLR 0U

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#define LPDDR4__DENALI_PI_5__PI_DFI_VERSION_WOSET 0U

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#define LPDDR4__PI_DFI_VERSION__REG DENALI_PI_5

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#define LPDDR4__PI_DFI_VERSION__FLD LPDDR4__DENALI_PI_5__PI_DFI_VERSION

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#define LPDDR4__DENALI_PI_5__PI_DFI_PHYMSTR_TYPE_MASK 0x03000000U

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#define LPDDR4__DENALI_PI_5__PI_DFI_PHYMSTR_TYPE_SHIFT 24U

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#define LPDDR4__DENALI_PI_5__PI_DFI_PHYMSTR_TYPE_WIDTH 2U

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#define LPDDR4__PI_DFI_PHYMSTR_TYPE__REG DENALI_PI_5

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#define LPDDR4__PI_DFI_PHYMSTR_TYPE__FLD LPDDR4__DENALI_PI_5__PI_DFI_PHYMSTR_TYPE

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#define LPDDR4__DENALI_PI_6_READ_MASK 0x00000101U

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#define LPDDR4__DENALI_PI_6_WRITE_MASK 0x00000101U

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#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R_MASK 0x00000001U

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#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R_SHIFT 0U

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#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R_WIDTH 1U

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#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R_WOCLR 0U

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#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R_WOSET 0U

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#define LPDDR4__PI_DFI_PHYMSTR_CS_STATE_R__REG DENALI_PI_6

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#define LPDDR4__PI_DFI_PHYMSTR_CS_STATE_R__FLD LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R

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#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R_MASK 0x00000100U

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#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R_SHIFT 8U

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#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R_WIDTH 1U

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#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R_WOCLR 0U

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#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R_WOSET 0U

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#define LPDDR4__PI_DFI_PHYMSTR_STATE_SEL_R__REG DENALI_PI_6

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#define LPDDR4__PI_DFI_PHYMSTR_STATE_SEL_R__FLD LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R

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#define LPDDR4__DENALI_PI_7_READ_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_7_WRITE_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_7__PI_TDFI_PHYMSTR_MAX_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_7__PI_TDFI_PHYMSTR_MAX_SHIFT 0U

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#define LPDDR4__DENALI_PI_7__PI_TDFI_PHYMSTR_MAX_WIDTH 32U

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#define LPDDR4__PI_TDFI_PHYMSTR_MAX__REG DENALI_PI_7

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#define LPDDR4__PI_TDFI_PHYMSTR_MAX__FLD LPDDR4__DENALI_PI_7__PI_TDFI_PHYMSTR_MAX

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#define LPDDR4__DENALI_PI_8_READ_MASK 0x000FFFFFU

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#define LPDDR4__DENALI_PI_8_WRITE_MASK 0x000FFFFFU

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#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_RESP_MASK 0x000FFFFFU

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#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_RESP_SHIFT 0U

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#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_RESP_WIDTH 20U

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#define LPDDR4__PI_TDFI_PHYMSTR_RESP__REG DENALI_PI_8

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#define LPDDR4__PI_TDFI_PHYMSTR_RESP__FLD LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_RESP

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#define LPDDR4__DENALI_PI_9_READ_MASK 0x000FFFFFU

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#define LPDDR4__DENALI_PI_9_WRITE_MASK 0x000FFFFFU

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#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYUPD_RESP_MASK 0x000FFFFFU

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#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYUPD_RESP_SHIFT 0U

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#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYUPD_RESP_WIDTH 20U

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#define LPDDR4__PI_TDFI_PHYUPD_RESP__REG DENALI_PI_9

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#define LPDDR4__PI_TDFI_PHYUPD_RESP__FLD LPDDR4__DENALI_PI_9__PI_TDFI_PHYUPD_RESP

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#define LPDDR4__DENALI_PI_10_READ_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_10_WRITE_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_MAX_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_MAX_SHIFT 0U

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#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_MAX_WIDTH 32U

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#define LPDDR4__PI_TDFI_PHYUPD_MAX__REG DENALI_PI_10

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#define LPDDR4__PI_TDFI_PHYUPD_MAX__FLD LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_MAX

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#define LPDDR4__DENALI_PI_11_READ_MASK 0x0000011FU

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#define LPDDR4__DENALI_PI_11_WRITE_MASK 0x0000011FU

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#define LPDDR4__DENALI_PI_11__PI_INIT_WORK_FREQ_MASK 0x0000001FU

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#define LPDDR4__DENALI_PI_11__PI_INIT_WORK_FREQ_SHIFT 0U

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#define LPDDR4__DENALI_PI_11__PI_INIT_WORK_FREQ_WIDTH 5U

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#define LPDDR4__PI_INIT_WORK_FREQ__REG DENALI_PI_11

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#define LPDDR4__PI_INIT_WORK_FREQ__FLD LPDDR4__DENALI_PI_11__PI_INIT_WORK_FREQ

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#define LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY_MASK 0x00000100U

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#define LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY_SHIFT 8U

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#define LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY_WIDTH 1U

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#define LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY_WOCLR 0U

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#define LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY_WOSET 0U

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#define LPDDR4__PI_INIT_DFS_CALVL_ONLY__REG DENALI_PI_11

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#define LPDDR4__PI_INIT_DFS_CALVL_ONLY__FLD LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY

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#define LPDDR4__DENALI_PI_12_READ_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_12_WRITE_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_MASK 0xFFFFFFFFU

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#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_SHIFT 0U

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#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_WIDTH 32U

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#define LPDDR4__PI_FREQ_MAP__REG DENALI_PI_12

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#define LPDDR4__PI_FREQ_MAP__FLD LPDDR4__DENALI_PI_12__PI_FREQ_MAP

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#define LPDDR4__DENALI_PI_13_READ_MASK 0x010F0101U

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#define LPDDR4__DENALI_PI_13_WRITE_MASK 0x010F0101U

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#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_MASK 0x00000001U

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#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_SHIFT 0U

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#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WIDTH 1U

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#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WOCLR 0U

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#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WOSET 0U

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#define LPDDR4__PI_SW_RST_N__REG DENALI_PI_13

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#define LPDDR4__PI_SW_RST_N__FLD LPDDR4__DENALI_PI_13__PI_SW_RST_N

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#define LPDDR4__DENALI_PI_13__PI_RESERVED1_MASK 0x00000100U

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#define LPDDR4__DENALI_PI_13__PI_RESERVED1_SHIFT 8U

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#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WIDTH 1U

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#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WOCLR 0U

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#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WOSET 0U

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#define LPDDR4__PI_RESERVED1__REG DENALI_PI_13

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#define LPDDR4__PI_RESERVED1__FLD LPDDR4__DENALI_PI_13__PI_RESERVED1

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#define LPDDR4__DENALI_PI_13__PI_CS_MAP_MASK 0x000F0000U

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#define LPDDR4__DENALI_PI_13__PI_CS_MAP_SHIFT 16U

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#define LPDDR4__DENALI_PI_13__PI_CS_MAP_WIDTH 4U

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#define LPDDR4__PI_CS_MAP__REG DENALI_PI_13

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#define LPDDR4__PI_CS_MAP__FLD LPDDR4__DENALI_PI_13__PI_CS_MAP

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#define LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL_MASK 0x01000000U

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#define LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL_SHIFT 24U

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#define LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL_WIDTH 1U

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#define LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL_WOCLR 0U

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#define LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL_WOSET 0U

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#define LPDDR4__PI_SWLVL_CS_SEL__REG DENALI_PI_13

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#define LPDDR4__PI_SWLVL_CS_SEL__FLD LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL

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#define LPDDR4__DENALI_PI_14_READ_MASK 0x0F011F0FU

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#define LPDDR4__DENALI_PI_14_WRITE_MASK 0x0F011F0FU

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#define LPDDR4__DENALI_PI_14__PI_CS_MASK_MASK 0x0000000FU

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#define LPDDR4__DENALI_PI_14__PI_CS_MASK_SHIFT 0U

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#define LPDDR4__DENALI_PI_14__PI_CS_MASK_WIDTH 4U

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#define LPDDR4__PI_CS_MASK__REG DENALI_PI_14

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#define LPDDR4__PI_CS_MASK__FLD LPDDR4__DENALI_PI_14__PI_CS_MASK

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#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_MASK 0x00001F00U

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#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_SHIFT 8U

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#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_WIDTH 5U

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#define LPDDR4__PI_RANK_NUM_PER_CKE__REG DENALI_PI_14

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#define LPDDR4__PI_RANK_NUM_PER_CKE__FLD LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE

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#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_MASK 0x00010000U

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#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_SHIFT 16U

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#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WIDTH 1U

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#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WOCLR 0U

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#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WOSET 0U

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#define LPDDR4__PI_SRX_LVL_TARGET_CS_EN__REG DENALI_PI_14

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#define LPDDR4__PI_SRX_LVL_TARGET_CS_EN__FLD LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN

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#define LPDDR4__DENALI_PI_14__PI_TMRR_MASK 0x0F000000U

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#define LPDDR4__DENALI_PI_14__PI_TMRR_SHIFT 24U

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#define LPDDR4__DENALI_PI_14__PI_TMRR_WIDTH 4U

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#define LPDDR4__PI_TMRR__REG DENALI_PI_14

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#define LPDDR4__PI_TMRR__FLD LPDDR4__DENALI_PI_14__PI_TMRR

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#define LPDDR4__DENALI_PI_15_READ_MASK 0x0101070FU

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#define LPDDR4__DENALI_PI_15_WRITE_MASK 0x0101070FU

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#define LPDDR4__DENALI_PI_15__PI_TMPRR_MASK 0x0000000FU

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#define LPDDR4__DENALI_PI_15__PI_TMPRR_SHIFT 0U

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#define LPDDR4__DENALI_PI_15__PI_TMPRR_WIDTH 4U

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#define LPDDR4__PI_TMPRR__REG DENALI_PI_15

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#define LPDDR4__PI_TMPRR__FLD LPDDR4__DENALI_PI_15__PI_TMPRR

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#define LPDDR4__DENALI_PI_15__PI_VRCG_EN_MASK 0x00000700U

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#define LPDDR4__DENALI_PI_15__PI_VRCG_EN_SHIFT 8U

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#define LPDDR4__DENALI_PI_15__PI_VRCG_EN_WIDTH 3U

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#define LPDDR4__PI_VRCG_EN__REG DENALI_PI_15

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#define LPDDR4__PI_VRCG_EN__FLD LPDDR4__DENALI_PI_15__PI_VRCG_EN

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#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_MASK 0x00010000U

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#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_SHIFT 16U

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#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WIDTH 1U

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#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WOCLR 0U

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#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WOSET 0U

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#define LPDDR4__PI_MCAREF_FORWARD_ONLY__REG DENALI_PI_15

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#define LPDDR4__PI_MCAREF_FORWARD_ONLY__FLD LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY

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#define LPDDR4__DENALI_PI_15__PI_RESERVED2_MASK 0x01000000U

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#define LPDDR4__DENALI_PI_15__PI_RESERVED2_SHIFT 24U

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#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WIDTH 1U

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#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WOCLR 0U

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#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WOSET 0U

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#define LPDDR4__PI_RESERVED2__REG DENALI_PI_15

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#define LPDDR4__PI_RESERVED2__FLD LPDDR4__DENALI_PI_15__PI_RESERVED2

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#define LPDDR4__DENALI_PI_16_READ_MASK 0x010FFFFFU

285

#define LPDDR4__DENALI_PI_16_WRITE_MASK 0x010FFFFFU

286

#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_MASK 0x000FFFFFU

287

#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_SHIFT 0U

288

#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_WIDTH 20U

289

#define LPDDR4__PI_TREF_INTERVAL__REG DENALI_PI_16

290

#define LPDDR4__PI_TREF_INTERVAL__FLD LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL

291

292

#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_MASK 0x01000000U

293

#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_SHIFT 24U

294

#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WIDTH 1U

295

#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WOCLR 0U

296

#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WOSET 0U

297

#define LPDDR4__PI_ON_DFIBUS__REG DENALI_PI_16

298

#define LPDDR4__PI_ON_DFIBUS__FLD LPDDR4__DENALI_PI_16__PI_ON_DFIBUS

299

300

#define LPDDR4__DENALI_PI_17_READ_MASK 0x01010001U

301

#define LPDDR4__DENALI_PI_17_WRITE_MASK 0x01010001U

302

#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_MASK 0x00000001U

303

#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_SHIFT 0U

304

#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WIDTH 1U

305

#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WOCLR 0U

306

#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WOSET 0U

307

#define LPDDR4__PI_DATA_RETENTION__REG DENALI_PI_17

308

#define LPDDR4__PI_DATA_RETENTION__FLD LPDDR4__DENALI_PI_17__PI_DATA_RETENTION

309

310

#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_MASK 0x00000100U

311

#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_SHIFT 8U

312

#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WIDTH 1U

313

#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WOCLR 0U

314

#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WOSET 0U

315

#define LPDDR4__PI_SWLVL_LOAD__REG DENALI_PI_17

316

#define LPDDR4__PI_SWLVL_LOAD__FLD LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD

317

318

#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_MASK 0x00010000U

319

#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_SHIFT 16U

320

#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WIDTH 1U

321

#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WOCLR 0U

322

#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WOSET 0U

323

#define LPDDR4__PI_SWLVL_OP_DONE__REG DENALI_PI_17

324

#define LPDDR4__PI_SWLVL_OP_DONE__FLD LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE

325

326

#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_MASK 0x01000000U

327

#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_SHIFT 24U

328

#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WIDTH 1U

329

#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WOCLR 0U

330

#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WOSET 0U

331

#define LPDDR4__PI_SW_WRLVL_RESP_0__REG DENALI_PI_17

332

#define LPDDR4__PI_SW_WRLVL_RESP_0__FLD LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0

333

334

#define LPDDR4__DENALI_PI_18_READ_MASK 0x03010101U

335

#define LPDDR4__DENALI_PI_18_WRITE_MASK 0x03010101U

336

#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_MASK 0x00000001U

337

#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_SHIFT 0U

338

#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WIDTH 1U

339

#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WOCLR 0U

340

#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WOSET 0U

341

#define LPDDR4__PI_SW_WRLVL_RESP_1__REG DENALI_PI_18

342

#define LPDDR4__PI_SW_WRLVL_RESP_1__FLD LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1

343

344

#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_MASK 0x00000100U

345

#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_SHIFT 8U

346

#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_WIDTH 1U

347

#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_WOCLR 0U

348

#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_WOSET 0U

349

#define LPDDR4__PI_SW_WRLVL_RESP_2__REG DENALI_PI_18

350

#define LPDDR4__PI_SW_WRLVL_RESP_2__FLD LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2

351

352

#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_MASK 0x00010000U

353

#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_SHIFT 16U

354

#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_WIDTH 1U

355

#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_WOCLR 0U

356

#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_WOSET 0U

357

#define LPDDR4__PI_SW_WRLVL_RESP_3__REG DENALI_PI_18

358

#define LPDDR4__PI_SW_WRLVL_RESP_3__FLD LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3

359

360

#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_MASK 0x03000000U

361

#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_SHIFT 24U

362

#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_WIDTH 2U

363

#define LPDDR4__PI_SW_RDLVL_RESP_0__REG DENALI_PI_18

364

#define LPDDR4__PI_SW_RDLVL_RESP_0__FLD LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0

365

366

#define LPDDR4__DENALI_PI_19_READ_MASK 0x03030303U

367

#define LPDDR4__DENALI_PI_19_WRITE_MASK 0x03030303U

368

#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1_MASK 0x00000003U

369

#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1_SHIFT 0U

370

#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1_WIDTH 2U

371

#define LPDDR4__PI_SW_RDLVL_RESP_1__REG DENALI_PI_19

372

#define LPDDR4__PI_SW_RDLVL_RESP_1__FLD LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1

373

374

#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2_MASK 0x00000300U

375

#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2_SHIFT 8U

376

#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2_WIDTH 2U

377

#define LPDDR4__PI_SW_RDLVL_RESP_2__REG DENALI_PI_19

378

#define LPDDR4__PI_SW_RDLVL_RESP_2__FLD LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2

379

380

#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3_MASK 0x00030000U

381

#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3_SHIFT 16U

382

#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3_WIDTH 2U

383

#define LPDDR4__PI_SW_RDLVL_RESP_3__REG DENALI_PI_19

384

#define LPDDR4__PI_SW_RDLVL_RESP_3__FLD LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3

385

386

#define LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0_MASK 0x03000000U

387

#define LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0_SHIFT 24U

388

#define LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0_WIDTH 2U

389

#define LPDDR4__PI_SW_CALVL_RESP_0__REG DENALI_PI_19

390

#define LPDDR4__PI_SW_CALVL_RESP_0__FLD LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0

391

392

#define LPDDR4__DENALI_PI_20_READ_MASK 0x00000007U

393

#define LPDDR4__DENALI_PI_20_WRITE_MASK 0x00000007U

394

#define LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE_MASK 0x00000007U

395

#define LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE_SHIFT 0U

396

#define LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE_WIDTH 3U

397

#define LPDDR4__PI_SW_LEVELING_MODE__REG DENALI_PI_20

398

#define LPDDR4__PI_SW_LEVELING_MODE__FLD LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE

399

400

#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_MASK 0x00000100U

401

#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_SHIFT 8U

402

#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_WIDTH 1U

403

#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_WOCLR 0U

404

#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_WOSET 0U

405

#define LPDDR4__PI_SWLVL_START__REG DENALI_PI_20

406

#define LPDDR4__PI_SWLVL_START__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_START

407

408

#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_MASK 0x00010000U

409

#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_SHIFT 16U

410

#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_WIDTH 1U

411

#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_WOCLR 0U

412

#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_WOSET 0U

413

#define LPDDR4__PI_SWLVL_EXIT__REG DENALI_PI_20

414

#define LPDDR4__PI_SWLVL_EXIT__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT

415

416

#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_MASK 0x01000000U

417

#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_SHIFT 24U

418

#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_WIDTH 1U

419

#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_WOCLR 0U

420

#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_WOSET 0U

421

#define LPDDR4__PI_SWLVL_WR_SLICE_0__REG DENALI_PI_20

422

#define LPDDR4__PI_SWLVL_WR_SLICE_0__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0

423

424

#define LPDDR4__DENALI_PI_21_READ_MASK 0x00030000U

425

#define LPDDR4__DENALI_PI_21_WRITE_MASK 0x00030000U

426

#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_MASK 0x00000001U

427

#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_SHIFT 0U

428

#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_WIDTH 1U

429

#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_WOCLR 0U

430

#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_WOSET 0U

431

#define LPDDR4__PI_SWLVL_RD_SLICE_0__REG DENALI_PI_21

432

#define LPDDR4__PI_SWLVL_RD_SLICE_0__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0

433

434

#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_MASK 0x00000100U

435

#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_SHIFT 8U

436

#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_WIDTH 1U

437

#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_WOCLR 0U

438

#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_WOSET 0U

439

#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_0__REG DENALI_PI_21

440

#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_0__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0

441

442

#define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0_MASK 0x00030000U

443

#define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0_SHIFT 16U

444

#define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0_WIDTH 2U

445

#define LPDDR4__PI_SW_WDQLVL_RESP_0__REG DENALI_PI_21

446

#define LPDDR4__PI_SW_WDQLVL_RESP_0__FLD LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0

447

448

#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_MASK 0x01000000U

449

#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_SHIFT 24U

450

#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_WIDTH 1U

451

#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_WOCLR 0U

452

#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_WOSET 0U

453

#define LPDDR4__PI_SWLVL_WR_SLICE_1__REG DENALI_PI_21

454

#define LPDDR4__PI_SWLVL_WR_SLICE_1__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1

455

456

#define LPDDR4__DENALI_PI_22_READ_MASK 0x00030000U

457

#define LPDDR4__DENALI_PI_22_WRITE_MASK 0x00030000U

458

#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_MASK 0x00000001U

459

#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_SHIFT 0U

460

#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_WIDTH 1U

461

#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_WOCLR 0U

462

#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_WOSET 0U

463

#define LPDDR4__PI_SWLVL_RD_SLICE_1__REG DENALI_PI_22

464

#define LPDDR4__PI_SWLVL_RD_SLICE_1__FLD LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1

465

466

#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_MASK 0x00000100U

467

#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_SHIFT 8U

468

#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_WIDTH 1U

469

#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_WOCLR 0U

470

#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_WOSET 0U

471

#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_1__REG DENALI_PI_22

472

#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_1__FLD LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1

473

474

#define LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1_MASK 0x00030000U

475

#define LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1_SHIFT 16U

476

#define LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1_WIDTH 2U

477

#define LPDDR4__PI_SW_WDQLVL_RESP_1__REG DENALI_PI_22

478

#define LPDDR4__PI_SW_WDQLVL_RESP_1__FLD LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1

479

480

#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_MASK 0x01000000U

481

#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_SHIFT 24U

482

#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_WIDTH 1U

483

#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_WOCLR 0U

484

#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_WOSET 0U

485

#define LPDDR4__PI_SWLVL_WR_SLICE_2__REG DENALI_PI_22

486

#define LPDDR4__PI_SWLVL_WR_SLICE_2__FLD LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2

487

488

#define LPDDR4__DENALI_PI_23_READ_MASK 0x00030000U

489

#define LPDDR4__DENALI_PI_23_WRITE_MASK 0x00030000U

490

#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_MASK 0x00000001U

491

#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_SHIFT 0U

492

#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_WIDTH 1U

493

#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_WOCLR 0U

494

#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_WOSET 0U

495

#define LPDDR4__PI_SWLVL_RD_SLICE_2__REG DENALI_PI_23

496

#define LPDDR4__PI_SWLVL_RD_SLICE_2__FLD LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2

497

498

#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_MASK 0x00000100U

499

#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_SHIFT 8U

500

#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_WIDTH 1U

501

#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_WOCLR 0U

502

#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_WOSET 0U

503

#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_2__REG DENALI_PI_23

504

#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_2__FLD LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2

505

506

#define LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2_MASK 0x00030000U

507

#define LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2_SHIFT 16U

508

#define LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2_WIDTH 2U

509

#define LPDDR4__PI_SW_WDQLVL_RESP_2__REG DENALI_PI_23

510

#define LPDDR4__PI_SW_WDQLVL_RESP_2__FLD LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2

511

512

#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_MASK 0x01000000U

513

#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_SHIFT 24U

514

#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_WIDTH 1U

515

#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_WOCLR 0U

516

#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_WOSET 0U

517

#define LPDDR4__PI_SWLVL_WR_SLICE_3__REG DENALI_PI_23

518

#define LPDDR4__PI_SWLVL_WR_SLICE_3__FLD LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3

519

520

#define LPDDR4__DENALI_PI_24_READ_MASK 0x00030000U

521

#define LPDDR4__DENALI_PI_24_WRITE_MASK 0x00030000U

522

#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_MASK 0x00000001U

523

#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_SHIFT 0U

524

#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_WIDTH 1U

525

#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_WOCLR 0U

526

#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_WOSET 0U

527

#define LPDDR4__PI_SWLVL_RD_SLICE_3__REG DENALI_PI_24

528

#define LPDDR4__PI_SWLVL_RD_SLICE_3__FLD LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3

529

530

#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_MASK 0x00000100U

531

#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_SHIFT 8U

532

#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_WIDTH 1U

533

#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_WOCLR 0U

534

#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_WOSET 0U

535

#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_3__REG DENALI_PI_24

536

#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_3__FLD LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3

537

538

#define LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3_MASK 0x00030000U

539

#define LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3_SHIFT 16U

540

#define LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3_WIDTH 2U

541

#define LPDDR4__PI_SW_WDQLVL_RESP_3__REG DENALI_PI_24

542

#define LPDDR4__PI_SW_WDQLVL_RESP_3__FLD LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3

543

544

#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_MASK 0x01000000U

545

#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_SHIFT 24U

546

#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_WIDTH 1U

547

#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_WOCLR 0U

548

#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_WOSET 0U

549

#define LPDDR4__PI_SWLVL_SM2_START__REG DENALI_PI_24

550

#define LPDDR4__PI_SWLVL_SM2_START__FLD LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START

551

552

#define LPDDR4__DENALI_PI_25_READ_MASK 0x01000000U

553

#define LPDDR4__DENALI_PI_25_WRITE_MASK 0x01000000U

554

#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_MASK 0x00000001U

555

#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_SHIFT 0U

556

#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_WIDTH 1U

557

#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_WOCLR 0U

558

#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_WOSET 0U

559

#define LPDDR4__PI_SWLVL_SM2_WR__REG DENALI_PI_25

560

#define LPDDR4__PI_SWLVL_SM2_WR__FLD LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR

561

562

#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_MASK 0x00000100U

563

#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_SHIFT 8U

564

#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_WIDTH 1U

565

#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_WOCLR 0U

566

#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_WOSET 0U

567

#define LPDDR4__PI_SWLVL_SM2_RD__REG DENALI_PI_25

568

#define LPDDR4__PI_SWLVL_SM2_RD__FLD LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD

569

570

#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_MASK 0x00010000U

571

#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_SHIFT 16U

572

#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_WIDTH 1U

573

#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_WOCLR 0U

574

#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_WOSET 0U

575

#define LPDDR4__PI_SEQUENTIAL_LVL_REQ__REG DENALI_PI_25

576

#define LPDDR4__PI_SEQUENTIAL_LVL_REQ__FLD LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ

577

578

#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_MASK 0x01000000U

579

#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_SHIFT 24U

580

#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_WIDTH 1U

581

#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_WOCLR 0U

582

#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_WOSET 0U

583

#define LPDDR4__PI_DFS_PERIOD_EN__REG DENALI_PI_25

584

#define LPDDR4__PI_DFS_PERIOD_EN__FLD LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN

585

586

#define LPDDR4__DENALI_PI_26_READ_MASK 0x01010101U

587

#define LPDDR4__DENALI_PI_26_WRITE_MASK 0x01010101U

588

#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_MASK 0x00000001U

589

#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_SHIFT 0U

590

#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_WIDTH 1U

591

#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_WOCLR 0U

592

#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_WOSET 0U

593

#define LPDDR4__PI_SRE_PERIOD_EN__REG DENALI_PI_26

594

#define LPDDR4__PI_SRE_PERIOD_EN__FLD LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN

595

596

#define LPDDR4__DENALI_PI_26__PI_MPD_PERIOD_EN_MASK 0x00000100U

597

#define LPDDR4__DENALI_PI_26__PI_MPD_PERIOD_EN_SHIFT 8U

598

#define LPDDR4__DENALI_PI_26__PI_MPD_PERIOD_EN_WIDTH 1U

599

#define LPDDR4__DENALI_PI_26__PI_MPD_PERIOD_EN_WOCLR 0U

600

#define LPDDR4__DENALI_PI_26__PI_MPD_PERIOD_EN_WOSET 0U

601

#define LPDDR4__PI_MPD_PERIOD_EN__REG DENALI_PI_26

602

#define LPDDR4__PI_MPD_PERIOD_EN__FLD LPDDR4__DENALI_PI_26__PI_MPD_PERIOD_EN

603

604

#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_MASK 0x00010000U

605

#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_SHIFT 16U

606

#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_WIDTH 1U

607

#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_WOCLR 0U

608

#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_WOSET 0U

609

#define LPDDR4__PI_DFI40_POLARITY__REG DENALI_PI_26

610

#define LPDDR4__PI_DFI40_POLARITY__FLD LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY

611

612

#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_MASK 0x01000000U

613

#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_SHIFT 24U

614

#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_WIDTH 1U

615

#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_WOCLR 0U

616

#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_WOSET 0U

617

#define LPDDR4__PI_16BIT_DRAM_CONNECT__REG DENALI_PI_26

618

#define LPDDR4__PI_16BIT_DRAM_CONNECT__FLD LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT

619

620

#define LPDDR4__DENALI_PI_27_READ_MASK 0x3F030F00U

621

#define LPDDR4__DENALI_PI_27_WRITE_MASK 0x3F030F00U

622

#define LPDDR4__DENALI_PI_27__PI_WRLVL_REQ_MASK 0x00000001U

623

#define LPDDR4__DENALI_PI_27__PI_WRLVL_REQ_SHIFT 0U

624

#define LPDDR4__DENALI_PI_27__PI_WRLVL_REQ_WIDTH 1U

625

#define LPDDR4__DENALI_PI_27__PI_WRLVL_REQ_WOCLR 0U

626

#define LPDDR4__DENALI_PI_27__PI_WRLVL_REQ_WOSET 0U

627

#define LPDDR4__PI_WRLVL_REQ__REG DENALI_PI_27

628

#define LPDDR4__PI_WRLVL_REQ__FLD LPDDR4__DENALI_PI_27__PI_WRLVL_REQ

629

630

#define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_SW_MASK 0x00000F00U

631

#define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_SW_SHIFT 8U

632

#define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_SW_WIDTH 4U

633

#define LPDDR4__PI_WRLVL_CS_SW__REG DENALI_PI_27

634

#define LPDDR4__PI_WRLVL_CS_SW__FLD LPDDR4__DENALI_PI_27__PI_WRLVL_CS_SW

635

636

#define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_MASK 0x00030000U

637

#define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_SHIFT 16U

638

#define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_WIDTH 2U

639

#define LPDDR4__PI_WRLVL_CS__REG DENALI_PI_27

640

#define LPDDR4__PI_WRLVL_CS__FLD LPDDR4__DENALI_PI_27__PI_WRLVL_CS

641

642

#define LPDDR4__DENALI_PI_27__PI_WLDQSEN_MASK 0x3F000000U

643

#define LPDDR4__DENALI_PI_27__PI_WLDQSEN_SHIFT 24U

644

#define LPDDR4__DENALI_PI_27__PI_WLDQSEN_WIDTH 6U

645

#define LPDDR4__PI_WLDQSEN__REG DENALI_PI_27

646

#define LPDDR4__PI_WLDQSEN__FLD LPDDR4__DENALI_PI_27__PI_WLDQSEN

647

648

#define LPDDR4__DENALI_PI_28_READ_MASK 0x01FFFF3FU

649

#define LPDDR4__DENALI_PI_28_WRITE_MASK 0x01FFFF3FU

650

#define LPDDR4__DENALI_PI_28__PI_WLMRD_MASK 0x0000003FU

651

#define LPDDR4__DENALI_PI_28__PI_WLMRD_SHIFT 0U

652

#define LPDDR4__DENALI_PI_28__PI_WLMRD_WIDTH 6U

653

#define LPDDR4__PI_WLMRD__REG DENALI_PI_28

654

#define LPDDR4__PI_WLMRD__FLD LPDDR4__DENALI_PI_28__PI_WLMRD

655

656

#define LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL_MASK 0x00FFFF00U

657

#define LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL_SHIFT 8U

658

#define LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL_WIDTH 16U

659

#define LPDDR4__PI_WRLVL_INTERVAL__REG DENALI_PI_28

660

#define LPDDR4__PI_WRLVL_INTERVAL__FLD LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL

661

662

#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_MASK 0x01000000U

663

#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_SHIFT 24U

664

#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_WIDTH 1U

665

#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_WOCLR 0U

666

#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_WOSET 0U

667

#define LPDDR4__PI_WRLVL_ON_SREF_EXIT__REG DENALI_PI_28

668

#define LPDDR4__PI_WRLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT

669

670

#define LPDDR4__DENALI_PI_29_READ_MASK 0x0F010F01U

671

#define LPDDR4__DENALI_PI_29_WRITE_MASK 0x0F010F01U

672

#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_MASK 0x00000001U

673

#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_SHIFT 0U

674

#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_WIDTH 1U

675

#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_WOCLR 0U

676

#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_WOSET 0U

677

#define LPDDR4__PI_WRLVL_DISABLE_DFS__REG DENALI_PI_29

678

#define LPDDR4__PI_WRLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS

679

680

#define LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK_MASK 0x00000F00U

681

#define LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK_SHIFT 8U

682

#define LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK_WIDTH 4U

683

#define LPDDR4__PI_WRLVL_RESP_MASK__REG DENALI_PI_29

684

#define LPDDR4__PI_WRLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK

685

686

#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_MASK 0x00010000U

687

#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_SHIFT 16U

688

#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_WIDTH 1U

689

#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_WOCLR 0U

690

#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_WOSET 0U

691

#define LPDDR4__PI_WRLVL_ROTATE__REG DENALI_PI_29

692

#define LPDDR4__PI_WRLVL_ROTATE__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE

693

694

#define LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP_MASK 0x0F000000U

695

#define LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP_SHIFT 24U

696

#define LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP_WIDTH 4U

697

#define LPDDR4__PI_WRLVL_CS_MAP__REG DENALI_PI_29

698

#define LPDDR4__PI_WRLVL_CS_MAP__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP

699

700

#define LPDDR4__DENALI_PI_30_READ_MASK 0x00FF0101U

701

#define LPDDR4__DENALI_PI_30_WRITE_MASK 0x00FF0101U

702

#define LPDDR4__DENALI_PI_30__PI_WRLVL_ON_MPD_EXIT_MASK 0x00000001U

703

#define LPDDR4__DENALI_PI_30__PI_WRLVL_ON_MPD_EXIT_SHIFT 0U

704

#define LPDDR4__DENALI_PI_30__PI_WRLVL_ON_MPD_EXIT_WIDTH 1U

705

#define LPDDR4__DENALI_PI_30__PI_WRLVL_ON_MPD_EXIT_WOCLR 0U

706

#define LPDDR4__DENALI_PI_30__PI_WRLVL_ON_MPD_EXIT_WOSET 0U

707

#define LPDDR4__PI_WRLVL_ON_MPD_EXIT__REG DENALI_PI_30

708

#define LPDDR4__PI_WRLVL_ON_MPD_EXIT__FLD LPDDR4__DENALI_PI_30__PI_WRLVL_ON_MPD_EXIT

709

710

#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_MASK 0x00000100U

711

#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_SHIFT 8U

712

#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_WIDTH 1U

713

#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_WOCLR 0U

714

#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_WOSET 0U

715

#define LPDDR4__PI_WRLVL_ERROR_STATUS__REG DENALI_PI_30

716

#define LPDDR4__PI_WRLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS

717

718

#define LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN_MASK 0x00FF0000U

719

#define LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN_SHIFT 16U

720

#define LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN_WIDTH 8U

721

#define LPDDR4__PI_TDFI_WRLVL_EN__REG DENALI_PI_30

722

#define LPDDR4__PI_TDFI_WRLVL_EN__FLD LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN

723

724

#define LPDDR4__DENALI_PI_31_READ_MASK 0xFFFFFFFFU

725

#define LPDDR4__DENALI_PI_31_WRITE_MASK 0xFFFFFFFFU

726

#define LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP_MASK 0xFFFFFFFFU

727

#define LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP_SHIFT 0U

728

#define LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP_WIDTH 32U

729

#define LPDDR4__PI_TDFI_WRLVL_RESP__REG DENALI_PI_31

730

#define LPDDR4__PI_TDFI_WRLVL_RESP__FLD LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP

731

732

#define LPDDR4__DENALI_PI_32_READ_MASK 0xFFFFFFFFU

733

#define LPDDR4__DENALI_PI_32_WRITE_MASK 0xFFFFFFFFU

734

#define LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX_MASK 0xFFFFFFFFU

735

#define LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX_SHIFT 0U

736

#define LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX_WIDTH 32U

737

#define LPDDR4__PI_TDFI_WRLVL_MAX__REG DENALI_PI_32

738

#define LPDDR4__PI_TDFI_WRLVL_MAX__FLD LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX

739

740

#define LPDDR4__DENALI_PI_33_READ_MASK 0x0F0F0F1FU

741

#define LPDDR4__DENALI_PI_33_WRITE_MASK 0x0F0F0F1FU

742

#define LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM_MASK 0x0000001FU

743

#define LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM_SHIFT 0U

744

#define LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM_WIDTH 5U

745

#define LPDDR4__PI_WRLVL_STROBE_NUM__REG DENALI_PI_33

746

#define LPDDR4__PI_WRLVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM

747

748

#define LPDDR4__DENALI_PI_33__PI_TODTH_WR_MASK 0x00000F00U

749

#define LPDDR4__DENALI_PI_33__PI_TODTH_WR_SHIFT 8U

750

#define LPDDR4__DENALI_PI_33__PI_TODTH_WR_WIDTH 4U

751

#define LPDDR4__PI_TODTH_WR__REG DENALI_PI_33

752

#define LPDDR4__PI_TODTH_WR__FLD LPDDR4__DENALI_PI_33__PI_TODTH_WR

753

754

#define LPDDR4__DENALI_PI_33__PI_TODTH_RD_MASK 0x000F0000U

755

#define LPDDR4__DENALI_PI_33__PI_TODTH_RD_SHIFT 16U

756

#define LPDDR4__DENALI_PI_33__PI_TODTH_RD_WIDTH 4U

757

#define LPDDR4__PI_TODTH_RD__REG DENALI_PI_33

758

#define LPDDR4__PI_TODTH_RD__FLD LPDDR4__DENALI_PI_33__PI_TODTH_RD

759

760

#define LPDDR4__DENALI_PI_33__PI_ODT_VALUE_MASK 0x0F000000U

761

#define LPDDR4__DENALI_PI_33__PI_ODT_VALUE_SHIFT 24U

762

#define LPDDR4__DENALI_PI_33__PI_ODT_VALUE_WIDTH 4U

763

#define LPDDR4__PI_ODT_VALUE__REG DENALI_PI_33

764

#define LPDDR4__PI_ODT_VALUE__FLD LPDDR4__DENALI_PI_33__PI_ODT_VALUE

765

766

#define LPDDR4__DENALI_PI_34_READ_MASK 0x0000000FU

767

#define LPDDR4__DENALI_PI_34_WRITE_MASK 0x0000000FU

768

#define LPDDR4__DENALI_PI_34__PI_ADDRESS_MIRRORING_MASK 0x0000000FU

769

#define LPDDR4__DENALI_PI_34__PI_ADDRESS_MIRRORING_SHIFT 0U

770

#define LPDDR4__DENALI_PI_34__PI_ADDRESS_MIRRORING_WIDTH 4U

771

#define LPDDR4__PI_ADDRESS_MIRRORING__REG DENALI_PI_34

772

#define LPDDR4__PI_ADDRESS_MIRRORING__FLD LPDDR4__DENALI_PI_34__PI_ADDRESS_MIRRORING

773

774

#define LPDDR4__DENALI_PI_35_READ_MASK 0x03FFFFFFU

775

#define LPDDR4__DENALI_PI_35_WRITE_MASK 0x03FFFFFFU

776

#define LPDDR4__DENALI_PI_35__PI_CA_PARITY_ERROR_INJECT_MASK 0x03FFFFFFU

777

#define LPDDR4__DENALI_PI_35__PI_CA_PARITY_ERROR_INJECT_SHIFT 0U

778

#define LPDDR4__DENALI_PI_35__PI_CA_PARITY_ERROR_INJECT_WIDTH 26U

779

#define LPDDR4__PI_CA_PARITY_ERROR_INJECT__REG DENALI_PI_35

780

#define LPDDR4__PI_CA_PARITY_ERROR_INJECT__FLD LPDDR4__DENALI_PI_35__PI_CA_PARITY_ERROR_INJECT

781

782

#define LPDDR4__DENALI_PI_36_READ_MASK 0x00000F07U

783

#define LPDDR4__DENALI_PI_36_WRITE_MASK 0x00000F07U

784

#define LPDDR4__DENALI_PI_36__PI_RESERVED3_MASK 0x00000007U

785

#define LPDDR4__DENALI_PI_36__PI_RESERVED3_SHIFT 0U

786

#define LPDDR4__DENALI_PI_36__PI_RESERVED3_WIDTH 3U

787

#define LPDDR4__PI_RESERVED3__REG DENALI_PI_36

788

#define LPDDR4__PI_RESERVED3__FLD LPDDR4__DENALI_PI_36__PI_RESERVED3

789

790

#define LPDDR4__DENALI_PI_36__PI_RESERVED4_MASK 0x00000F00U

791

#define LPDDR4__DENALI_PI_36__PI_RESERVED4_SHIFT 8U

792

#define LPDDR4__DENALI_PI_36__PI_RESERVED4_WIDTH 4U

793

#define LPDDR4__PI_RESERVED4__REG DENALI_PI_36

794

#define LPDDR4__PI_RESERVED4__FLD LPDDR4__DENALI_PI_36__PI_RESERVED4

795

796

#define LPDDR4__DENALI_PI_36__PI_RDLVL_REQ_MASK 0x00010000U

797

#define LPDDR4__DENALI_PI_36__PI_RDLVL_REQ_SHIFT 16U

798

#define LPDDR4__DENALI_PI_36__PI_RDLVL_REQ_WIDTH 1U

799

#define LPDDR4__DENALI_PI_36__PI_RDLVL_REQ_WOCLR 0U

800

#define LPDDR4__DENALI_PI_36__PI_RDLVL_REQ_WOSET 0U

801

#define LPDDR4__PI_RDLVL_REQ__REG DENALI_PI_36

802

#define LPDDR4__PI_RDLVL_REQ__FLD LPDDR4__DENALI_PI_36__PI_RDLVL_REQ

803

804

#define LPDDR4__DENALI_PI_36__PI_RDLVL_GATE_REQ_MASK 0x01000000U

805

#define LPDDR4__DENALI_PI_36__PI_RDLVL_GATE_REQ_SHIFT 24U

806

#define LPDDR4__DENALI_PI_36__PI_RDLVL_GATE_REQ_WIDTH 1U

807

#define LPDDR4__DENALI_PI_36__PI_RDLVL_GATE_REQ_WOCLR 0U

808

#define LPDDR4__DENALI_PI_36__PI_RDLVL_GATE_REQ_WOSET 0U

809

#define LPDDR4__PI_RDLVL_GATE_REQ__REG DENALI_PI_36

810

#define LPDDR4__PI_RDLVL_GATE_REQ__FLD LPDDR4__DENALI_PI_36__PI_RDLVL_GATE_REQ

811

812

#define LPDDR4__DENALI_PI_37_READ_MASK 0x0000030FU

813

#define LPDDR4__DENALI_PI_37_WRITE_MASK 0x0000030FU

814

#define LPDDR4__DENALI_PI_37__PI_RDLVL_CS_SW_MASK 0x0000000FU

815

#define LPDDR4__DENALI_PI_37__PI_RDLVL_CS_SW_SHIFT 0U

816

#define LPDDR4__DENALI_PI_37__PI_RDLVL_CS_SW_WIDTH 4U

817

#define LPDDR4__PI_RDLVL_CS_SW__REG DENALI_PI_37

818

#define LPDDR4__PI_RDLVL_CS_SW__FLD LPDDR4__DENALI_PI_37__PI_RDLVL_CS_SW

819

820

#define LPDDR4__DENALI_PI_37__PI_RDLVL_CS_MASK 0x00000300U

821

#define LPDDR4__DENALI_PI_37__PI_RDLVL_CS_SHIFT 8U

822

#define LPDDR4__DENALI_PI_37__PI_RDLVL_CS_WIDTH 2U

823

#define LPDDR4__PI_RDLVL_CS__REG DENALI_PI_37

824

#define LPDDR4__PI_RDLVL_CS__FLD LPDDR4__DENALI_PI_37__PI_RDLVL_CS

825

826

#define LPDDR4__DENALI_PI_38_READ_MASK 0xFFFFFFFFU

827

#define LPDDR4__DENALI_PI_38_WRITE_MASK 0xFFFFFFFFU

828

#define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_0_MASK 0xFFFFFFFFU

829

#define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_0_SHIFT 0U

830

#define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_0_WIDTH 32U

831

#define LPDDR4__PI_RDLVL_PAT_0__REG DENALI_PI_38

832

#define LPDDR4__PI_RDLVL_PAT_0__FLD LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_0

833

834

#define LPDDR4__DENALI_PI_39_READ_MASK 0xFFFFFFFFU

835

#define LPDDR4__DENALI_PI_39_WRITE_MASK 0xFFFFFFFFU

836

#define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_1_MASK 0xFFFFFFFFU

837

#define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_1_SHIFT 0U

838

#define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_1_WIDTH 32U

839

#define LPDDR4__PI_RDLVL_PAT_1__REG DENALI_PI_39

840

#define LPDDR4__PI_RDLVL_PAT_1__FLD LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_1

841

842

#define LPDDR4__DENALI_PI_40_READ_MASK 0xFFFFFFFFU

843

#define LPDDR4__DENALI_PI_40_WRITE_MASK 0xFFFFFFFFU

844

#define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_2_MASK 0xFFFFFFFFU

845

#define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_2_SHIFT 0U

846

#define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_2_WIDTH 32U

847

#define LPDDR4__PI_RDLVL_PAT_2__REG DENALI_PI_40

848

#define LPDDR4__PI_RDLVL_PAT_2__FLD LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_2

849

850

#define LPDDR4__DENALI_PI_41_READ_MASK 0xFFFFFFFFU

851

#define LPDDR4__DENALI_PI_41_WRITE_MASK 0xFFFFFFFFU

852

#define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_3_MASK 0xFFFFFFFFU

853

#define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_3_SHIFT 0U

854

#define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_3_WIDTH 32U

855

#define LPDDR4__PI_RDLVL_PAT_3__REG DENALI_PI_41

856

#define LPDDR4__PI_RDLVL_PAT_3__FLD LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_3

857

858

#define LPDDR4__DENALI_PI_42_READ_MASK 0xFFFFFFFFU

859

#define LPDDR4__DENALI_PI_42_WRITE_MASK 0xFFFFFFFFU

860

#define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_4_MASK 0xFFFFFFFFU

861

#define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_4_SHIFT 0U

862

#define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_4_WIDTH 32U

863

#define LPDDR4__PI_RDLVL_PAT_4__REG DENALI_PI_42

864

#define LPDDR4__PI_RDLVL_PAT_4__FLD LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_4

865

866

#define LPDDR4__DENALI_PI_43_READ_MASK 0xFFFFFFFFU

867

#define LPDDR4__DENALI_PI_43_WRITE_MASK 0xFFFFFFFFU

868

#define LPDDR4__DENALI_PI_43__PI_RDLVL_PAT_5_MASK 0xFFFFFFFFU

869

#define LPDDR4__DENALI_PI_43__PI_RDLVL_PAT_5_SHIFT 0U

870

#define LPDDR4__DENALI_PI_43__PI_RDLVL_PAT_5_WIDTH 32U

871

#define LPDDR4__PI_RDLVL_PAT_5__REG DENALI_PI_43

872

#define LPDDR4__PI_RDLVL_PAT_5__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_PAT_5

873

874

#define LPDDR4__DENALI_PI_44_READ_MASK 0xFFFFFFFFU

875

#define LPDDR4__DENALI_PI_44_WRITE_MASK 0xFFFFFFFFU

876

#define LPDDR4__DENALI_PI_44__PI_RDLVL_PAT_6_MASK 0xFFFFFFFFU

877

#define LPDDR4__DENALI_PI_44__PI_RDLVL_PAT_6_SHIFT 0U

878

#define LPDDR4__DENALI_PI_44__PI_RDLVL_PAT_6_WIDTH 32U

879

#define LPDDR4__PI_RDLVL_PAT_6__REG DENALI_PI_44

880

#define LPDDR4__PI_RDLVL_PAT_6__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_PAT_6

881

882

#define LPDDR4__DENALI_PI_45_READ_MASK 0xFFFFFFFFU

883

#define LPDDR4__DENALI_PI_45_WRITE_MASK 0xFFFFFFFFU

884

#define LPDDR4__DENALI_PI_45__PI_RDLVL_PAT_7_MASK 0xFFFFFFFFU

885

#define LPDDR4__DENALI_PI_45__PI_RDLVL_PAT_7_SHIFT 0U

886

#define LPDDR4__DENALI_PI_45__PI_RDLVL_PAT_7_WIDTH 32U

887

#define LPDDR4__PI_RDLVL_PAT_7__REG DENALI_PI_45

888

#define LPDDR4__PI_RDLVL_PAT_7__FLD LPDDR4__DENALI_PI_45__PI_RDLVL_PAT_7

889

890

#define LPDDR4__DENALI_PI_46_READ_MASK 0x0101010FU

891

#define LPDDR4__DENALI_PI_46_WRITE_MASK 0x0101010FU

892

#define LPDDR4__DENALI_PI_46__PI_RDLVL_SEQ_EN_MASK 0x0000000FU

893

#define LPDDR4__DENALI_PI_46__PI_RDLVL_SEQ_EN_SHIFT 0U

894

#define LPDDR4__DENALI_PI_46__PI_RDLVL_SEQ_EN_WIDTH 4U

895

#define LPDDR4__PI_RDLVL_SEQ_EN__REG DENALI_PI_46

896

#define LPDDR4__PI_RDLVL_SEQ_EN__FLD LPDDR4__DENALI_PI_46__PI_RDLVL_SEQ_EN

897

898

#define LPDDR4__DENALI_PI_46__PI_RDLVL_ON_SREF_EXIT_MASK 0x00000100U

899

#define LPDDR4__DENALI_PI_46__PI_RDLVL_ON_SREF_EXIT_SHIFT 8U

900

#define LPDDR4__DENALI_PI_46__PI_RDLVL_ON_SREF_EXIT_WIDTH 1U

901

#define LPDDR4__DENALI_PI_46__PI_RDLVL_ON_SREF_EXIT_WOCLR 0U

902

#define LPDDR4__DENALI_PI_46__PI_RDLVL_ON_SREF_EXIT_WOSET 0U

903

#define LPDDR4__PI_RDLVL_ON_SREF_EXIT__REG DENALI_PI_46

904

#define LPDDR4__PI_RDLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_46__PI_RDLVL_ON_SREF_EXIT

905

906

#define LPDDR4__DENALI_PI_46__PI_RDLVL_DISABLE_DFS_MASK 0x00010000U

907

#define LPDDR4__DENALI_PI_46__PI_RDLVL_DISABLE_DFS_SHIFT 16U

908

#define LPDDR4__DENALI_PI_46__PI_RDLVL_DISABLE_DFS_WIDTH 1U

909

#define LPDDR4__DENALI_PI_46__PI_RDLVL_DISABLE_DFS_WOCLR 0U

910

#define LPDDR4__DENALI_PI_46__PI_RDLVL_DISABLE_DFS_WOSET 0U

911

#define LPDDR4__PI_RDLVL_DISABLE_DFS__REG DENALI_PI_46

912

#define LPDDR4__PI_RDLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_46__PI_RDLVL_DISABLE_DFS

913

914

#define LPDDR4__DENALI_PI_46__PI_RDLVL_GATE_ON_SREF_EXIT_MASK 0x01000000U

915

#define LPDDR4__DENALI_PI_46__PI_RDLVL_GATE_ON_SREF_EXIT_SHIFT 24U

916

#define LPDDR4__DENALI_PI_46__PI_RDLVL_GATE_ON_SREF_EXIT_WIDTH 1U

917

#define LPDDR4__DENALI_PI_46__PI_RDLVL_GATE_ON_SREF_EXIT_WOCLR 0U

918

#define LPDDR4__DENALI_PI_46__PI_RDLVL_GATE_ON_SREF_EXIT_WOSET 0U

919

#define LPDDR4__PI_RDLVL_GATE_ON_SREF_EXIT__REG DENALI_PI_46

920

#define LPDDR4__PI_RDLVL_GATE_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_46__PI_RDLVL_GATE_ON_SREF_EXIT

921

922

#define LPDDR4__DENALI_PI_47_READ_MASK 0x01010101U

923

#define LPDDR4__DENALI_PI_47_WRITE_MASK 0x01010101U

924

#define LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_DISABLE_DFS_MASK 0x00000001U

925

#define LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_DISABLE_DFS_SHIFT 0U

926

#define LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_DISABLE_DFS_WIDTH 1U

927

#define LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_DISABLE_DFS_WOCLR 0U

928

#define LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_DISABLE_DFS_WOSET 0U

929

#define LPDDR4__PI_RDLVL_GATE_DISABLE_DFS__REG DENALI_PI_47

930

#define LPDDR4__PI_RDLVL_GATE_DISABLE_DFS__FLD LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_DISABLE_DFS

931

932

#define LPDDR4__DENALI_PI_47__PI_RDLVL_ON_MPD_EXIT_MASK 0x00000100U

933

#define LPDDR4__DENALI_PI_47__PI_RDLVL_ON_MPD_EXIT_SHIFT 8U

934

#define LPDDR4__DENALI_PI_47__PI_RDLVL_ON_MPD_EXIT_WIDTH 1U

935

#define LPDDR4__DENALI_PI_47__PI_RDLVL_ON_MPD_EXIT_WOCLR 0U

936

#define LPDDR4__DENALI_PI_47__PI_RDLVL_ON_MPD_EXIT_WOSET 0U

937

#define LPDDR4__PI_RDLVL_ON_MPD_EXIT__REG DENALI_PI_47

938

#define LPDDR4__PI_RDLVL_ON_MPD_EXIT__FLD LPDDR4__DENALI_PI_47__PI_RDLVL_ON_MPD_EXIT

939

940

#define LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_ON_MPD_EXIT_MASK 0x00010000U

941

#define LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_ON_MPD_EXIT_SHIFT 16U

942

#define LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_ON_MPD_EXIT_WIDTH 1U

943

#define LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_ON_MPD_EXIT_WOCLR 0U

944

#define LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_ON_MPD_EXIT_WOSET 0U

945

#define LPDDR4__PI_RDLVL_GATE_ON_MPD_EXIT__REG DENALI_PI_47

946

#define LPDDR4__PI_RDLVL_GATE_ON_MPD_EXIT__FLD LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_ON_MPD_EXIT

947

948

#define LPDDR4__DENALI_PI_47__PI_RDLVL_ROTATE_MASK 0x01000000U

949

#define LPDDR4__DENALI_PI_47__PI_RDLVL_ROTATE_SHIFT 24U

950

#define LPDDR4__DENALI_PI_47__PI_RDLVL_ROTATE_WIDTH 1U

951

#define LPDDR4__DENALI_PI_47__PI_RDLVL_ROTATE_WOCLR 0U

952

#define LPDDR4__DENALI_PI_47__PI_RDLVL_ROTATE_WOSET 0U

953

#define LPDDR4__PI_RDLVL_ROTATE__REG DENALI_PI_47

954

#define LPDDR4__PI_RDLVL_ROTATE__FLD LPDDR4__DENALI_PI_47__PI_RDLVL_ROTATE

955

956

#define LPDDR4__DENALI_PI_48_READ_MASK 0x000F0F01U

957

#define LPDDR4__DENALI_PI_48_WRITE_MASK 0x000F0F01U

958

#define LPDDR4__DENALI_PI_48__PI_RDLVL_GATE_ROTATE_MASK 0x00000001U

959

#define LPDDR4__DENALI_PI_48__PI_RDLVL_GATE_ROTATE_SHIFT 0U

960

#define LPDDR4__DENALI_PI_48__PI_RDLVL_GATE_ROTATE_WIDTH 1U

961

#define LPDDR4__DENALI_PI_48__PI_RDLVL_GATE_ROTATE_WOCLR 0U

962

#define LPDDR4__DENALI_PI_48__PI_RDLVL_GATE_ROTATE_WOSET 0U

963

#define LPDDR4__PI_RDLVL_GATE_ROTATE__REG DENALI_PI_48

964

#define LPDDR4__PI_RDLVL_GATE_ROTATE__FLD LPDDR4__DENALI_PI_48__PI_RDLVL_GATE_ROTATE

965

966

#define LPDDR4__DENALI_PI_48__PI_RDLVL_CS_MAP_MASK 0x00000F00U

967

#define LPDDR4__DENALI_PI_48__PI_RDLVL_CS_MAP_SHIFT 8U

968

#define LPDDR4__DENALI_PI_48__PI_RDLVL_CS_MAP_WIDTH 4U

969

#define LPDDR4__PI_RDLVL_CS_MAP__REG DENALI_PI_48

970

#define LPDDR4__PI_RDLVL_CS_MAP__FLD LPDDR4__DENALI_PI_48__PI_RDLVL_CS_MAP

971

972

#define LPDDR4__DENALI_PI_48__PI_RDLVL_GATE_CS_MAP_MASK 0x000F0000U

973

#define LPDDR4__DENALI_PI_48__PI_RDLVL_GATE_CS_MAP_SHIFT 16U

974

#define LPDDR4__DENALI_PI_48__PI_RDLVL_GATE_CS_MAP_WIDTH 4U

975

#define LPDDR4__PI_RDLVL_GATE_CS_MAP__REG DENALI_PI_48

976

#define LPDDR4__PI_RDLVL_GATE_CS_MAP__FLD LPDDR4__DENALI_PI_48__PI_RDLVL_GATE_CS_MAP

977

978

#define LPDDR4__DENALI_PI_49_READ_MASK 0x000003FFU

979

#define LPDDR4__DENALI_PI_49_WRITE_MASK 0x000003FFU

980

#define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_RR_MASK 0x000003FFU

981

#define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_RR_SHIFT 0U

982

#define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_RR_WIDTH 10U

983

#define LPDDR4__PI_TDFI_RDLVL_RR__REG DENALI_PI_49

984

#define LPDDR4__PI_TDFI_RDLVL_RR__FLD LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_RR

985

986

#define LPDDR4__DENALI_PI_50_READ_MASK 0xFFFFFFFFU

987

#define LPDDR4__DENALI_PI_50_WRITE_MASK 0xFFFFFFFFU

988

#define LPDDR4__DENALI_PI_50__PI_TDFI_RDLVL_RESP_MASK 0xFFFFFFFFU

989

#define LPDDR4__DENALI_PI_50__PI_TDFI_RDLVL_RESP_SHIFT 0U

990

#define LPDDR4__DENALI_PI_50__PI_TDFI_RDLVL_RESP_WIDTH 32U

991

#define LPDDR4__PI_TDFI_RDLVL_RESP__REG DENALI_PI_50

992

#define LPDDR4__PI_TDFI_RDLVL_RESP__FLD LPDDR4__DENALI_PI_50__PI_TDFI_RDLVL_RESP

993

994

#define LPDDR4__DENALI_PI_51_READ_MASK 0x0000FF0FU

995

#define LPDDR4__DENALI_PI_51_WRITE_MASK 0x0000FF0FU

996

#define LPDDR4__DENALI_PI_51__PI_RDLVL_RESP_MASK_MASK 0x0000000FU

997

#define LPDDR4__DENALI_PI_51__PI_RDLVL_RESP_MASK_SHIFT 0U

998

#define LPDDR4__DENALI_PI_51__PI_RDLVL_RESP_MASK_WIDTH 4U

999

#define LPDDR4__PI_RDLVL_RESP_MASK__REG DENALI_PI_51

1000

#define LPDDR4__PI_RDLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_51__PI_RDLVL_RESP_MASK

1001

1002

#define LPDDR4__DENALI_PI_51__PI_TDFI_RDLVL_EN_MASK 0x0000FF00U

1003

#define LPDDR4__DENALI_PI_51__PI_TDFI_RDLVL_EN_SHIFT 8U

1004

#define LPDDR4__DENALI_PI_51__PI_TDFI_RDLVL_EN_WIDTH 8U

1005

#define LPDDR4__PI_TDFI_RDLVL_EN__REG DENALI_PI_51

1006

#define LPDDR4__PI_TDFI_RDLVL_EN__FLD LPDDR4__DENALI_PI_51__PI_TDFI_RDLVL_EN

1007

1008

#define LPDDR4__DENALI_PI_52_READ_MASK 0xFFFFFFFFU

1009

#define LPDDR4__DENALI_PI_52_WRITE_MASK 0xFFFFFFFFU

1010

#define LPDDR4__DENALI_PI_52__PI_TDFI_RDLVL_MAX_MASK 0xFFFFFFFFU

1011

#define LPDDR4__DENALI_PI_52__PI_TDFI_RDLVL_MAX_SHIFT 0U

1012

#define LPDDR4__DENALI_PI_52__PI_TDFI_RDLVL_MAX_WIDTH 32U

1013

#define LPDDR4__PI_TDFI_RDLVL_MAX__REG DENALI_PI_52

1014

#define LPDDR4__PI_TDFI_RDLVL_MAX__FLD LPDDR4__DENALI_PI_52__PI_TDFI_RDLVL_MAX

1015

1016

#define LPDDR4__DENALI_PI_53_READ_MASK 0x00FFFF01U

1017

#define LPDDR4__DENALI_PI_53_WRITE_MASK 0x00FFFF01U

1018

#define LPDDR4__DENALI_PI_53__PI_RDLVL_ERROR_STATUS_MASK 0x00000001U

1019

#define LPDDR4__DENALI_PI_53__PI_RDLVL_ERROR_STATUS_SHIFT 0U

1020

#define LPDDR4__DENALI_PI_53__PI_RDLVL_ERROR_STATUS_WIDTH 1U

1021

#define LPDDR4__DENALI_PI_53__PI_RDLVL_ERROR_STATUS_WOCLR 0U

1022

#define LPDDR4__DENALI_PI_53__PI_RDLVL_ERROR_STATUS_WOSET 0U

1023

#define LPDDR4__PI_RDLVL_ERROR_STATUS__REG DENALI_PI_53

1024

#define LPDDR4__PI_RDLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_53__PI_RDLVL_ERROR_STATUS

1025

1026

#define LPDDR4__DENALI_PI_53__PI_RDLVL_INTERVAL_MASK 0x00FFFF00U

1027

#define LPDDR4__DENALI_PI_53__PI_RDLVL_INTERVAL_SHIFT 8U

1028

#define LPDDR4__DENALI_PI_53__PI_RDLVL_INTERVAL_WIDTH 16U

1029

#define LPDDR4__PI_RDLVL_INTERVAL__REG DENALI_PI_53

1030

#define LPDDR4__PI_RDLVL_INTERVAL__FLD LPDDR4__DENALI_PI_53__PI_RDLVL_INTERVAL

1031

1032

#define LPDDR4__DENALI_PI_54_READ_MASK 0x0F0FFFFFU

1033

#define LPDDR4__DENALI_PI_54_WRITE_MASK 0x0F0FFFFFU

1034

#define LPDDR4__DENALI_PI_54__PI_RDLVL_GATE_INTERVAL_MASK 0x0000FFFFU

1035

#define LPDDR4__DENALI_PI_54__PI_RDLVL_GATE_INTERVAL_SHIFT 0U

1036

#define LPDDR4__DENALI_PI_54__PI_RDLVL_GATE_INTERVAL_WIDTH 16U

1037

#define LPDDR4__PI_RDLVL_GATE_INTERVAL__REG DENALI_PI_54

1038

#define LPDDR4__PI_RDLVL_GATE_INTERVAL__FLD LPDDR4__DENALI_PI_54__PI_RDLVL_GATE_INTERVAL

1039

1040

#define LPDDR4__DENALI_PI_54__PI_RDLVL_PATTERN_START_MASK 0x000F0000U

1041

#define LPDDR4__DENALI_PI_54__PI_RDLVL_PATTERN_START_SHIFT 16U

1042

#define LPDDR4__DENALI_PI_54__PI_RDLVL_PATTERN_START_WIDTH 4U

1043

#define LPDDR4__PI_RDLVL_PATTERN_START__REG DENALI_PI_54

1044

#define LPDDR4__PI_RDLVL_PATTERN_START__FLD LPDDR4__DENALI_PI_54__PI_RDLVL_PATTERN_START

1045

1046

#define LPDDR4__DENALI_PI_54__PI_RDLVL_PATTERN_NUM_MASK 0x0F000000U

1047

#define LPDDR4__DENALI_PI_54__PI_RDLVL_PATTERN_NUM_SHIFT 24U

1048

#define LPDDR4__DENALI_PI_54__PI_RDLVL_PATTERN_NUM_WIDTH 4U

1049

#define LPDDR4__PI_RDLVL_PATTERN_NUM__REG DENALI_PI_54

1050

#define LPDDR4__PI_RDLVL_PATTERN_NUM__FLD LPDDR4__DENALI_PI_54__PI_RDLVL_PATTERN_NUM

1051

1052

#define LPDDR4__DENALI_PI_55_READ_MASK 0x01011F1FU

1053

#define LPDDR4__DENALI_PI_55_WRITE_MASK 0x01011F1FU

1054

#define LPDDR4__DENALI_PI_55__PI_RDLVL_STROBE_NUM_MASK 0x0000001FU

1055

#define LPDDR4__DENALI_PI_55__PI_RDLVL_STROBE_NUM_SHIFT 0U

1056

#define LPDDR4__DENALI_PI_55__PI_RDLVL_STROBE_NUM_WIDTH 5U

1057

#define LPDDR4__PI_RDLVL_STROBE_NUM__REG DENALI_PI_55

1058

#define LPDDR4__PI_RDLVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_55__PI_RDLVL_STROBE_NUM

1059

1060

#define LPDDR4__DENALI_PI_55__PI_RDLVL_GATE_STROBE_NUM_MASK 0x00001F00U

1061

#define LPDDR4__DENALI_PI_55__PI_RDLVL_GATE_STROBE_NUM_SHIFT 8U

1062

#define LPDDR4__DENALI_PI_55__PI_RDLVL_GATE_STROBE_NUM_WIDTH 5U

1063

#define LPDDR4__PI_RDLVL_GATE_STROBE_NUM__REG DENALI_PI_55

1064

#define LPDDR4__PI_RDLVL_GATE_STROBE_NUM__FLD LPDDR4__DENALI_PI_55__PI_RDLVL_GATE_STROBE_NUM

1065

1066

#define LPDDR4__DENALI_PI_55__PI_RD_PREAMBLE_TRAINING_EN_MASK 0x00010000U

1067

#define LPDDR4__DENALI_PI_55__PI_RD_PREAMBLE_TRAINING_EN_SHIFT 16U

1068

#define LPDDR4__DENALI_PI_55__PI_RD_PREAMBLE_TRAINING_EN_WIDTH 1U

1069

#define LPDDR4__DENALI_PI_55__PI_RD_PREAMBLE_TRAINING_EN_WOCLR 0U

1070

#define LPDDR4__DENALI_PI_55__PI_RD_PREAMBLE_TRAINING_EN_WOSET 0U

1071

#define LPDDR4__PI_RD_PREAMBLE_TRAINING_EN__REG DENALI_PI_55

1072

#define LPDDR4__PI_RD_PREAMBLE_TRAINING_EN__FLD LPDDR4__DENALI_PI_55__PI_RD_PREAMBLE_TRAINING_EN

1073

1074

#define LPDDR4__DENALI_PI_55__PI_REG_DIMM_ENABLE_MASK 0x01000000U

1075

#define LPDDR4__DENALI_PI_55__PI_REG_DIMM_ENABLE_SHIFT 24U

1076

#define LPDDR4__DENALI_PI_55__PI_REG_DIMM_ENABLE_WIDTH 1U

1077

#define LPDDR4__DENALI_PI_55__PI_REG_DIMM_ENABLE_WOCLR 0U

1078

#define LPDDR4__DENALI_PI_55__PI_REG_DIMM_ENABLE_WOSET 0U

1079

#define LPDDR4__PI_REG_DIMM_ENABLE__REG DENALI_PI_55

1080

#define LPDDR4__PI_REG_DIMM_ENABLE__FLD LPDDR4__DENALI_PI_55__PI_REG_DIMM_ENABLE

1081

1082

#define LPDDR4__DENALI_PI_56_READ_MASK 0x0F00FFFFU

1083

#define LPDDR4__DENALI_PI_56_WRITE_MASK 0x0F00FFFFU

1084

#define LPDDR4__DENALI_PI_56__PI_TDFI_RDDATA_EN_MASK 0x000000FFU

1085

#define LPDDR4__DENALI_PI_56__PI_TDFI_RDDATA_EN_SHIFT 0U

1086

#define LPDDR4__DENALI_PI_56__PI_TDFI_RDDATA_EN_WIDTH 8U

1087

#define LPDDR4__PI_TDFI_RDDATA_EN__REG DENALI_PI_56

1088

#define LPDDR4__PI_TDFI_RDDATA_EN__FLD LPDDR4__DENALI_PI_56__PI_TDFI_RDDATA_EN

1089

1090

#define LPDDR4__DENALI_PI_56__PI_TDFI_PHY_WRLAT_MASK 0x0000FF00U

1091

#define LPDDR4__DENALI_PI_56__PI_TDFI_PHY_WRLAT_SHIFT 8U

1092

#define LPDDR4__DENALI_PI_56__PI_TDFI_PHY_WRLAT_WIDTH 8U

1093

#define LPDDR4__PI_TDFI_PHY_WRLAT__REG DENALI_PI_56

1094

#define LPDDR4__PI_TDFI_PHY_WRLAT__FLD LPDDR4__DENALI_PI_56__PI_TDFI_PHY_WRLAT

1095

1096

#define LPDDR4__DENALI_PI_56__PI_CALVL_REQ_MASK 0x00010000U

1097

#define LPDDR4__DENALI_PI_56__PI_CALVL_REQ_SHIFT 16U

1098

#define LPDDR4__DENALI_PI_56__PI_CALVL_REQ_WIDTH 1U

1099

#define LPDDR4__DENALI_PI_56__PI_CALVL_REQ_WOCLR 0U

1100

#define LPDDR4__DENALI_PI_56__PI_CALVL_REQ_WOSET 0U

1101

#define LPDDR4__PI_CALVL_REQ__REG DENALI_PI_56

1102

#define LPDDR4__PI_CALVL_REQ__FLD LPDDR4__DENALI_PI_56__PI_CALVL_REQ

1103

1104

#define LPDDR4__DENALI_PI_56__PI_CALVL_CS_SW_MASK 0x0F000000U

1105

#define LPDDR4__DENALI_PI_56__PI_CALVL_CS_SW_SHIFT 24U

1106

#define LPDDR4__DENALI_PI_56__PI_CALVL_CS_SW_WIDTH 4U

1107

#define LPDDR4__PI_CALVL_CS_SW__REG DENALI_PI_56

1108

#define LPDDR4__PI_CALVL_CS_SW__FLD LPDDR4__DENALI_PI_56__PI_CALVL_CS_SW

1109

1110

#define LPDDR4__DENALI_PI_57_READ_MASK 0x030F0103U

1111

#define LPDDR4__DENALI_PI_57_WRITE_MASK 0x030F0103U

1112

#define LPDDR4__DENALI_PI_57__PI_CALVL_CS_MASK 0x00000003U

1113

#define LPDDR4__DENALI_PI_57__PI_CALVL_CS_SHIFT 0U

1114

#define LPDDR4__DENALI_PI_57__PI_CALVL_CS_WIDTH 2U

1115

#define LPDDR4__PI_CALVL_CS__REG DENALI_PI_57

1116

#define LPDDR4__PI_CALVL_CS__FLD LPDDR4__DENALI_PI_57__PI_CALVL_CS

1117

1118

#define LPDDR4__DENALI_PI_57__PI_RESERVED5_MASK 0x00000100U

1119

#define LPDDR4__DENALI_PI_57__PI_RESERVED5_SHIFT 8U

1120

#define LPDDR4__DENALI_PI_57__PI_RESERVED5_WIDTH 1U

1121

#define LPDDR4__DENALI_PI_57__PI_RESERVED5_WOCLR 0U

1122

#define LPDDR4__DENALI_PI_57__PI_RESERVED5_WOSET 0U

1123

#define LPDDR4__PI_RESERVED5__REG DENALI_PI_57

1124

#define LPDDR4__PI_RESERVED5__FLD LPDDR4__DENALI_PI_57__PI_RESERVED5

1125

1126

#define LPDDR4__DENALI_PI_57__PI_RESERVED6_MASK 0x000F0000U

1127

#define LPDDR4__DENALI_PI_57__PI_RESERVED6_SHIFT 16U

1128

#define LPDDR4__DENALI_PI_57__PI_RESERVED6_WIDTH 4U

1129

#define LPDDR4__PI_RESERVED6__REG DENALI_PI_57

1130

#define LPDDR4__PI_RESERVED6__FLD LPDDR4__DENALI_PI_57__PI_RESERVED6

1131

1132

#define LPDDR4__DENALI_PI_57__PI_CALVL_SEQ_EN_MASK 0x03000000U

1133

#define LPDDR4__DENALI_PI_57__PI_CALVL_SEQ_EN_SHIFT 24U

1134

#define LPDDR4__DENALI_PI_57__PI_CALVL_SEQ_EN_WIDTH 2U

1135

#define LPDDR4__PI_CALVL_SEQ_EN__REG DENALI_PI_57

1136

#define LPDDR4__PI_CALVL_SEQ_EN__FLD LPDDR4__DENALI_PI_57__PI_CALVL_SEQ_EN

1137

1138

#define LPDDR4__DENALI_PI_58_READ_MASK 0x01010101U

1139

#define LPDDR4__DENALI_PI_58_WRITE_MASK 0x01010101U

1140

#define LPDDR4__DENALI_PI_58__PI_CALVL_PERIODIC_MASK 0x00000001U

1141

#define LPDDR4__DENALI_PI_58__PI_CALVL_PERIODIC_SHIFT 0U

1142

#define LPDDR4__DENALI_PI_58__PI_CALVL_PERIODIC_WIDTH 1U

1143

#define LPDDR4__DENALI_PI_58__PI_CALVL_PERIODIC_WOCLR 0U

1144

#define LPDDR4__DENALI_PI_58__PI_CALVL_PERIODIC_WOSET 0U

1145

#define LPDDR4__PI_CALVL_PERIODIC__REG DENALI_PI_58

1146

#define LPDDR4__PI_CALVL_PERIODIC__FLD LPDDR4__DENALI_PI_58__PI_CALVL_PERIODIC

1147

1148

#define LPDDR4__DENALI_PI_58__PI_CALVL_ON_SREF_EXIT_MASK 0x00000100U

1149

#define LPDDR4__DENALI_PI_58__PI_CALVL_ON_SREF_EXIT_SHIFT 8U

1150

#define LPDDR4__DENALI_PI_58__PI_CALVL_ON_SREF_EXIT_WIDTH 1U

1151

#define LPDDR4__DENALI_PI_58__PI_CALVL_ON_SREF_EXIT_WOCLR 0U

1152

#define LPDDR4__DENALI_PI_58__PI_CALVL_ON_SREF_EXIT_WOSET 0U

1153

#define LPDDR4__PI_CALVL_ON_SREF_EXIT__REG DENALI_PI_58

1154

#define LPDDR4__PI_CALVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_58__PI_CALVL_ON_SREF_EXIT

1155

1156

#define LPDDR4__DENALI_PI_58__PI_CALVL_DISABLE_DFS_MASK 0x00010000U

1157

#define LPDDR4__DENALI_PI_58__PI_CALVL_DISABLE_DFS_SHIFT 16U

1158

#define LPDDR4__DENALI_PI_58__PI_CALVL_DISABLE_DFS_WIDTH 1U

1159

#define LPDDR4__DENALI_PI_58__PI_CALVL_DISABLE_DFS_WOCLR 0U

1160

#define LPDDR4__DENALI_PI_58__PI_CALVL_DISABLE_DFS_WOSET 0U

1161

#define LPDDR4__PI_CALVL_DISABLE_DFS__REG DENALI_PI_58

1162

#define LPDDR4__PI_CALVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_58__PI_CALVL_DISABLE_DFS

1163

1164

#define LPDDR4__DENALI_PI_58__PI_CALVL_ROTATE_MASK 0x01000000U

1165

#define LPDDR4__DENALI_PI_58__PI_CALVL_ROTATE_SHIFT 24U

1166

#define LPDDR4__DENALI_PI_58__PI_CALVL_ROTATE_WIDTH 1U

1167

#define LPDDR4__DENALI_PI_58__PI_CALVL_ROTATE_WOCLR 0U

1168

#define LPDDR4__DENALI_PI_58__PI_CALVL_ROTATE_WOSET 0U

1169

#define LPDDR4__PI_CALVL_ROTATE__REG DENALI_PI_58

1170

#define LPDDR4__PI_CALVL_ROTATE__FLD LPDDR4__DENALI_PI_58__PI_CALVL_ROTATE

1171

1172

#define LPDDR4__DENALI_PI_59_READ_MASK 0x0000FF0FU

1173

#define LPDDR4__DENALI_PI_59_WRITE_MASK 0x0000FF0FU

1174

#define LPDDR4__DENALI_PI_59__PI_CALVL_CS_MAP_MASK 0x0000000FU

1175

#define LPDDR4__DENALI_PI_59__PI_CALVL_CS_MAP_SHIFT 0U

1176

#define LPDDR4__DENALI_PI_59__PI_CALVL_CS_MAP_WIDTH 4U

1177

#define LPDDR4__PI_CALVL_CS_MAP__REG DENALI_PI_59

1178

#define LPDDR4__PI_CALVL_CS_MAP__FLD LPDDR4__DENALI_PI_59__PI_CALVL_CS_MAP

1179

1180

#define LPDDR4__DENALI_PI_59__PI_TDFI_CALVL_EN_MASK 0x0000FF00U

1181

#define LPDDR4__DENALI_PI_59__PI_TDFI_CALVL_EN_SHIFT 8U

1182

#define LPDDR4__DENALI_PI_59__PI_TDFI_CALVL_EN_WIDTH 8U

1183

#define LPDDR4__PI_TDFI_CALVL_EN__REG DENALI_PI_59

1184

#define LPDDR4__PI_TDFI_CALVL_EN__FLD LPDDR4__DENALI_PI_59__PI_TDFI_CALVL_EN

1185

1186

#define LPDDR4__DENALI_PI_60_READ_MASK 0xFFFFFFFFU

1187

#define LPDDR4__DENALI_PI_60_WRITE_MASK 0xFFFFFFFFU

1188

#define LPDDR4__DENALI_PI_60__PI_TDFI_CALVL_RESP_MASK 0xFFFFFFFFU

1189

#define LPDDR4__DENALI_PI_60__PI_TDFI_CALVL_RESP_SHIFT 0U

1190

#define LPDDR4__DENALI_PI_60__PI_TDFI_CALVL_RESP_WIDTH 32U

1191

#define LPDDR4__PI_TDFI_CALVL_RESP__REG DENALI_PI_60

1192

#define LPDDR4__PI_TDFI_CALVL_RESP__FLD LPDDR4__DENALI_PI_60__PI_TDFI_CALVL_RESP

1193

1194

#define LPDDR4__DENALI_PI_61_READ_MASK 0xFFFFFFFFU

1195

#define LPDDR4__DENALI_PI_61_WRITE_MASK 0xFFFFFFFFU

1196

#define LPDDR4__DENALI_PI_61__PI_TDFI_CALVL_MAX_MASK 0xFFFFFFFFU

1197

#define LPDDR4__DENALI_PI_61__PI_TDFI_CALVL_MAX_SHIFT 0U

1198

#define LPDDR4__DENALI_PI_61__PI_TDFI_CALVL_MAX_WIDTH 32U

1199

#define LPDDR4__PI_TDFI_CALVL_MAX__REG DENALI_PI_61

1200

#define LPDDR4__PI_TDFI_CALVL_MAX__FLD LPDDR4__DENALI_PI_61__PI_TDFI_CALVL_MAX

1201

1202

#define LPDDR4__DENALI_PI_62_READ_MASK 0xFFFF0301U

1203

#define LPDDR4__DENALI_PI_62_WRITE_MASK 0xFFFF0301U

1204

#define LPDDR4__DENALI_PI_62__PI_CALVL_RESP_MASK_MASK 0x00000001U

1205

#define LPDDR4__DENALI_PI_62__PI_CALVL_RESP_MASK_SHIFT 0U

1206

#define LPDDR4__DENALI_PI_62__PI_CALVL_RESP_MASK_WIDTH 1U

1207

#define LPDDR4__DENALI_PI_62__PI_CALVL_RESP_MASK_WOCLR 0U

1208

#define LPDDR4__DENALI_PI_62__PI_CALVL_RESP_MASK_WOSET 0U

1209

#define LPDDR4__PI_CALVL_RESP_MASK__REG DENALI_PI_62

1210

#define LPDDR4__PI_CALVL_RESP_MASK__FLD LPDDR4__DENALI_PI_62__PI_CALVL_RESP_MASK

1211

1212

#define LPDDR4__DENALI_PI_62__PI_CALVL_ERROR_STATUS_MASK 0x00000300U

1213

#define LPDDR4__DENALI_PI_62__PI_CALVL_ERROR_STATUS_SHIFT 8U

1214

#define LPDDR4__DENALI_PI_62__PI_CALVL_ERROR_STATUS_WIDTH 2U

1215

#define LPDDR4__PI_CALVL_ERROR_STATUS__REG DENALI_PI_62

1216

#define LPDDR4__PI_CALVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_62__PI_CALVL_ERROR_STATUS

1217

1218

#define LPDDR4__DENALI_PI_62__PI_CALVL_INTERVAL_MASK 0xFFFF0000U

1219

#define LPDDR4__DENALI_PI_62__PI_CALVL_INTERVAL_SHIFT 16U

1220

#define LPDDR4__DENALI_PI_62__PI_CALVL_INTERVAL_WIDTH 16U

1221

#define LPDDR4__PI_CALVL_INTERVAL__REG DENALI_PI_62

1222

#define LPDDR4__PI_CALVL_INTERVAL__FLD LPDDR4__DENALI_PI_62__PI_CALVL_INTERVAL

1223

1224

#define LPDDR4__DENALI_PI_63_READ_MASK 0x1F1F3F1FU

1225

#define LPDDR4__DENALI_PI_63_WRITE_MASK 0x1F1F3F1FU

1226

#define LPDDR4__DENALI_PI_63__PI_TCACKEL_MASK 0x0000001FU

1227

#define LPDDR4__DENALI_PI_63__PI_TCACKEL_SHIFT 0U

1228

#define LPDDR4__DENALI_PI_63__PI_TCACKEL_WIDTH 5U

1229

#define LPDDR4__PI_TCACKEL__REG DENALI_PI_63

1230

#define LPDDR4__PI_TCACKEL__FLD LPDDR4__DENALI_PI_63__PI_TCACKEL

1231

1232

#define LPDDR4__DENALI_PI_63__PI_TCAMRD_MASK 0x00003F00U

1233

#define LPDDR4__DENALI_PI_63__PI_TCAMRD_SHIFT 8U

1234

#define LPDDR4__DENALI_PI_63__PI_TCAMRD_WIDTH 6U

1235

#define LPDDR4__PI_TCAMRD__REG DENALI_PI_63

1236

#define LPDDR4__PI_TCAMRD__FLD LPDDR4__DENALI_PI_63__PI_TCAMRD

1237

1238

#define LPDDR4__DENALI_PI_63__PI_TCACKEH_MASK 0x001F0000U

1239

#define LPDDR4__DENALI_PI_63__PI_TCACKEH_SHIFT 16U

1240

#define LPDDR4__DENALI_PI_63__PI_TCACKEH_WIDTH 5U

1241

#define LPDDR4__PI_TCACKEH__REG DENALI_PI_63

1242

#define LPDDR4__PI_TCACKEH__FLD LPDDR4__DENALI_PI_63__PI_TCACKEH

1243

1244

#define LPDDR4__DENALI_PI_63__PI_TCAEXT_MASK 0x1F000000U

1245

#define LPDDR4__DENALI_PI_63__PI_TCAEXT_SHIFT 24U

1246

#define LPDDR4__DENALI_PI_63__PI_TCAEXT_WIDTH 5U

1247

#define LPDDR4__PI_TCAEXT__REG DENALI_PI_63

1248

#define LPDDR4__PI_TCAEXT__FLD LPDDR4__DENALI_PI_63__PI_TCAEXT

1249

1250

#define LPDDR4__DENALI_PI_64_READ_MASK 0xFF0F0F01U

1251

#define LPDDR4__DENALI_PI_64_WRITE_MASK 0xFF0F0F01U

1252

#define LPDDR4__DENALI_PI_64__PI_CA_TRAIN_VREF_EN_MASK 0x00000001U

1253

#define LPDDR4__DENALI_PI_64__PI_CA_TRAIN_VREF_EN_SHIFT 0U

1254

#define LPDDR4__DENALI_PI_64__PI_CA_TRAIN_VREF_EN_WIDTH 1U

1255

#define LPDDR4__DENALI_PI_64__PI_CA_TRAIN_VREF_EN_WOCLR 0U

1256

#define LPDDR4__DENALI_PI_64__PI_CA_TRAIN_VREF_EN_WOSET 0U

1257

#define LPDDR4__PI_CA_TRAIN_VREF_EN__REG DENALI_PI_64

1258

#define LPDDR4__PI_CA_TRAIN_VREF_EN__FLD LPDDR4__DENALI_PI_64__PI_CA_TRAIN_VREF_EN

1259

1260

#define LPDDR4__DENALI_PI_64__PI_CALVL_VREF_INITIAL_STEPSIZE_MASK 0x00000F00U

1261

#define LPDDR4__DENALI_PI_64__PI_CALVL_VREF_INITIAL_STEPSIZE_SHIFT 8U

1262

#define LPDDR4__DENALI_PI_64__PI_CALVL_VREF_INITIAL_STEPSIZE_WIDTH 4U

1263

#define LPDDR4__PI_CALVL_VREF_INITIAL_STEPSIZE__REG DENALI_PI_64

1264

#define LPDDR4__PI_CALVL_VREF_INITIAL_STEPSIZE__FLD LPDDR4__DENALI_PI_64__PI_CALVL_VREF_INITIAL_STEPSIZE

1265

1266

#define LPDDR4__DENALI_PI_64__PI_CALVL_VREF_NORMAL_STEPSIZE_MASK 0x000F0000U

1267

#define LPDDR4__DENALI_PI_64__PI_CALVL_VREF_NORMAL_STEPSIZE_SHIFT 16U

1268

#define LPDDR4__DENALI_PI_64__PI_CALVL_VREF_NORMAL_STEPSIZE_WIDTH 4U

1269

#define LPDDR4__PI_CALVL_VREF_NORMAL_STEPSIZE__REG DENALI_PI_64

1270

#define LPDDR4__PI_CALVL_VREF_NORMAL_STEPSIZE__FLD LPDDR4__DENALI_PI_64__PI_CALVL_VREF_NORMAL_STEPSIZE

1271

1272

#define LPDDR4__DENALI_PI_64__PI_TDFI_INIT_START_MIN_MASK 0xFF000000U

1273

#define LPDDR4__DENALI_PI_64__PI_TDFI_INIT_START_MIN_SHIFT 24U

1274

#define LPDDR4__DENALI_PI_64__PI_TDFI_INIT_START_MIN_WIDTH 8U

1275

#define LPDDR4__PI_TDFI_INIT_START_MIN__REG DENALI_PI_64

1276

#define LPDDR4__PI_TDFI_INIT_START_MIN__FLD LPDDR4__DENALI_PI_64__PI_TDFI_INIT_START_MIN

1277

1278

#define LPDDR4__DENALI_PI_65_READ_MASK 0x017F1FFFU

1279

#define LPDDR4__DENALI_PI_65_WRITE_MASK 0x017F1FFFU

1280

#define LPDDR4__DENALI_PI_65__PI_TCKCKEH_MASK 0x000000FFU

1281

#define LPDDR4__DENALI_PI_65__PI_TCKCKEH_SHIFT 0U

1282

#define LPDDR4__DENALI_PI_65__PI_TCKCKEH_WIDTH 8U

1283

#define LPDDR4__PI_TCKCKEH__REG DENALI_PI_65

1284

#define LPDDR4__PI_TCKCKEH__FLD LPDDR4__DENALI_PI_65__PI_TCKCKEH

1285

1286

#define LPDDR4__DENALI_PI_65__PI_CALVL_STROBE_NUM_MASK 0x00001F00U

1287

#define LPDDR4__DENALI_PI_65__PI_CALVL_STROBE_NUM_SHIFT 8U

1288

#define LPDDR4__DENALI_PI_65__PI_CALVL_STROBE_NUM_WIDTH 5U

1289

#define LPDDR4__PI_CALVL_STROBE_NUM__REG DENALI_PI_65

1290

#define LPDDR4__PI_CALVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_65__PI_CALVL_STROBE_NUM

1291

1292

#define LPDDR4__DENALI_PI_65__PI_SW_CA_TRAIN_VREF_MASK 0x007F0000U

1293

#define LPDDR4__DENALI_PI_65__PI_SW_CA_TRAIN_VREF_SHIFT 16U

1294

#define LPDDR4__DENALI_PI_65__PI_SW_CA_TRAIN_VREF_WIDTH 7U

1295

#define LPDDR4__PI_SW_CA_TRAIN_VREF__REG DENALI_PI_65

1296

#define LPDDR4__PI_SW_CA_TRAIN_VREF__FLD LPDDR4__DENALI_PI_65__PI_SW_CA_TRAIN_VREF

1297

1298

#define LPDDR4__DENALI_PI_65__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_MASK 0x01000000U

1299

#define LPDDR4__DENALI_PI_65__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_SHIFT 24U

1300

#define LPDDR4__DENALI_PI_65__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WIDTH 1U

1301

#define LPDDR4__DENALI_PI_65__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WOCLR 0U

1302

#define LPDDR4__DENALI_PI_65__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WOSET 0U

1303

#define LPDDR4__PI_REFRESH_BETWEEN_SEGMENT_DISABLE__REG DENALI_PI_65

1304

#define LPDDR4__PI_REFRESH_BETWEEN_SEGMENT_DISABLE__FLD LPDDR4__DENALI_PI_65__PI_REFRESH_BETWEEN_SEGMENT_DISABLE

1305

1306

#define LPDDR4__DENALI_PI_66_READ_MASK 0xFF01FFFFU

1307

#define LPDDR4__DENALI_PI_66_WRITE_MASK 0xFF01FFFFU

1308

#define LPDDR4__DENALI_PI_66__PI_CLKDISABLE_2_INIT_START_MASK 0x000000FFU

1309

#define LPDDR4__DENALI_PI_66__PI_CLKDISABLE_2_INIT_START_SHIFT 0U

1310

#define LPDDR4__DENALI_PI_66__PI_CLKDISABLE_2_INIT_START_WIDTH 8U

1311

#define LPDDR4__PI_CLKDISABLE_2_INIT_START__REG DENALI_PI_66

1312

#define LPDDR4__PI_CLKDISABLE_2_INIT_START__FLD LPDDR4__DENALI_PI_66__PI_CLKDISABLE_2_INIT_START

1313

1314

#define LPDDR4__DENALI_PI_66__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_MASK 0x0000FF00U

1315

#define LPDDR4__DENALI_PI_66__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_SHIFT 8U

1316

#define LPDDR4__DENALI_PI_66__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_WIDTH 8U

1317

#define LPDDR4__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE__REG DENALI_PI_66

1318

#define LPDDR4__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE__FLD LPDDR4__DENALI_PI_66__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE

1319

1320

#define LPDDR4__DENALI_PI_66__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_MASK 0x00010000U

1321

#define LPDDR4__DENALI_PI_66__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_SHIFT 16U

1322

#define LPDDR4__DENALI_PI_66__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WIDTH 1U

1323

#define LPDDR4__DENALI_PI_66__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WOCLR 0U

1324

#define LPDDR4__DENALI_PI_66__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WOSET 0U

1325

#define LPDDR4__PI_DRAM_CLK_DISABLE_DEASSERT_SEL__REG DENALI_PI_66

1326

#define LPDDR4__PI_DRAM_CLK_DISABLE_DEASSERT_SEL__FLD LPDDR4__DENALI_PI_66__PI_DRAM_CLK_DISABLE_DEASSERT_SEL

1327

1328

#define LPDDR4__DENALI_PI_66__PI_TDFI_INIT_COMPLETE_MIN_MASK 0xFF000000U

1329

#define LPDDR4__DENALI_PI_66__PI_TDFI_INIT_COMPLETE_MIN_SHIFT 24U

1330

#define LPDDR4__DENALI_PI_66__PI_TDFI_INIT_COMPLETE_MIN_WIDTH 8U

1331

#define LPDDR4__PI_TDFI_INIT_COMPLETE_MIN__REG DENALI_PI_66

1332

#define LPDDR4__PI_TDFI_INIT_COMPLETE_MIN__FLD LPDDR4__DENALI_PI_66__PI_TDFI_INIT_COMPLETE_MIN

1333

1334

#define LPDDR4__DENALI_PI_67_READ_MASK 0x01010103U

1335

#define LPDDR4__DENALI_PI_67_WRITE_MASK 0x01010103U

1336

#define LPDDR4__DENALI_PI_67__PI_VREF_CS_MASK 0x00000003U

1337

#define LPDDR4__DENALI_PI_67__PI_VREF_CS_SHIFT 0U

1338

#define LPDDR4__DENALI_PI_67__PI_VREF_CS_WIDTH 2U

1339

#define LPDDR4__PI_VREF_CS__REG DENALI_PI_67

1340

#define LPDDR4__PI_VREF_CS__FLD LPDDR4__DENALI_PI_67__PI_VREF_CS

1341

1342

#define LPDDR4__DENALI_PI_67__PI_VREF_PDA_EN_MASK 0x00000100U

1343

#define LPDDR4__DENALI_PI_67__PI_VREF_PDA_EN_SHIFT 8U

1344

#define LPDDR4__DENALI_PI_67__PI_VREF_PDA_EN_WIDTH 1U

1345

#define LPDDR4__DENALI_PI_67__PI_VREF_PDA_EN_WOCLR 0U

1346

#define LPDDR4__DENALI_PI_67__PI_VREF_PDA_EN_WOSET 0U

1347

#define LPDDR4__PI_VREF_PDA_EN__REG DENALI_PI_67

1348

#define LPDDR4__PI_VREF_PDA_EN__FLD LPDDR4__DENALI_PI_67__PI_VREF_PDA_EN

1349

1350

#define LPDDR4__DENALI_PI_67__PI_VREFLVL_DISABLE_DFS_MASK 0x00010000U

1351

#define LPDDR4__DENALI_PI_67__PI_VREFLVL_DISABLE_DFS_SHIFT 16U

1352

#define LPDDR4__DENALI_PI_67__PI_VREFLVL_DISABLE_DFS_WIDTH 1U

1353

#define LPDDR4__DENALI_PI_67__PI_VREFLVL_DISABLE_DFS_WOCLR 0U

1354

#define LPDDR4__DENALI_PI_67__PI_VREFLVL_DISABLE_DFS_WOSET 0U

1355

#define LPDDR4__PI_VREFLVL_DISABLE_DFS__REG DENALI_PI_67

1356

#define LPDDR4__PI_VREFLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_67__PI_VREFLVL_DISABLE_DFS

1357

1358

#define LPDDR4__DENALI_PI_67__PI_MC_DFS_PI_SET_VREF_ENABLE_MASK 0x01000000U

1359

#define LPDDR4__DENALI_PI_67__PI_MC_DFS_PI_SET_VREF_ENABLE_SHIFT 24U

1360

#define LPDDR4__DENALI_PI_67__PI_MC_DFS_PI_SET_VREF_ENABLE_WIDTH 1U

1361

#define LPDDR4__DENALI_PI_67__PI_MC_DFS_PI_SET_VREF_ENABLE_WOCLR 0U

1362

#define LPDDR4__DENALI_PI_67__PI_MC_DFS_PI_SET_VREF_ENABLE_WOSET 0U

1363

#define LPDDR4__PI_MC_DFS_PI_SET_VREF_ENABLE__REG DENALI_PI_67

1364

#define LPDDR4__PI_MC_DFS_PI_SET_VREF_ENABLE__FLD LPDDR4__DENALI_PI_67__PI_MC_DFS_PI_SET_VREF_ENABLE

1365

1366

#define LPDDR4__DENALI_PI_68_READ_MASK 0x0F0701FFU

1367

#define LPDDR4__DENALI_PI_68_WRITE_MASK 0x0F0701FFU

1368

#define LPDDR4__DENALI_PI_68__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT_MASK 0x000000FFU

1369

#define LPDDR4__DENALI_PI_68__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT_SHIFT 0U

1370

#define LPDDR4__DENALI_PI_68__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT_WIDTH 8U

1371

#define LPDDR4__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT__REG DENALI_PI_68

1372

#define LPDDR4__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT__FLD LPDDR4__DENALI_PI_68__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT

1373

1374

#define LPDDR4__DENALI_PI_68__PI_WDQLVL_VREF_EN_MASK 0x00000100U

1375

#define LPDDR4__DENALI_PI_68__PI_WDQLVL_VREF_EN_SHIFT 8U

1376

#define LPDDR4__DENALI_PI_68__PI_WDQLVL_VREF_EN_WIDTH 1U

1377

#define LPDDR4__DENALI_PI_68__PI_WDQLVL_VREF_EN_WOCLR 0U

1378

#define LPDDR4__DENALI_PI_68__PI_WDQLVL_VREF_EN_WOSET 0U

1379

#define LPDDR4__PI_WDQLVL_VREF_EN__REG DENALI_PI_68

1380

#define LPDDR4__PI_WDQLVL_VREF_EN__FLD LPDDR4__DENALI_PI_68__PI_WDQLVL_VREF_EN

1381

1382

#define LPDDR4__DENALI_PI_68__PI_WDQLVL_BST_NUM_MASK 0x00070000U

1383

#define LPDDR4__DENALI_PI_68__PI_WDQLVL_BST_NUM_SHIFT 16U

1384

#define LPDDR4__DENALI_PI_68__PI_WDQLVL_BST_NUM_WIDTH 3U

1385

#define LPDDR4__PI_WDQLVL_BST_NUM__REG DENALI_PI_68

1386

#define LPDDR4__PI_WDQLVL_BST_NUM__FLD LPDDR4__DENALI_PI_68__PI_WDQLVL_BST_NUM

1387

1388

#define LPDDR4__DENALI_PI_68__PI_WDQLVL_RESP_MASK_MASK 0x0F000000U

1389

#define LPDDR4__DENALI_PI_68__PI_WDQLVL_RESP_MASK_SHIFT 24U

1390

#define LPDDR4__DENALI_PI_68__PI_WDQLVL_RESP_MASK_WIDTH 4U

1391

#define LPDDR4__PI_WDQLVL_RESP_MASK__REG DENALI_PI_68

1392

#define LPDDR4__PI_WDQLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_68__PI_WDQLVL_RESP_MASK

1393

1394

#define LPDDR4__DENALI_PI_69_READ_MASK 0x1F1F0F01U

1395

#define LPDDR4__DENALI_PI_69_WRITE_MASK 0x1F1F0F01U

1396

#define LPDDR4__DENALI_PI_69__PI_WDQLVL_ROTATE_MASK 0x00000001U

1397

#define LPDDR4__DENALI_PI_69__PI_WDQLVL_ROTATE_SHIFT 0U

1398

#define LPDDR4__DENALI_PI_69__PI_WDQLVL_ROTATE_WIDTH 1U

1399

#define LPDDR4__DENALI_PI_69__PI_WDQLVL_ROTATE_WOCLR 0U

1400

#define LPDDR4__DENALI_PI_69__PI_WDQLVL_ROTATE_WOSET 0U

1401

#define LPDDR4__PI_WDQLVL_ROTATE__REG DENALI_PI_69

1402

#define LPDDR4__PI_WDQLVL_ROTATE__FLD LPDDR4__DENALI_PI_69__PI_WDQLVL_ROTATE

1403

1404

#define LPDDR4__DENALI_PI_69__PI_WDQLVL_CS_MAP_MASK 0x00000F00U

1405

#define LPDDR4__DENALI_PI_69__PI_WDQLVL_CS_MAP_SHIFT 8U

1406

#define LPDDR4__DENALI_PI_69__PI_WDQLVL_CS_MAP_WIDTH 4U

1407

#define LPDDR4__PI_WDQLVL_CS_MAP__REG DENALI_PI_69

1408

#define LPDDR4__PI_WDQLVL_CS_MAP__FLD LPDDR4__DENALI_PI_69__PI_WDQLVL_CS_MAP

1409

1410

#define LPDDR4__DENALI_PI_69__PI_WDQLVL_VREF_INITIAL_STEPSIZE_MASK 0x001F0000U

1411

#define LPDDR4__DENALI_PI_69__PI_WDQLVL_VREF_INITIAL_STEPSIZE_SHIFT 16U

1412

#define LPDDR4__DENALI_PI_69__PI_WDQLVL_VREF_INITIAL_STEPSIZE_WIDTH 5U

1413

#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STEPSIZE__REG DENALI_PI_69

1414

#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STEPSIZE__FLD LPDDR4__DENALI_PI_69__PI_WDQLVL_VREF_INITIAL_STEPSIZE

1415

1416

#define LPDDR4__DENALI_PI_69__PI_WDQLVL_VREF_NORMAL_STEPSIZE_MASK 0x1F000000U

1417

#define LPDDR4__DENALI_PI_69__PI_WDQLVL_VREF_NORMAL_STEPSIZE_SHIFT 24U

1418

#define LPDDR4__DENALI_PI_69__PI_WDQLVL_VREF_NORMAL_STEPSIZE_WIDTH 5U

1419

#define LPDDR4__PI_WDQLVL_VREF_NORMAL_STEPSIZE__REG DENALI_PI_69

1420

#define LPDDR4__PI_WDQLVL_VREF_NORMAL_STEPSIZE__FLD LPDDR4__DENALI_PI_69__PI_WDQLVL_VREF_NORMAL_STEPSIZE

1421

1422

#define LPDDR4__DENALI_PI_70_READ_MASK 0x030F0001U

1423

#define LPDDR4__DENALI_PI_70_WRITE_MASK 0x030F0001U

1424

#define LPDDR4__DENALI_PI_70__PI_WDQLVL_PERIODIC_MASK 0x00000001U

1425

#define LPDDR4__DENALI_PI_70__PI_WDQLVL_PERIODIC_SHIFT 0U

1426

#define LPDDR4__DENALI_PI_70__PI_WDQLVL_PERIODIC_WIDTH 1U

1427

#define LPDDR4__DENALI_PI_70__PI_WDQLVL_PERIODIC_WOCLR 0U

1428

#define LPDDR4__DENALI_PI_70__PI_WDQLVL_PERIODIC_WOSET 0U

1429

#define LPDDR4__PI_WDQLVL_PERIODIC__REG DENALI_PI_70

1430

#define LPDDR4__PI_WDQLVL_PERIODIC__FLD LPDDR4__DENALI_PI_70__PI_WDQLVL_PERIODIC

1431

1432

#define LPDDR4__DENALI_PI_70__PI_WDQLVL_REQ_MASK 0x00000100U

1433

#define LPDDR4__DENALI_PI_70__PI_WDQLVL_REQ_SHIFT 8U

1434

#define LPDDR4__DENALI_PI_70__PI_WDQLVL_REQ_WIDTH 1U

1435

#define LPDDR4__DENALI_PI_70__PI_WDQLVL_REQ_WOCLR 0U

1436

#define LPDDR4__DENALI_PI_70__PI_WDQLVL_REQ_WOSET 0U

1437

#define LPDDR4__PI_WDQLVL_REQ__REG DENALI_PI_70

1438

#define LPDDR4__PI_WDQLVL_REQ__FLD LPDDR4__DENALI_PI_70__PI_WDQLVL_REQ

1439

1440

#define LPDDR4__DENALI_PI_70__PI_WDQLVL_CS_SW_MASK 0x000F0000U

1441

#define LPDDR4__DENALI_PI_70__PI_WDQLVL_CS_SW_SHIFT 16U

1442

#define LPDDR4__DENALI_PI_70__PI_WDQLVL_CS_SW_WIDTH 4U

1443

#define LPDDR4__PI_WDQLVL_CS_SW__REG DENALI_PI_70

1444

#define LPDDR4__PI_WDQLVL_CS_SW__FLD LPDDR4__DENALI_PI_70__PI_WDQLVL_CS_SW

1445

1446

#define LPDDR4__DENALI_PI_70__PI_WDQLVL_CS_MASK 0x03000000U

1447

#define LPDDR4__DENALI_PI_70__PI_WDQLVL_CS_SHIFT 24U

1448

#define LPDDR4__DENALI_PI_70__PI_WDQLVL_CS_WIDTH 2U

1449

#define LPDDR4__PI_WDQLVL_CS__REG DENALI_PI_70

1450

#define LPDDR4__PI_WDQLVL_CS__FLD LPDDR4__DENALI_PI_70__PI_WDQLVL_CS

1451

1452

#define LPDDR4__DENALI_PI_71_READ_MASK 0x000000FFU

1453

#define LPDDR4__DENALI_PI_71_WRITE_MASK 0x000000FFU

1454

#define LPDDR4__DENALI_PI_71__PI_TDFI_WDQLVL_EN_MASK 0x000000FFU

1455

#define LPDDR4__DENALI_PI_71__PI_TDFI_WDQLVL_EN_SHIFT 0U

1456

#define LPDDR4__DENALI_PI_71__PI_TDFI_WDQLVL_EN_WIDTH 8U

1457

#define LPDDR4__PI_TDFI_WDQLVL_EN__REG DENALI_PI_71

1458

#define LPDDR4__PI_TDFI_WDQLVL_EN__FLD LPDDR4__DENALI_PI_71__PI_TDFI_WDQLVL_EN

1459

1460

#define LPDDR4__DENALI_PI_72_READ_MASK 0xFFFFFFFFU

1461

#define LPDDR4__DENALI_PI_72_WRITE_MASK 0xFFFFFFFFU

1462

#define LPDDR4__DENALI_PI_72__PI_TDFI_WDQLVL_RESP_MASK 0xFFFFFFFFU

1463

#define LPDDR4__DENALI_PI_72__PI_TDFI_WDQLVL_RESP_SHIFT 0U

1464

#define LPDDR4__DENALI_PI_72__PI_TDFI_WDQLVL_RESP_WIDTH 32U

1465

#define LPDDR4__PI_TDFI_WDQLVL_RESP__REG DENALI_PI_72

1466

#define LPDDR4__PI_TDFI_WDQLVL_RESP__FLD LPDDR4__DENALI_PI_72__PI_TDFI_WDQLVL_RESP

1467

1468

#define LPDDR4__DENALI_PI_73_READ_MASK 0xFFFFFFFFU

1469

#define LPDDR4__DENALI_PI_73_WRITE_MASK 0xFFFFFFFFU

1470

#define LPDDR4__DENALI_PI_73__PI_TDFI_WDQLVL_MAX_MASK 0xFFFFFFFFU

1471

#define LPDDR4__DENALI_PI_73__PI_TDFI_WDQLVL_MAX_SHIFT 0U

1472

#define LPDDR4__DENALI_PI_73__PI_TDFI_WDQLVL_MAX_WIDTH 32U

1473

#define LPDDR4__PI_TDFI_WDQLVL_MAX__REG DENALI_PI_73

1474

#define LPDDR4__PI_TDFI_WDQLVL_MAX__FLD LPDDR4__DENALI_PI_73__PI_TDFI_WDQLVL_MAX

1475

1476

#define LPDDR4__DENALI_PI_74_READ_MASK 0x0101FFFFU

1477

#define LPDDR4__DENALI_PI_74_WRITE_MASK 0x0101FFFFU

1478

#define LPDDR4__DENALI_PI_74__PI_WDQLVL_INTERVAL_MASK 0x0000FFFFU

1479

#define LPDDR4__DENALI_PI_74__PI_WDQLVL_INTERVAL_SHIFT 0U

1480

#define LPDDR4__DENALI_PI_74__PI_WDQLVL_INTERVAL_WIDTH 16U

1481

#define LPDDR4__PI_WDQLVL_INTERVAL__REG DENALI_PI_74

1482

#define LPDDR4__PI_WDQLVL_INTERVAL__FLD LPDDR4__DENALI_PI_74__PI_WDQLVL_INTERVAL

1483

1484

#define LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_SREF_EXIT_MASK 0x00010000U

1485

#define LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_SREF_EXIT_SHIFT 16U

1486

#define LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_SREF_EXIT_WIDTH 1U

1487

#define LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_SREF_EXIT_WOCLR 0U

1488

#define LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_SREF_EXIT_WOSET 0U

1489

#define LPDDR4__PI_WDQLVL_ON_SREF_EXIT__REG DENALI_PI_74

1490

#define LPDDR4__PI_WDQLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_SREF_EXIT

1491

1492

#define LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_MPD_EXIT_MASK 0x01000000U

1493

#define LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_MPD_EXIT_SHIFT 24U

1494

#define LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_MPD_EXIT_WIDTH 1U

1495

#define LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_MPD_EXIT_WOCLR 0U

1496

#define LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_MPD_EXIT_WOSET 0U

1497

#define LPDDR4__PI_WDQLVL_ON_MPD_EXIT__REG DENALI_PI_74

1498

#define LPDDR4__PI_WDQLVL_ON_MPD_EXIT__FLD LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_MPD_EXIT

1499

1500

#define LPDDR4__DENALI_PI_75_READ_MASK 0x00030301U

1501

#define LPDDR4__DENALI_PI_75_WRITE_MASK 0x00030301U

1502

#define LPDDR4__DENALI_PI_75__PI_WDQLVL_DISABLE_DFS_MASK 0x00000001U

1503

#define LPDDR4__DENALI_PI_75__PI_WDQLVL_DISABLE_DFS_SHIFT 0U

1504

#define LPDDR4__DENALI_PI_75__PI_WDQLVL_DISABLE_DFS_WIDTH 1U

1505

#define LPDDR4__DENALI_PI_75__PI_WDQLVL_DISABLE_DFS_WOCLR 0U

1506

#define LPDDR4__DENALI_PI_75__PI_WDQLVL_DISABLE_DFS_WOSET 0U

1507

#define LPDDR4__PI_WDQLVL_DISABLE_DFS__REG DENALI_PI_75

1508

#define LPDDR4__PI_WDQLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_75__PI_WDQLVL_DISABLE_DFS

1509

1510

#define LPDDR4__DENALI_PI_75__PI_WDQLVL_ERROR_STATUS_MASK 0x00000300U

1511

#define LPDDR4__DENALI_PI_75__PI_WDQLVL_ERROR_STATUS_SHIFT 8U

1512

#define LPDDR4__DENALI_PI_75__PI_WDQLVL_ERROR_STATUS_WIDTH 2U

1513

#define LPDDR4__PI_WDQLVL_ERROR_STATUS__REG DENALI_PI_75

1514

#define LPDDR4__PI_WDQLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_75__PI_WDQLVL_ERROR_STATUS

1515

1516

#define LPDDR4__DENALI_PI_75__PI_WDQLVL_NEED_SAVE_RESTORE_MASK 0x00030000U

1517

#define LPDDR4__DENALI_PI_75__PI_WDQLVL_NEED_SAVE_RESTORE_SHIFT 16U

1518

#define LPDDR4__DENALI_PI_75__PI_WDQLVL_NEED_SAVE_RESTORE_WIDTH 2U

1519

#define LPDDR4__PI_WDQLVL_NEED_SAVE_RESTORE__REG DENALI_PI_75

1520

#define LPDDR4__PI_WDQLVL_NEED_SAVE_RESTORE__FLD LPDDR4__DENALI_PI_75__PI_WDQLVL_NEED_SAVE_RESTORE

1521

1522

#define LPDDR4__DENALI_PI_76_READ_MASK 0xFFFFFFFFU

1523

#define LPDDR4__DENALI_PI_76_WRITE_MASK 0xFFFFFFFFU

1524

#define LPDDR4__DENALI_PI_76__PI_WDQLVL_DRAM_LVL_START_ADDR_0_MASK 0xFFFFFFFFU

1525

#define LPDDR4__DENALI_PI_76__PI_WDQLVL_DRAM_LVL_START_ADDR_0_SHIFT 0U

1526

#define LPDDR4__DENALI_PI_76__PI_WDQLVL_DRAM_LVL_START_ADDR_0_WIDTH 32U

1527

#define LPDDR4__PI_WDQLVL_DRAM_LVL_START_ADDR_0__REG DENALI_PI_76

1528

#define LPDDR4__PI_WDQLVL_DRAM_LVL_START_ADDR_0__FLD LPDDR4__DENALI_PI_76__PI_WDQLVL_DRAM_LVL_START_ADDR_0

1529

1530

#define LPDDR4__DENALI_PI_77_READ_MASK 0x00010107U

1531

#define LPDDR4__DENALI_PI_77_WRITE_MASK 0x00010107U

1532

#define LPDDR4__DENALI_PI_77__PI_WDQLVL_DRAM_LVL_START_ADDR_1_MASK 0x00000007U

1533

#define LPDDR4__DENALI_PI_77__PI_WDQLVL_DRAM_LVL_START_ADDR_1_SHIFT 0U

1534

#define LPDDR4__DENALI_PI_77__PI_WDQLVL_DRAM_LVL_START_ADDR_1_WIDTH 3U

1535

#define LPDDR4__PI_WDQLVL_DRAM_LVL_START_ADDR_1__REG DENALI_PI_77

1536

#define LPDDR4__PI_WDQLVL_DRAM_LVL_START_ADDR_1__FLD LPDDR4__DENALI_PI_77__PI_WDQLVL_DRAM_LVL_START_ADDR_1

1537

1538

#define LPDDR4__DENALI_PI_77__PI_WDQLVL_DM_LEVEL_EN_MASK 0x00000100U

1539

#define LPDDR4__DENALI_PI_77__PI_WDQLVL_DM_LEVEL_EN_SHIFT 8U

1540

#define LPDDR4__DENALI_PI_77__PI_WDQLVL_DM_LEVEL_EN_WIDTH 1U

1541

#define LPDDR4__DENALI_PI_77__PI_WDQLVL_DM_LEVEL_EN_WOCLR 0U

1542

#define LPDDR4__DENALI_PI_77__PI_WDQLVL_DM_LEVEL_EN_WOSET 0U

1543

#define LPDDR4__PI_WDQLVL_DM_LEVEL_EN__REG DENALI_PI_77

1544

#define LPDDR4__PI_WDQLVL_DM_LEVEL_EN__FLD LPDDR4__DENALI_PI_77__PI_WDQLVL_DM_LEVEL_EN

1545

1546

#define LPDDR4__DENALI_PI_77__PI_NO_MEMORY_DM_MASK 0x00010000U

1547

#define LPDDR4__DENALI_PI_77__PI_NO_MEMORY_DM_SHIFT 16U

1548

#define LPDDR4__DENALI_PI_77__PI_NO_MEMORY_DM_WIDTH 1U

1549

#define LPDDR4__DENALI_PI_77__PI_NO_MEMORY_DM_WOCLR 0U

1550

#define LPDDR4__DENALI_PI_77__PI_NO_MEMORY_DM_WOSET 0U

1551

#define LPDDR4__PI_NO_MEMORY_DM__REG DENALI_PI_77

1552

#define LPDDR4__PI_NO_MEMORY_DM__FLD LPDDR4__DENALI_PI_77__PI_NO_MEMORY_DM

1553

1554

#define LPDDR4__DENALI_PI_78_READ_MASK 0x010003FFU

1555

#define LPDDR4__DENALI_PI_78_WRITE_MASK 0x010003FFU

1556

#define LPDDR4__DENALI_PI_78__PI_TDFI_WDQLVL_WW_MASK 0x000003FFU

1557

#define LPDDR4__DENALI_PI_78__PI_TDFI_WDQLVL_WW_SHIFT 0U

1558

#define LPDDR4__DENALI_PI_78__PI_TDFI_WDQLVL_WW_WIDTH 10U

1559

#define LPDDR4__PI_TDFI_WDQLVL_WW__REG DENALI_PI_78

1560

#define LPDDR4__PI_TDFI_WDQLVL_WW__FLD LPDDR4__DENALI_PI_78__PI_TDFI_WDQLVL_WW

1561

1562

#define LPDDR4__DENALI_PI_78__PI_SWLVL_SM2_DM_NIBBLE_START_MASK 0x00010000U

1563

#define LPDDR4__DENALI_PI_78__PI_SWLVL_SM2_DM_NIBBLE_START_SHIFT 16U

1564

#define LPDDR4__DENALI_PI_78__PI_SWLVL_SM2_DM_NIBBLE_START_WIDTH 1U

1565

#define LPDDR4__DENALI_PI_78__PI_SWLVL_SM2_DM_NIBBLE_START_WOCLR 0U

1566

#define LPDDR4__DENALI_PI_78__PI_SWLVL_SM2_DM_NIBBLE_START_WOSET 0U

1567

#define LPDDR4__PI_SWLVL_SM2_DM_NIBBLE_START__REG DENALI_PI_78

1568

#define LPDDR4__PI_SWLVL_SM2_DM_NIBBLE_START__FLD LPDDR4__DENALI_PI_78__PI_SWLVL_SM2_DM_NIBBLE_START

1569

1570

#define LPDDR4__DENALI_PI_78__PI_WDQLVL_NIBBLE_MODE_MASK 0x01000000U

1571

#define LPDDR4__DENALI_PI_78__PI_WDQLVL_NIBBLE_MODE_SHIFT 24U

1572

#define LPDDR4__DENALI_PI_78__PI_WDQLVL_NIBBLE_MODE_WIDTH 1U

1573

#define LPDDR4__DENALI_PI_78__PI_WDQLVL_NIBBLE_MODE_WOCLR 0U

1574

#define LPDDR4__DENALI_PI_78__PI_WDQLVL_NIBBLE_MODE_WOSET 0U

1575

#define LPDDR4__PI_WDQLVL_NIBBLE_MODE__REG DENALI_PI_78

1576

#define LPDDR4__PI_WDQLVL_NIBBLE_MODE__FLD LPDDR4__DENALI_PI_78__PI_WDQLVL_NIBBLE_MODE

1577

1578

#define LPDDR4__DENALI_PI_79_READ_MASK 0x01010101U

1579

#define LPDDR4__DENALI_PI_79_WRITE_MASK 0x01010101U

1580

#define LPDDR4__DENALI_PI_79__PI_WDQLVL_OSC_EN_MASK 0x00000001U

1581

#define LPDDR4__DENALI_PI_79__PI_WDQLVL_OSC_EN_SHIFT 0U

1582

#define LPDDR4__DENALI_PI_79__PI_WDQLVL_OSC_EN_WIDTH 1U

1583

#define LPDDR4__DENALI_PI_79__PI_WDQLVL_OSC_EN_WOCLR 0U

1584

#define LPDDR4__DENALI_PI_79__PI_WDQLVL_OSC_EN_WOSET 0U

1585

#define LPDDR4__PI_WDQLVL_OSC_EN__REG DENALI_PI_79

1586

#define LPDDR4__PI_WDQLVL_OSC_EN__FLD LPDDR4__DENALI_PI_79__PI_WDQLVL_OSC_EN

1587

1588

#define LPDDR4__DENALI_PI_79__PI_DQS_OSC_PERIOD_EN_MASK 0x00000100U

1589

#define LPDDR4__DENALI_PI_79__PI_DQS_OSC_PERIOD_EN_SHIFT 8U

1590

#define LPDDR4__DENALI_PI_79__PI_DQS_OSC_PERIOD_EN_WIDTH 1U

1591

#define LPDDR4__DENALI_PI_79__PI_DQS_OSC_PERIOD_EN_WOCLR 0U

1592

#define LPDDR4__DENALI_PI_79__PI_DQS_OSC_PERIOD_EN_WOSET 0U

1593

#define LPDDR4__PI_DQS_OSC_PERIOD_EN__REG DENALI_PI_79

1594

#define LPDDR4__PI_DQS_OSC_PERIOD_EN__FLD LPDDR4__DENALI_PI_79__PI_DQS_OSC_PERIOD_EN

1595

1596

#define LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_EN_MASK 0x00010000U

1597

#define LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_EN_SHIFT 16U

1598

#define LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_EN_WIDTH 1U

1599

#define LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_EN_WOCLR 0U

1600

#define LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_EN_WOSET 0U

1601

#define LPDDR4__PI_WDQLVL_PDA_EN__REG DENALI_PI_79

1602

#define LPDDR4__PI_WDQLVL_PDA_EN__FLD LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_EN

1603

1604

#define LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_VREF_TRAIN_MASK 0x01000000U

1605

#define LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_VREF_TRAIN_SHIFT 24U

1606

#define LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_VREF_TRAIN_WIDTH 1U

1607

#define LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_VREF_TRAIN_WOCLR 0U

1608

#define LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_VREF_TRAIN_WOSET 0U

1609

#define LPDDR4__PI_WDQLVL_PDA_VREF_TRAIN__REG DENALI_PI_79

1610

#define LPDDR4__PI_WDQLVL_PDA_VREF_TRAIN__FLD LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_VREF_TRAIN

1611

1612

#define LPDDR4__DENALI_PI_80_READ_MASK 0x07030F01U

1613

#define LPDDR4__DENALI_PI_80_WRITE_MASK 0x07030F01U

1614

#define LPDDR4__DENALI_PI_80__PI_PARALLEL_WDQLVL_EN_MASK 0x00000001U

1615

#define LPDDR4__DENALI_PI_80__PI_PARALLEL_WDQLVL_EN_SHIFT 0U

1616

#define LPDDR4__DENALI_PI_80__PI_PARALLEL_WDQLVL_EN_WIDTH 1U

1617

#define LPDDR4__DENALI_PI_80__PI_PARALLEL_WDQLVL_EN_WOCLR 0U

1618

#define LPDDR4__DENALI_PI_80__PI_PARALLEL_WDQLVL_EN_WOSET 0U

1619

#define LPDDR4__PI_PARALLEL_WDQLVL_EN__REG DENALI_PI_80

1620

#define LPDDR4__PI_PARALLEL_WDQLVL_EN__FLD LPDDR4__DENALI_PI_80__PI_PARALLEL_WDQLVL_EN

1621

1622

#define LPDDR4__DENALI_PI_80__PI_DBILVL_RESP_MASK_MASK 0x00000F00U

1623

#define LPDDR4__DENALI_PI_80__PI_DBILVL_RESP_MASK_SHIFT 8U

1624

#define LPDDR4__DENALI_PI_80__PI_DBILVL_RESP_MASK_WIDTH 4U

1625

#define LPDDR4__PI_DBILVL_RESP_MASK__REG DENALI_PI_80

1626

#define LPDDR4__PI_DBILVL_RESP_MASK__FLD LPDDR4__DENALI_PI_80__PI_DBILVL_RESP_MASK

1627

1628

#define LPDDR4__DENALI_PI_80__PI_BANK_DIFF_MASK 0x00030000U

1629

#define LPDDR4__DENALI_PI_80__PI_BANK_DIFF_SHIFT 16U

1630

#define LPDDR4__DENALI_PI_80__PI_BANK_DIFF_WIDTH 2U

1631

#define LPDDR4__PI_BANK_DIFF__REG DENALI_PI_80

1632

#define LPDDR4__PI_BANK_DIFF__FLD LPDDR4__DENALI_PI_80__PI_BANK_DIFF

1633

1634

#define LPDDR4__DENALI_PI_80__PI_ROW_DIFF_MASK 0x07000000U

1635

#define LPDDR4__DENALI_PI_80__PI_ROW_DIFF_SHIFT 24U

1636

#define LPDDR4__DENALI_PI_80__PI_ROW_DIFF_WIDTH 3U

1637

#define LPDDR4__PI_ROW_DIFF__REG DENALI_PI_80

1638

#define LPDDR4__PI_ROW_DIFF__FLD LPDDR4__DENALI_PI_80__PI_ROW_DIFF

1639

1640

#define LPDDR4__DENALI_PI_81_READ_MASK 0x0F0F0F1FU

1641

#define LPDDR4__DENALI_PI_81_WRITE_MASK 0x0F0F0F1FU

1642

#define LPDDR4__DENALI_PI_81__PI_TCCD_MASK 0x0000001FU

1643

#define LPDDR4__DENALI_PI_81__PI_TCCD_SHIFT 0U

1644

#define LPDDR4__DENALI_PI_81__PI_TCCD_WIDTH 5U

1645

#define LPDDR4__PI_TCCD__REG DENALI_PI_81

1646

#define LPDDR4__PI_TCCD__FLD LPDDR4__DENALI_PI_81__PI_TCCD

1647

1648

#define LPDDR4__DENALI_PI_81__PI_RESERVED7_MASK 0x00000F00U

1649

#define LPDDR4__DENALI_PI_81__PI_RESERVED7_SHIFT 8U

1650

#define LPDDR4__DENALI_PI_81__PI_RESERVED7_WIDTH 4U

1651

#define LPDDR4__PI_RESERVED7__REG DENALI_PI_81

1652

#define LPDDR4__PI_RESERVED7__FLD LPDDR4__DENALI_PI_81__PI_RESERVED7

1653

1654

#define LPDDR4__DENALI_PI_81__PI_RESERVED8_MASK 0x000F0000U

1655

#define LPDDR4__DENALI_PI_81__PI_RESERVED8_SHIFT 16U

1656

#define LPDDR4__DENALI_PI_81__PI_RESERVED8_WIDTH 4U

1657

#define LPDDR4__PI_RESERVED8__REG DENALI_PI_81

1658

#define LPDDR4__PI_RESERVED8__FLD LPDDR4__DENALI_PI_81__PI_RESERVED8

1659

1660

#define LPDDR4__DENALI_PI_81__PI_RESERVED9_MASK 0x0F000000U

1661

#define LPDDR4__DENALI_PI_81__PI_RESERVED9_SHIFT 24U

1662

#define LPDDR4__DENALI_PI_81__PI_RESERVED9_WIDTH 4U

1663

#define LPDDR4__PI_RESERVED9__REG DENALI_PI_81

1664

#define LPDDR4__PI_RESERVED9__FLD LPDDR4__DENALI_PI_81__PI_RESERVED9

1665

1666

#define LPDDR4__DENALI_PI_82_READ_MASK 0x0F0F0F0FU

1667

#define LPDDR4__DENALI_PI_82_WRITE_MASK 0x0F0F0F0FU

1668

#define LPDDR4__DENALI_PI_82__PI_RESERVED10_MASK 0x0000000FU

1669

#define LPDDR4__DENALI_PI_82__PI_RESERVED10_SHIFT 0U

1670

#define LPDDR4__DENALI_PI_82__PI_RESERVED10_WIDTH 4U

1671

#define LPDDR4__PI_RESERVED10__REG DENALI_PI_82

1672

#define LPDDR4__PI_RESERVED10__FLD LPDDR4__DENALI_PI_82__PI_RESERVED10

1673

1674

#define LPDDR4__DENALI_PI_82__PI_RESERVED11_MASK 0x00000F00U

1675

#define LPDDR4__DENALI_PI_82__PI_RESERVED11_SHIFT 8U

1676

#define LPDDR4__DENALI_PI_82__PI_RESERVED11_WIDTH 4U

1677

#define LPDDR4__PI_RESERVED11__REG DENALI_PI_82

1678

#define LPDDR4__PI_RESERVED11__FLD LPDDR4__DENALI_PI_82__PI_RESERVED11

1679

1680

#define LPDDR4__DENALI_PI_82__PI_RESERVED12_MASK 0x000F0000U

1681

#define LPDDR4__DENALI_PI_82__PI_RESERVED12_SHIFT 16U

1682

#define LPDDR4__DENALI_PI_82__PI_RESERVED12_WIDTH 4U

1683

#define LPDDR4__PI_RESERVED12__REG DENALI_PI_82

1684

#define LPDDR4__PI_RESERVED12__FLD LPDDR4__DENALI_PI_82__PI_RESERVED12

1685

1686

#define LPDDR4__DENALI_PI_82__PI_RESERVED13_MASK 0x0F000000U

1687

#define LPDDR4__DENALI_PI_82__PI_RESERVED13_SHIFT 24U

1688

#define LPDDR4__DENALI_PI_82__PI_RESERVED13_WIDTH 4U

1689

#define LPDDR4__PI_RESERVED13__REG DENALI_PI_82

1690

#define LPDDR4__PI_RESERVED13__FLD LPDDR4__DENALI_PI_82__PI_RESERVED13

1691

1692

#define LPDDR4__DENALI_PI_83_READ_MASK 0x0F0F0F0FU

1693

#define LPDDR4__DENALI_PI_83_WRITE_MASK 0x0F0F0F0FU

1694

#define LPDDR4__DENALI_PI_83__PI_RESERVED14_MASK 0x0000000FU

1695

#define LPDDR4__DENALI_PI_83__PI_RESERVED14_SHIFT 0U

1696

#define LPDDR4__DENALI_PI_83__PI_RESERVED14_WIDTH 4U

1697

#define LPDDR4__PI_RESERVED14__REG DENALI_PI_83

1698

#define LPDDR4__PI_RESERVED14__FLD LPDDR4__DENALI_PI_83__PI_RESERVED14

1699

1700

#define LPDDR4__DENALI_PI_83__PI_RESERVED15_MASK 0x00000F00U

1701

#define LPDDR4__DENALI_PI_83__PI_RESERVED15_SHIFT 8U

1702

#define LPDDR4__DENALI_PI_83__PI_RESERVED15_WIDTH 4U

1703

#define LPDDR4__PI_RESERVED15__REG DENALI_PI_83

1704

#define LPDDR4__PI_RESERVED15__FLD LPDDR4__DENALI_PI_83__PI_RESERVED15

1705

1706

#define LPDDR4__DENALI_PI_83__PI_RESERVED16_MASK 0x000F0000U

1707

#define LPDDR4__DENALI_PI_83__PI_RESERVED16_SHIFT 16U

1708

#define LPDDR4__DENALI_PI_83__PI_RESERVED16_WIDTH 4U

1709

#define LPDDR4__PI_RESERVED16__REG DENALI_PI_83

1710

#define LPDDR4__PI_RESERVED16__FLD LPDDR4__DENALI_PI_83__PI_RESERVED16

1711

1712

#define LPDDR4__DENALI_PI_83__PI_RESERVED17_MASK 0x0F000000U

1713

#define LPDDR4__DENALI_PI_83__PI_RESERVED17_SHIFT 24U

1714

#define LPDDR4__DENALI_PI_83__PI_RESERVED17_WIDTH 4U

1715

#define LPDDR4__PI_RESERVED17__REG DENALI_PI_83

1716

#define LPDDR4__PI_RESERVED17__FLD LPDDR4__DENALI_PI_83__PI_RESERVED17

1717

1718

#define LPDDR4__DENALI_PI_84_READ_MASK 0x0F0F0F0FU

1719

#define LPDDR4__DENALI_PI_84_WRITE_MASK 0x0F0F0F0FU

1720

#define LPDDR4__DENALI_PI_84__PI_RESERVED18_MASK 0x0000000FU

1721

#define LPDDR4__DENALI_PI_84__PI_RESERVED18_SHIFT 0U

1722

#define LPDDR4__DENALI_PI_84__PI_RESERVED18_WIDTH 4U

1723

#define LPDDR4__PI_RESERVED18__REG DENALI_PI_84

1724

#define LPDDR4__PI_RESERVED18__FLD LPDDR4__DENALI_PI_84__PI_RESERVED18

1725

1726

#define LPDDR4__DENALI_PI_84__PI_RESERVED19_MASK 0x00000F00U

1727

#define LPDDR4__DENALI_PI_84__PI_RESERVED19_SHIFT 8U

1728

#define LPDDR4__DENALI_PI_84__PI_RESERVED19_WIDTH 4U

1729

#define LPDDR4__PI_RESERVED19__REG DENALI_PI_84

1730

#define LPDDR4__PI_RESERVED19__FLD LPDDR4__DENALI_PI_84__PI_RESERVED19

1731

1732

#define LPDDR4__DENALI_PI_84__PI_RESERVED20_MASK 0x000F0000U

1733

#define LPDDR4__DENALI_PI_84__PI_RESERVED20_SHIFT 16U

1734

#define LPDDR4__DENALI_PI_84__PI_RESERVED20_WIDTH 4U

1735

#define LPDDR4__PI_RESERVED20__REG DENALI_PI_84

1736

#define LPDDR4__PI_RESERVED20__FLD LPDDR4__DENALI_PI_84__PI_RESERVED20

1737

1738

#define LPDDR4__DENALI_PI_84__PI_RESERVED21_MASK 0x0F000000U

1739

#define LPDDR4__DENALI_PI_84__PI_RESERVED21_SHIFT 24U

1740

#define LPDDR4__DENALI_PI_84__PI_RESERVED21_WIDTH 4U

1741

#define LPDDR4__PI_RESERVED21__REG DENALI_PI_84

1742

#define LPDDR4__PI_RESERVED21__FLD LPDDR4__DENALI_PI_84__PI_RESERVED21

1743

1744

#define LPDDR4__DENALI_PI_85_READ_MASK 0x0F0F0F0FU

1745

#define LPDDR4__DENALI_PI_85_WRITE_MASK 0x0F0F0F0FU

1746

#define LPDDR4__DENALI_PI_85__PI_RESERVED22_MASK 0x0000000FU

1747

#define LPDDR4__DENALI_PI_85__PI_RESERVED22_SHIFT 0U

1748

#define LPDDR4__DENALI_PI_85__PI_RESERVED22_WIDTH 4U

1749

#define LPDDR4__PI_RESERVED22__REG DENALI_PI_85

1750

#define LPDDR4__PI_RESERVED22__FLD LPDDR4__DENALI_PI_85__PI_RESERVED22

1751

1752

#define LPDDR4__DENALI_PI_85__PI_RESERVED23_MASK 0x00000F00U

1753

#define LPDDR4__DENALI_PI_85__PI_RESERVED23_SHIFT 8U

1754

#define LPDDR4__DENALI_PI_85__PI_RESERVED23_WIDTH 4U

1755

#define LPDDR4__PI_RESERVED23__REG DENALI_PI_85

1756

#define LPDDR4__PI_RESERVED23__FLD LPDDR4__DENALI_PI_85__PI_RESERVED23

1757

1758

#define LPDDR4__DENALI_PI_85__PI_RESERVED24_MASK 0x000F0000U

1759

#define LPDDR4__DENALI_PI_85__PI_RESERVED24_SHIFT 16U

1760

#define LPDDR4__DENALI_PI_85__PI_RESERVED24_WIDTH 4U

1761

#define LPDDR4__PI_RESERVED24__REG DENALI_PI_85

1762

#define LPDDR4__PI_RESERVED24__FLD LPDDR4__DENALI_PI_85__PI_RESERVED24

1763

1764

#define LPDDR4__DENALI_PI_85__PI_RESERVED25_MASK 0x0F000000U

1765

#define LPDDR4__DENALI_PI_85__PI_RESERVED25_SHIFT 24U

1766

#define LPDDR4__DENALI_PI_85__PI_RESERVED25_WIDTH 4U

1767

#define LPDDR4__PI_RESERVED25__REG DENALI_PI_85

1768

#define LPDDR4__PI_RESERVED25__FLD LPDDR4__DENALI_PI_85__PI_RESERVED25

1769

1770

#define LPDDR4__DENALI_PI_86_READ_MASK 0x0000000FU

1771

#define LPDDR4__DENALI_PI_86_WRITE_MASK 0x0000000FU

1772

#define LPDDR4__DENALI_PI_86__PI_RESERVED26_MASK 0x0000000FU

1773

#define LPDDR4__DENALI_PI_86__PI_RESERVED26_SHIFT 0U

1774

#define LPDDR4__DENALI_PI_86__PI_RESERVED26_WIDTH 4U

1775

#define LPDDR4__PI_RESERVED26__REG DENALI_PI_86

1776

#define LPDDR4__PI_RESERVED26__FLD LPDDR4__DENALI_PI_86__PI_RESERVED26

1777

1778

#define LPDDR4__DENALI_PI_87_READ_MASK 0x3FFFFFFFU

1779

#define LPDDR4__DENALI_PI_87_WRITE_MASK 0x3FFFFFFFU

1780

#define LPDDR4__DENALI_PI_87__PI_INT_STATUS_MASK 0x3FFFFFFFU

1781

#define LPDDR4__DENALI_PI_87__PI_INT_STATUS_SHIFT 0U

1782

#define LPDDR4__DENALI_PI_87__PI_INT_STATUS_WIDTH 30U

1783

#define LPDDR4__PI_INT_STATUS__REG DENALI_PI_87

1784

#define LPDDR4__PI_INT_STATUS__FLD LPDDR4__DENALI_PI_87__PI_INT_STATUS

1785

1786

#define LPDDR4__DENALI_PI_88__PI_INT_ACK_MASK 0x1FFFFFFFU

1787

#define LPDDR4__DENALI_PI_88__PI_INT_ACK_SHIFT 0U

1788

#define LPDDR4__DENALI_PI_88__PI_INT_ACK_WIDTH 29U

1789

#define LPDDR4__PI_INT_ACK__REG DENALI_PI_88

1790

#define LPDDR4__PI_INT_ACK__FLD LPDDR4__DENALI_PI_88__PI_INT_ACK

1791

1792

#define LPDDR4__DENALI_PI_89_READ_MASK 0x3FFFFFFFU

1793

#define LPDDR4__DENALI_PI_89_WRITE_MASK 0x3FFFFFFFU

1794

#define LPDDR4__DENALI_PI_89__PI_INT_MASK_MASK 0x3FFFFFFFU

1795

#define LPDDR4__DENALI_PI_89__PI_INT_MASK_SHIFT 0U

1796

#define LPDDR4__DENALI_PI_89__PI_INT_MASK_WIDTH 30U

1797

#define LPDDR4__PI_INT_MASK__REG DENALI_PI_89

1798

#define LPDDR4__PI_INT_MASK__FLD LPDDR4__DENALI_PI_89__PI_INT_MASK

1799

1800

#define LPDDR4__DENALI_PI_90_READ_MASK 0xFFFFFFFFU

1801

#define LPDDR4__DENALI_PI_90_WRITE_MASK 0xFFFFFFFFU

1802

#define LPDDR4__DENALI_PI_90__PI_BIST_EXP_DATA_0_MASK 0xFFFFFFFFU

1803

#define LPDDR4__DENALI_PI_90__PI_BIST_EXP_DATA_0_SHIFT 0U

1804

#define LPDDR4__DENALI_PI_90__PI_BIST_EXP_DATA_0_WIDTH 32U

1805

#define LPDDR4__PI_BIST_EXP_DATA_0__REG DENALI_PI_90

1806

#define LPDDR4__PI_BIST_EXP_DATA_0__FLD LPDDR4__DENALI_PI_90__PI_BIST_EXP_DATA_0

1807

1808

#define LPDDR4__DENALI_PI_91_READ_MASK 0xFFFFFFFFU

1809

#define LPDDR4__DENALI_PI_91_WRITE_MASK 0xFFFFFFFFU

1810

#define LPDDR4__DENALI_PI_91__PI_BIST_EXP_DATA_1_MASK 0xFFFFFFFFU

1811

#define LPDDR4__DENALI_PI_91__PI_BIST_EXP_DATA_1_SHIFT 0U

1812

#define LPDDR4__DENALI_PI_91__PI_BIST_EXP_DATA_1_WIDTH 32U

1813

#define LPDDR4__PI_BIST_EXP_DATA_1__REG DENALI_PI_91

1814

#define LPDDR4__PI_BIST_EXP_DATA_1__FLD LPDDR4__DENALI_PI_91__PI_BIST_EXP_DATA_1

1815

1816

#define LPDDR4__DENALI_PI_92_READ_MASK 0xFFFFFFFFU

1817

#define LPDDR4__DENALI_PI_92_WRITE_MASK 0xFFFFFFFFU

1818

#define LPDDR4__DENALI_PI_92__PI_BIST_EXP_DATA_2_MASK 0xFFFFFFFFU

1819

#define LPDDR4__DENALI_PI_92__PI_BIST_EXP_DATA_2_SHIFT 0U

1820

#define LPDDR4__DENALI_PI_92__PI_BIST_EXP_DATA_2_WIDTH 32U

1821

#define LPDDR4__PI_BIST_EXP_DATA_2__REG DENALI_PI_92

1822

#define LPDDR4__PI_BIST_EXP_DATA_2__FLD LPDDR4__DENALI_PI_92__PI_BIST_EXP_DATA_2

1823

1824

#define LPDDR4__DENALI_PI_93_READ_MASK 0xFFFFFFFFU

1825

#define LPDDR4__DENALI_PI_93_WRITE_MASK 0xFFFFFFFFU

1826

#define LPDDR4__DENALI_PI_93__PI_BIST_EXP_DATA_3_MASK 0xFFFFFFFFU

1827

#define LPDDR4__DENALI_PI_93__PI_BIST_EXP_DATA_3_SHIFT 0U

1828

#define LPDDR4__DENALI_PI_93__PI_BIST_EXP_DATA_3_WIDTH 32U

1829

#define LPDDR4__PI_BIST_EXP_DATA_3__REG DENALI_PI_93

1830

#define LPDDR4__PI_BIST_EXP_DATA_3__FLD LPDDR4__DENALI_PI_93__PI_BIST_EXP_DATA_3

1831

1832

#define LPDDR4__DENALI_PI_94_READ_MASK 0xFFFFFFFFU

1833

#define LPDDR4__DENALI_PI_94_WRITE_MASK 0xFFFFFFFFU

1834

#define LPDDR4__DENALI_PI_94__PI_BIST_FAIL_DATA_0_MASK 0xFFFFFFFFU

1835

#define LPDDR4__DENALI_PI_94__PI_BIST_FAIL_DATA_0_SHIFT 0U

1836

#define LPDDR4__DENALI_PI_94__PI_BIST_FAIL_DATA_0_WIDTH 32U

1837

#define LPDDR4__PI_BIST_FAIL_DATA_0__REG DENALI_PI_94

1838

#define LPDDR4__PI_BIST_FAIL_DATA_0__FLD LPDDR4__DENALI_PI_94__PI_BIST_FAIL_DATA_0

1839

1840

#define LPDDR4__DENALI_PI_95_READ_MASK 0xFFFFFFFFU

1841

#define LPDDR4__DENALI_PI_95_WRITE_MASK 0xFFFFFFFFU

1842

#define LPDDR4__DENALI_PI_95__PI_BIST_FAIL_DATA_1_MASK 0xFFFFFFFFU

1843

#define LPDDR4__DENALI_PI_95__PI_BIST_FAIL_DATA_1_SHIFT 0U

1844

#define LPDDR4__DENALI_PI_95__PI_BIST_FAIL_DATA_1_WIDTH 32U

1845

#define LPDDR4__PI_BIST_FAIL_DATA_1__REG DENALI_PI_95

1846

#define LPDDR4__PI_BIST_FAIL_DATA_1__FLD LPDDR4__DENALI_PI_95__PI_BIST_FAIL_DATA_1

1847

1848

#define LPDDR4__DENALI_PI_96_READ_MASK 0xFFFFFFFFU

1849

#define LPDDR4__DENALI_PI_96_WRITE_MASK 0xFFFFFFFFU

1850

#define LPDDR4__DENALI_PI_96__PI_BIST_FAIL_DATA_2_MASK 0xFFFFFFFFU

1851

#define LPDDR4__DENALI_PI_96__PI_BIST_FAIL_DATA_2_SHIFT 0U

1852

#define LPDDR4__DENALI_PI_96__PI_BIST_FAIL_DATA_2_WIDTH 32U

1853

#define LPDDR4__PI_BIST_FAIL_DATA_2__REG DENALI_PI_96

1854

#define LPDDR4__PI_BIST_FAIL_DATA_2__FLD LPDDR4__DENALI_PI_96__PI_BIST_FAIL_DATA_2

1855

1856

#define LPDDR4__DENALI_PI_97_READ_MASK 0xFFFFFFFFU

1857

#define LPDDR4__DENALI_PI_97_WRITE_MASK 0xFFFFFFFFU

1858

#define LPDDR4__DENALI_PI_97__PI_BIST_FAIL_DATA_3_MASK 0xFFFFFFFFU

1859

#define LPDDR4__DENALI_PI_97__PI_BIST_FAIL_DATA_3_SHIFT 0U

1860

#define LPDDR4__DENALI_PI_97__PI_BIST_FAIL_DATA_3_WIDTH 32U

1861

#define LPDDR4__PI_BIST_FAIL_DATA_3__REG DENALI_PI_97

1862

#define LPDDR4__PI_BIST_FAIL_DATA_3__FLD LPDDR4__DENALI_PI_97__PI_BIST_FAIL_DATA_3

1863

1864

#define LPDDR4__DENALI_PI_98_READ_MASK 0xFFFFFFFFU

1865

#define LPDDR4__DENALI_PI_98_WRITE_MASK 0xFFFFFFFFU

1866

#define LPDDR4__DENALI_PI_98__PI_BIST_FAIL_ADDR_0_MASK 0xFFFFFFFFU

1867

#define LPDDR4__DENALI_PI_98__PI_BIST_FAIL_ADDR_0_SHIFT 0U

1868

#define LPDDR4__DENALI_PI_98__PI_BIST_FAIL_ADDR_0_WIDTH 32U

1869

#define LPDDR4__PI_BIST_FAIL_ADDR_0__REG DENALI_PI_98

1870

#define LPDDR4__PI_BIST_FAIL_ADDR_0__FLD LPDDR4__DENALI_PI_98__PI_BIST_FAIL_ADDR_0

1871

1872

#define LPDDR4__DENALI_PI_99_READ_MASK 0x011F3F07U

1873

#define LPDDR4__DENALI_PI_99_WRITE_MASK 0x011F3F07U

1874

#define LPDDR4__DENALI_PI_99__PI_BIST_FAIL_ADDR_1_MASK 0x00000007U

1875

#define LPDDR4__DENALI_PI_99__PI_BIST_FAIL_ADDR_1_SHIFT 0U

1876

#define LPDDR4__DENALI_PI_99__PI_BIST_FAIL_ADDR_1_WIDTH 3U

1877

#define LPDDR4__PI_BIST_FAIL_ADDR_1__REG DENALI_PI_99

1878

#define LPDDR4__PI_BIST_FAIL_ADDR_1__FLD LPDDR4__DENALI_PI_99__PI_BIST_FAIL_ADDR_1

1879

1880

#define LPDDR4__DENALI_PI_99__PI_BSTLEN_MASK 0x00003F00U

1881

#define LPDDR4__DENALI_PI_99__PI_BSTLEN_SHIFT 8U

1882

#define LPDDR4__DENALI_PI_99__PI_BSTLEN_WIDTH 6U

1883

#define LPDDR4__PI_BSTLEN__REG DENALI_PI_99

1884

#define LPDDR4__PI_BSTLEN__FLD LPDDR4__DENALI_PI_99__PI_BSTLEN

1885

1886

#define LPDDR4__DENALI_PI_99__PI_LONG_COUNT_MASK_MASK 0x001F0000U

1887

#define LPDDR4__DENALI_PI_99__PI_LONG_COUNT_MASK_SHIFT 16U

1888

#define LPDDR4__DENALI_PI_99__PI_LONG_COUNT_MASK_WIDTH 5U

1889

#define LPDDR4__PI_LONG_COUNT_MASK__REG DENALI_PI_99

1890

#define LPDDR4__PI_LONG_COUNT_MASK__FLD LPDDR4__DENALI_PI_99__PI_LONG_COUNT_MASK

1891

1892

#define LPDDR4__DENALI_PI_99__PI_CMD_SWAP_EN_MASK 0x01000000U

1893

#define LPDDR4__DENALI_PI_99__PI_CMD_SWAP_EN_SHIFT 24U

1894

#define LPDDR4__DENALI_PI_99__PI_CMD_SWAP_EN_WIDTH 1U

1895

#define LPDDR4__DENALI_PI_99__PI_CMD_SWAP_EN_WOCLR 0U

1896

#define LPDDR4__DENALI_PI_99__PI_CMD_SWAP_EN_WOSET 0U

1897

#define LPDDR4__PI_CMD_SWAP_EN__REG DENALI_PI_99

1898

#define LPDDR4__PI_CMD_SWAP_EN__FLD LPDDR4__DENALI_PI_99__PI_CMD_SWAP_EN

1899

1900

#define LPDDR4__DENALI_PI_100_READ_MASK 0x1F1F1F1FU

1901

#define LPDDR4__DENALI_PI_100_WRITE_MASK 0x1F1F1F1FU

1902

#define LPDDR4__DENALI_PI_100__PI_PARITY_IN_MUX_MASK 0x0000001FU

1903

#define LPDDR4__DENALI_PI_100__PI_PARITY_IN_MUX_SHIFT 0U

1904

#define LPDDR4__DENALI_PI_100__PI_PARITY_IN_MUX_WIDTH 5U

1905

#define LPDDR4__PI_PARITY_IN_MUX__REG DENALI_PI_100

1906

#define LPDDR4__PI_PARITY_IN_MUX__FLD LPDDR4__DENALI_PI_100__PI_PARITY_IN_MUX

1907

1908

#define LPDDR4__DENALI_PI_100__PI_ACT_N_MUX_MASK 0x00001F00U

1909

#define LPDDR4__DENALI_PI_100__PI_ACT_N_MUX_SHIFT 8U

1910

#define LPDDR4__DENALI_PI_100__PI_ACT_N_MUX_WIDTH 5U

1911

#define LPDDR4__PI_ACT_N_MUX__REG DENALI_PI_100

1912

#define LPDDR4__PI_ACT_N_MUX__FLD LPDDR4__DENALI_PI_100__PI_ACT_N_MUX

1913

1914

#define LPDDR4__DENALI_PI_100__PI_BG_MUX_0_MASK 0x001F0000U

1915

#define LPDDR4__DENALI_PI_100__PI_BG_MUX_0_SHIFT 16U

1916

#define LPDDR4__DENALI_PI_100__PI_BG_MUX_0_WIDTH 5U

1917

#define LPDDR4__PI_BG_MUX_0__REG DENALI_PI_100

1918

#define LPDDR4__PI_BG_MUX_0__FLD LPDDR4__DENALI_PI_100__PI_BG_MUX_0

1919

1920

#define LPDDR4__DENALI_PI_100__PI_BG_MUX_1_MASK 0x1F000000U

1921

#define LPDDR4__DENALI_PI_100__PI_BG_MUX_1_SHIFT 24U

1922

#define LPDDR4__DENALI_PI_100__PI_BG_MUX_1_WIDTH 5U

1923

#define LPDDR4__PI_BG_MUX_1__REG DENALI_PI_100

1924

#define LPDDR4__PI_BG_MUX_1__FLD LPDDR4__DENALI_PI_100__PI_BG_MUX_1

1925

1926

#define LPDDR4__DENALI_PI_101_READ_MASK 0x1F1F1F1FU

1927

#define LPDDR4__DENALI_PI_101_WRITE_MASK 0x1F1F1F1FU

1928

#define LPDDR4__DENALI_PI_101__PI_RAS_N_MUX_MASK 0x0000001FU

1929

#define LPDDR4__DENALI_PI_101__PI_RAS_N_MUX_SHIFT 0U

1930

#define LPDDR4__DENALI_PI_101__PI_RAS_N_MUX_WIDTH 5U

1931

#define LPDDR4__PI_RAS_N_MUX__REG DENALI_PI_101

1932

#define LPDDR4__PI_RAS_N_MUX__FLD LPDDR4__DENALI_PI_101__PI_RAS_N_MUX

1933

1934

#define LPDDR4__DENALI_PI_101__PI_CAS_N_MUX_MASK 0x00001F00U

1935

#define LPDDR4__DENALI_PI_101__PI_CAS_N_MUX_SHIFT 8U

1936

#define LPDDR4__DENALI_PI_101__PI_CAS_N_MUX_WIDTH 5U

1937

#define LPDDR4__PI_CAS_N_MUX__REG DENALI_PI_101

1938

#define LPDDR4__PI_CAS_N_MUX__FLD LPDDR4__DENALI_PI_101__PI_CAS_N_MUX

1939

1940

#define LPDDR4__DENALI_PI_101__PI_WE_N_MUX_MASK 0x001F0000U

1941

#define LPDDR4__DENALI_PI_101__PI_WE_N_MUX_SHIFT 16U

1942

#define LPDDR4__DENALI_PI_101__PI_WE_N_MUX_WIDTH 5U

1943

#define LPDDR4__PI_WE_N_MUX__REG DENALI_PI_101

1944

#define LPDDR4__PI_WE_N_MUX__FLD LPDDR4__DENALI_PI_101__PI_WE_N_MUX

1945

1946

#define LPDDR4__DENALI_PI_101__PI_BANK_MUX_0_MASK 0x1F000000U

1947

#define LPDDR4__DENALI_PI_101__PI_BANK_MUX_0_SHIFT 24U

1948

#define LPDDR4__DENALI_PI_101__PI_BANK_MUX_0_WIDTH 5U

1949

#define LPDDR4__PI_BANK_MUX_0__REG DENALI_PI_101

1950

#define LPDDR4__PI_BANK_MUX_0__FLD LPDDR4__DENALI_PI_101__PI_BANK_MUX_0

1951

1952

#define LPDDR4__DENALI_PI_102_READ_MASK 0x0303011FU

1953

#define LPDDR4__DENALI_PI_102_WRITE_MASK 0x0303011FU

1954

#define LPDDR4__DENALI_PI_102__PI_BANK_MUX_1_MASK 0x0000001FU

1955

#define LPDDR4__DENALI_PI_102__PI_BANK_MUX_1_SHIFT 0U

1956

#define LPDDR4__DENALI_PI_102__PI_BANK_MUX_1_WIDTH 5U

1957

#define LPDDR4__PI_BANK_MUX_1__REG DENALI_PI_102

1958

#define LPDDR4__PI_BANK_MUX_1__FLD LPDDR4__DENALI_PI_102__PI_BANK_MUX_1

1959

1960

#define LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_EN_MASK 0x00000100U

1961

#define LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_EN_SHIFT 8U

1962

#define LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_EN_WIDTH 1U

1963

#define LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_EN_WOCLR 0U

1964

#define LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_EN_WOSET 0U

1965

#define LPDDR4__PI_DATA_BYTE_SWAP_EN__REG DENALI_PI_102

1966

#define LPDDR4__PI_DATA_BYTE_SWAP_EN__FLD LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_EN

1967

1968

#define LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_SLICE0_MASK 0x00030000U

1969

#define LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_SLICE0_SHIFT 16U

1970

#define LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_SLICE0_WIDTH 2U

1971

#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE0__REG DENALI_PI_102

1972

#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE0__FLD LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_SLICE0

1973

1974

#define LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_SLICE1_MASK 0x03000000U

1975

#define LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_SLICE1_SHIFT 24U

1976

#define LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_SLICE1_WIDTH 2U

1977

#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE1__REG DENALI_PI_102

1978

#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE1__FLD LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_SLICE1

1979

1980

#define LPDDR4__DENALI_PI_103_READ_MASK 0x00010303U

1981

#define LPDDR4__DENALI_PI_103_WRITE_MASK 0x00010303U

1982

#define LPDDR4__DENALI_PI_103__PI_DATA_BYTE_SWAP_SLICE2_MASK 0x00000003U

1983

#define LPDDR4__DENALI_PI_103__PI_DATA_BYTE_SWAP_SLICE2_SHIFT 0U

1984

#define LPDDR4__DENALI_PI_103__PI_DATA_BYTE_SWAP_SLICE2_WIDTH 2U

1985

#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE2__REG DENALI_PI_103

1986

#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE2__FLD LPDDR4__DENALI_PI_103__PI_DATA_BYTE_SWAP_SLICE2

1987

1988

#define LPDDR4__DENALI_PI_103__PI_DATA_BYTE_SWAP_SLICE3_MASK 0x00000300U

1989

#define LPDDR4__DENALI_PI_103__PI_DATA_BYTE_SWAP_SLICE3_SHIFT 8U

1990

#define LPDDR4__DENALI_PI_103__PI_DATA_BYTE_SWAP_SLICE3_WIDTH 2U

1991

#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE3__REG DENALI_PI_103

1992

#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE3__FLD LPDDR4__DENALI_PI_103__PI_DATA_BYTE_SWAP_SLICE3

1993

1994

#define LPDDR4__DENALI_PI_103__PI_CTRLUPD_REQ_PER_AREF_EN_MASK 0x00010000U

1995

#define LPDDR4__DENALI_PI_103__PI_CTRLUPD_REQ_PER_AREF_EN_SHIFT 16U

1996

#define LPDDR4__DENALI_PI_103__PI_CTRLUPD_REQ_PER_AREF_EN_WIDTH 1U

1997

#define LPDDR4__DENALI_PI_103__PI_CTRLUPD_REQ_PER_AREF_EN_WOCLR 0U

1998

#define LPDDR4__DENALI_PI_103__PI_CTRLUPD_REQ_PER_AREF_EN_WOSET 0U

1999

#define LPDDR4__PI_CTRLUPD_REQ_PER_AREF_EN__REG DENALI_PI_103

2000

#define LPDDR4__PI_CTRLUPD_REQ_PER_AREF_EN__FLD LPDDR4__DENALI_PI_103__PI_CTRLUPD_REQ_PER_AREF_EN

2001

2002

#define LPDDR4__DENALI_PI_104_READ_MASK 0x0703FFFFU

2003

#define LPDDR4__DENALI_PI_104_WRITE_MASK 0x0703FFFFU

2004

#define LPDDR4__DENALI_PI_104__PI_TDFI_CTRLUPD_MIN_MASK 0x0000FFFFU

2005

#define LPDDR4__DENALI_PI_104__PI_TDFI_CTRLUPD_MIN_SHIFT 0U

2006

#define LPDDR4__DENALI_PI_104__PI_TDFI_CTRLUPD_MIN_WIDTH 16U

2007

#define LPDDR4__PI_TDFI_CTRLUPD_MIN__REG DENALI_PI_104

2008

#define LPDDR4__PI_TDFI_CTRLUPD_MIN__FLD LPDDR4__DENALI_PI_104__PI_TDFI_CTRLUPD_MIN

2009

2010

#define LPDDR4__DENALI_PI_104__PI_UPDATE_ERROR_STATUS_MASK 0x00030000U

2011

#define LPDDR4__DENALI_PI_104__PI_UPDATE_ERROR_STATUS_SHIFT 16U

2012

#define LPDDR4__DENALI_PI_104__PI_UPDATE_ERROR_STATUS_WIDTH 2U

2013

#define LPDDR4__PI_UPDATE_ERROR_STATUS__REG DENALI_PI_104

2014

#define LPDDR4__PI_UPDATE_ERROR_STATUS__FLD LPDDR4__DENALI_PI_104__PI_UPDATE_ERROR_STATUS

2015

2016

#define LPDDR4__DENALI_PI_104__PI_TDFI_PARIN_LAT_MASK 0x07000000U

2017

#define LPDDR4__DENALI_PI_104__PI_TDFI_PARIN_LAT_SHIFT 24U

2018

#define LPDDR4__DENALI_PI_104__PI_TDFI_PARIN_LAT_WIDTH 3U

2019

#define LPDDR4__PI_TDFI_PARIN_LAT__REG DENALI_PI_104

2020

#define LPDDR4__PI_TDFI_PARIN_LAT__FLD LPDDR4__DENALI_PI_104__PI_TDFI_PARIN_LAT

2021

2022

#define LPDDR4__DENALI_PI_105_READ_MASK 0xFF010301U

2023

#define LPDDR4__DENALI_PI_105_WRITE_MASK 0xFF010301U

2024

#define LPDDR4__DENALI_PI_105__PI_BIST_GO_MASK 0x00000001U

2025

#define LPDDR4__DENALI_PI_105__PI_BIST_GO_SHIFT 0U

2026

#define LPDDR4__DENALI_PI_105__PI_BIST_GO_WIDTH 1U

2027

#define LPDDR4__DENALI_PI_105__PI_BIST_GO_WOCLR 0U

2028

#define LPDDR4__DENALI_PI_105__PI_BIST_GO_WOSET 0U

2029

#define LPDDR4__PI_BIST_GO__REG DENALI_PI_105

2030

#define LPDDR4__PI_BIST_GO__FLD LPDDR4__DENALI_PI_105__PI_BIST_GO

2031

2032

#define LPDDR4__DENALI_PI_105__PI_BIST_RESULT_MASK 0x00000300U

2033

#define LPDDR4__DENALI_PI_105__PI_BIST_RESULT_SHIFT 8U

2034

#define LPDDR4__DENALI_PI_105__PI_BIST_RESULT_WIDTH 2U

2035

#define LPDDR4__PI_BIST_RESULT__REG DENALI_PI_105

2036

#define LPDDR4__PI_BIST_RESULT__FLD LPDDR4__DENALI_PI_105__PI_BIST_RESULT

2037

2038

#define LPDDR4__DENALI_PI_105__PI_BIST_LFSR_PATTERN_DONE_MASK 0x00010000U

2039

#define LPDDR4__DENALI_PI_105__PI_BIST_LFSR_PATTERN_DONE_SHIFT 16U

2040

#define LPDDR4__DENALI_PI_105__PI_BIST_LFSR_PATTERN_DONE_WIDTH 1U

2041

#define LPDDR4__DENALI_PI_105__PI_BIST_LFSR_PATTERN_DONE_WOCLR 0U

2042

#define LPDDR4__DENALI_PI_105__PI_BIST_LFSR_PATTERN_DONE_WOSET 0U

2043

#define LPDDR4__PI_BIST_LFSR_PATTERN_DONE__REG DENALI_PI_105

2044

#define LPDDR4__PI_BIST_LFSR_PATTERN_DONE__FLD LPDDR4__DENALI_PI_105__PI_BIST_LFSR_PATTERN_DONE

2045

2046

#define LPDDR4__DENALI_PI_105__PI_ADDR_SPACE_MASK 0xFF000000U

2047

#define LPDDR4__DENALI_PI_105__PI_ADDR_SPACE_SHIFT 24U

2048

#define LPDDR4__DENALI_PI_105__PI_ADDR_SPACE_WIDTH 8U

2049

#define LPDDR4__PI_ADDR_SPACE__REG DENALI_PI_105

2050

#define LPDDR4__PI_ADDR_SPACE__FLD LPDDR4__DENALI_PI_105__PI_ADDR_SPACE

2051

2052

#define LPDDR4__DENALI_PI_106_READ_MASK 0x00000101U

2053

#define LPDDR4__DENALI_PI_106_WRITE_MASK 0x00000101U

2054

#define LPDDR4__DENALI_PI_106__PI_BIST_DATA_CHECK_MASK 0x00000001U

2055

#define LPDDR4__DENALI_PI_106__PI_BIST_DATA_CHECK_SHIFT 0U

2056

#define LPDDR4__DENALI_PI_106__PI_BIST_DATA_CHECK_WIDTH 1U

2057

#define LPDDR4__DENALI_PI_106__PI_BIST_DATA_CHECK_WOCLR 0U

2058

#define LPDDR4__DENALI_PI_106__PI_BIST_DATA_CHECK_WOSET 0U

2059

#define LPDDR4__PI_BIST_DATA_CHECK__REG DENALI_PI_106

2060

#define LPDDR4__PI_BIST_DATA_CHECK__FLD LPDDR4__DENALI_PI_106__PI_BIST_DATA_CHECK

2061

2062

#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_CHECK_MASK 0x00000100U

2063

#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_CHECK_SHIFT 8U

2064

#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_CHECK_WIDTH 1U

2065

#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_CHECK_WOCLR 0U

2066

#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_CHECK_WOSET 0U

2067

#define LPDDR4__PI_BIST_ADDR_CHECK__REG DENALI_PI_106

2068

#define LPDDR4__PI_BIST_ADDR_CHECK__FLD LPDDR4__DENALI_PI_106__PI_BIST_ADDR_CHECK

2069

2070

#define LPDDR4__DENALI_PI_107_READ_MASK 0xFFFFFFFFU

2071

#define LPDDR4__DENALI_PI_107_WRITE_MASK 0xFFFFFFFFU

2072

#define LPDDR4__DENALI_PI_107__PI_BIST_START_ADDRESS_0_MASK 0xFFFFFFFFU

2073

#define LPDDR4__DENALI_PI_107__PI_BIST_START_ADDRESS_0_SHIFT 0U

2074

#define LPDDR4__DENALI_PI_107__PI_BIST_START_ADDRESS_0_WIDTH 32U

2075

#define LPDDR4__PI_BIST_START_ADDRESS_0__REG DENALI_PI_107

2076

#define LPDDR4__PI_BIST_START_ADDRESS_0__FLD LPDDR4__DENALI_PI_107__PI_BIST_START_ADDRESS_0

2077

2078

#define LPDDR4__DENALI_PI_108_READ_MASK 0x0000FF07U

2079

#define LPDDR4__DENALI_PI_108_WRITE_MASK 0x0000FF07U

2080

#define LPDDR4__DENALI_PI_108__PI_BIST_START_ADDRESS_1_MASK 0x00000007U

2081

#define LPDDR4__DENALI_PI_108__PI_BIST_START_ADDRESS_1_SHIFT 0U

2082

#define LPDDR4__DENALI_PI_108__PI_BIST_START_ADDRESS_1_WIDTH 3U

2083

#define LPDDR4__PI_BIST_START_ADDRESS_1__REG DENALI_PI_108

2084

#define LPDDR4__PI_BIST_START_ADDRESS_1__FLD LPDDR4__DENALI_PI_108__PI_BIST_START_ADDRESS_1

2085

2086

#define LPDDR4__DENALI_PI_108__PI_MBIST_INIT_PATTERN_MASK 0x0000FF00U

2087

#define LPDDR4__DENALI_PI_108__PI_MBIST_INIT_PATTERN_SHIFT 8U

2088

#define LPDDR4__DENALI_PI_108__PI_MBIST_INIT_PATTERN_WIDTH 8U

2089

#define LPDDR4__PI_MBIST_INIT_PATTERN__REG DENALI_PI_108

2090

#define LPDDR4__PI_MBIST_INIT_PATTERN__FLD LPDDR4__DENALI_PI_108__PI_MBIST_INIT_PATTERN

2091

2092

#define LPDDR4__DENALI_PI_109_READ_MASK 0xFFFFFFFFU

2093

#define LPDDR4__DENALI_PI_109_WRITE_MASK 0xFFFFFFFFU

2094

#define LPDDR4__DENALI_PI_109__PI_BIST_DATA_MASK_0_MASK 0xFFFFFFFFU

2095

#define LPDDR4__DENALI_PI_109__PI_BIST_DATA_MASK_0_SHIFT 0U

2096

#define LPDDR4__DENALI_PI_109__PI_BIST_DATA_MASK_0_WIDTH 32U

2097

#define LPDDR4__PI_BIST_DATA_MASK_0__REG DENALI_PI_109

2098

#define LPDDR4__PI_BIST_DATA_MASK_0__FLD LPDDR4__DENALI_PI_109__PI_BIST_DATA_MASK_0

2099

2100

#define LPDDR4__DENALI_PI_110_READ_MASK 0xFFFFFFFFU

2101

#define LPDDR4__DENALI_PI_110_WRITE_MASK 0xFFFFFFFFU

2102

#define LPDDR4__DENALI_PI_110__PI_BIST_DATA_MASK_1_MASK 0xFFFFFFFFU

2103

#define LPDDR4__DENALI_PI_110__PI_BIST_DATA_MASK_1_SHIFT 0U

2104

#define LPDDR4__DENALI_PI_110__PI_BIST_DATA_MASK_1_WIDTH 32U

2105

#define LPDDR4__PI_BIST_DATA_MASK_1__REG DENALI_PI_110

2106

#define LPDDR4__PI_BIST_DATA_MASK_1__FLD LPDDR4__DENALI_PI_110__PI_BIST_DATA_MASK_1

2107

2108

#define LPDDR4__DENALI_PI_111_READ_MASK 0x0FFF0FFFU

2109

#define LPDDR4__DENALI_PI_111_WRITE_MASK 0x0FFF0FFFU

2110

#define LPDDR4__DENALI_PI_111__PI_BIST_ERR_COUNT_MASK 0x00000FFFU

2111

#define LPDDR4__DENALI_PI_111__PI_BIST_ERR_COUNT_SHIFT 0U

2112

#define LPDDR4__DENALI_PI_111__PI_BIST_ERR_COUNT_WIDTH 12U

2113

#define LPDDR4__PI_BIST_ERR_COUNT__REG DENALI_PI_111

2114

#define LPDDR4__PI_BIST_ERR_COUNT__FLD LPDDR4__DENALI_PI_111__PI_BIST_ERR_COUNT

2115

2116

#define LPDDR4__DENALI_PI_111__PI_BIST_ERR_STOP_MASK 0x0FFF0000U

2117

#define LPDDR4__DENALI_PI_111__PI_BIST_ERR_STOP_SHIFT 16U

2118

#define LPDDR4__DENALI_PI_111__PI_BIST_ERR_STOP_WIDTH 12U

2119

#define LPDDR4__PI_BIST_ERR_STOP__REG DENALI_PI_111

2120

#define LPDDR4__PI_BIST_ERR_STOP__FLD LPDDR4__DENALI_PI_111__PI_BIST_ERR_STOP

2121

2122

#define LPDDR4__DENALI_PI_112_READ_MASK 0xFFFFFFFFU

2123

#define LPDDR4__DENALI_PI_112_WRITE_MASK 0xFFFFFFFFU

2124

#define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_0_0_MASK 0xFFFFFFFFU

2125

#define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_0_0_SHIFT 0U

2126

#define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_0_0_WIDTH 32U

2127

#define LPDDR4__PI_BIST_ADDR_MASK_0_0__REG DENALI_PI_112

2128

#define LPDDR4__PI_BIST_ADDR_MASK_0_0__FLD LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_0_0

2129

2130

#define LPDDR4__DENALI_PI_113_READ_MASK 0x0000000FU

2131

#define LPDDR4__DENALI_PI_113_WRITE_MASK 0x0000000FU

2132

#define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_0_1_MASK 0x0000000FU

2133

#define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_0_1_SHIFT 0U

2134

#define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_0_1_WIDTH 4U

2135

#define LPDDR4__PI_BIST_ADDR_MASK_0_1__REG DENALI_PI_113

2136

#define LPDDR4__PI_BIST_ADDR_MASK_0_1__FLD LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_0_1

2137

2138

#define LPDDR4__DENALI_PI_114_READ_MASK 0xFFFFFFFFU

2139

#define LPDDR4__DENALI_PI_114_WRITE_MASK 0xFFFFFFFFU

2140

#define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_1_0_MASK 0xFFFFFFFFU

2141

#define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_1_0_SHIFT 0U

2142

#define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_1_0_WIDTH 32U

2143

#define LPDDR4__PI_BIST_ADDR_MASK_1_0__REG DENALI_PI_114

2144

#define LPDDR4__PI_BIST_ADDR_MASK_1_0__FLD LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_1_0

2145

2146

#define LPDDR4__DENALI_PI_115_READ_MASK 0x0000000FU

2147

#define LPDDR4__DENALI_PI_115_WRITE_MASK 0x0000000FU

2148

#define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_1_1_MASK 0x0000000FU

2149

#define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_1_1_SHIFT 0U

2150

#define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_1_1_WIDTH 4U

2151

#define LPDDR4__PI_BIST_ADDR_MASK_1_1__REG DENALI_PI_115

2152

#define LPDDR4__PI_BIST_ADDR_MASK_1_1__FLD LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_1_1

2153

2154

#define LPDDR4__DENALI_PI_116_READ_MASK 0xFFFFFFFFU

2155

#define LPDDR4__DENALI_PI_116_WRITE_MASK 0xFFFFFFFFU

2156

#define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_2_0_MASK 0xFFFFFFFFU

2157

#define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_2_0_SHIFT 0U

2158

#define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_2_0_WIDTH 32U

2159

#define LPDDR4__PI_BIST_ADDR_MASK_2_0__REG DENALI_PI_116

2160

#define LPDDR4__PI_BIST_ADDR_MASK_2_0__FLD LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_2_0

2161

2162

#define LPDDR4__DENALI_PI_117_READ_MASK 0x0000000FU

2163

#define LPDDR4__DENALI_PI_117_WRITE_MASK 0x0000000FU

2164

#define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_2_1_MASK 0x0000000FU

2165

#define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_2_1_SHIFT 0U

2166

#define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_2_1_WIDTH 4U

2167

#define LPDDR4__PI_BIST_ADDR_MASK_2_1__REG DENALI_PI_117

2168

#define LPDDR4__PI_BIST_ADDR_MASK_2_1__FLD LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_2_1

2169

2170

#define LPDDR4__DENALI_PI_118_READ_MASK 0xFFFFFFFFU

2171

#define LPDDR4__DENALI_PI_118_WRITE_MASK 0xFFFFFFFFU

2172

#define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_3_0_MASK 0xFFFFFFFFU

2173

#define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_3_0_SHIFT 0U

2174

#define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_3_0_WIDTH 32U

2175

#define LPDDR4__PI_BIST_ADDR_MASK_3_0__REG DENALI_PI_118

2176

#define LPDDR4__PI_BIST_ADDR_MASK_3_0__FLD LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_3_0

2177

2178

#define LPDDR4__DENALI_PI_119_READ_MASK 0x0000000FU

2179

#define LPDDR4__DENALI_PI_119_WRITE_MASK 0x0000000FU

2180

#define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_3_1_MASK 0x0000000FU

2181

#define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_3_1_SHIFT 0U

2182

#define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_3_1_WIDTH 4U

2183

#define LPDDR4__PI_BIST_ADDR_MASK_3_1__REG DENALI_PI_119

2184

#define LPDDR4__PI_BIST_ADDR_MASK_3_1__FLD LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_3_1

2185

2186

#define LPDDR4__DENALI_PI_120_READ_MASK 0xFFFFFFFFU

2187

#define LPDDR4__DENALI_PI_120_WRITE_MASK 0xFFFFFFFFU

2188

#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_4_0_MASK 0xFFFFFFFFU

2189

#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_4_0_SHIFT 0U

2190

#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_4_0_WIDTH 32U

2191

#define LPDDR4__PI_BIST_ADDR_MASK_4_0__REG DENALI_PI_120

2192

#define LPDDR4__PI_BIST_ADDR_MASK_4_0__FLD LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_4_0

2193

2194

#define LPDDR4__DENALI_PI_121_READ_MASK 0x0000000FU

2195

#define LPDDR4__DENALI_PI_121_WRITE_MASK 0x0000000FU

2196

#define LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MASK_4_1_MASK 0x0000000FU

2197

#define LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MASK_4_1_SHIFT 0U

2198

#define LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MASK_4_1_WIDTH 4U

2199

#define LPDDR4__PI_BIST_ADDR_MASK_4_1__REG DENALI_PI_121

2200

#define LPDDR4__PI_BIST_ADDR_MASK_4_1__FLD LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MASK_4_1

2201

2202

#define LPDDR4__DENALI_PI_122_READ_MASK 0xFFFFFFFFU

2203

#define LPDDR4__DENALI_PI_122_WRITE_MASK 0xFFFFFFFFU

2204

#define LPDDR4__DENALI_PI_122__PI_BIST_ADDR_MASK_5_0_MASK 0xFFFFFFFFU

2205

#define LPDDR4__DENALI_PI_122__PI_BIST_ADDR_MASK_5_0_SHIFT 0U

2206

#define LPDDR4__DENALI_PI_122__PI_BIST_ADDR_MASK_5_0_WIDTH 32U

2207

#define LPDDR4__PI_BIST_ADDR_MASK_5_0__REG DENALI_PI_122

2208

#define LPDDR4__PI_BIST_ADDR_MASK_5_0__FLD LPDDR4__DENALI_PI_122__PI_BIST_ADDR_MASK_5_0

2209

2210

#define LPDDR4__DENALI_PI_123_READ_MASK 0x0000000FU

2211

#define LPDDR4__DENALI_PI_123_WRITE_MASK 0x0000000FU

2212

#define LPDDR4__DENALI_PI_123__PI_BIST_ADDR_MASK_5_1_MASK 0x0000000FU

2213

#define LPDDR4__DENALI_PI_123__PI_BIST_ADDR_MASK_5_1_SHIFT 0U

2214

#define LPDDR4__DENALI_PI_123__PI_BIST_ADDR_MASK_5_1_WIDTH 4U

2215

#define LPDDR4__PI_BIST_ADDR_MASK_5_1__REG DENALI_PI_123

2216

#define LPDDR4__PI_BIST_ADDR_MASK_5_1__FLD LPDDR4__DENALI_PI_123__PI_BIST_ADDR_MASK_5_1

2217

2218

#define LPDDR4__DENALI_PI_124_READ_MASK 0xFFFFFFFFU

2219

#define LPDDR4__DENALI_PI_124_WRITE_MASK 0xFFFFFFFFU

2220

#define LPDDR4__DENALI_PI_124__PI_BIST_ADDR_MASK_6_0_MASK 0xFFFFFFFFU

2221

#define LPDDR4__DENALI_PI_124__PI_BIST_ADDR_MASK_6_0_SHIFT 0U

2222

#define LPDDR4__DENALI_PI_124__PI_BIST_ADDR_MASK_6_0_WIDTH 32U

2223

#define LPDDR4__PI_BIST_ADDR_MASK_6_0__REG DENALI_PI_124

2224

#define LPDDR4__PI_BIST_ADDR_MASK_6_0__FLD LPDDR4__DENALI_PI_124__PI_BIST_ADDR_MASK_6_0

2225

2226

#define LPDDR4__DENALI_PI_125_READ_MASK 0x0000000FU

2227

#define LPDDR4__DENALI_PI_125_WRITE_MASK 0x0000000FU

2228

#define LPDDR4__DENALI_PI_125__PI_BIST_ADDR_MASK_6_1_MASK 0x0000000FU

2229

#define LPDDR4__DENALI_PI_125__PI_BIST_ADDR_MASK_6_1_SHIFT 0U

2230

#define LPDDR4__DENALI_PI_125__PI_BIST_ADDR_MASK_6_1_WIDTH 4U

2231

#define LPDDR4__PI_BIST_ADDR_MASK_6_1__REG DENALI_PI_125

2232

#define LPDDR4__PI_BIST_ADDR_MASK_6_1__FLD LPDDR4__DENALI_PI_125__PI_BIST_ADDR_MASK_6_1

2233

2234

#define LPDDR4__DENALI_PI_126_READ_MASK 0xFFFFFFFFU

2235

#define LPDDR4__DENALI_PI_126_WRITE_MASK 0xFFFFFFFFU

2236

#define LPDDR4__DENALI_PI_126__PI_BIST_ADDR_MASK_7_0_MASK 0xFFFFFFFFU

2237

#define LPDDR4__DENALI_PI_126__PI_BIST_ADDR_MASK_7_0_SHIFT 0U

2238

#define LPDDR4__DENALI_PI_126__PI_BIST_ADDR_MASK_7_0_WIDTH 32U

2239

#define LPDDR4__PI_BIST_ADDR_MASK_7_0__REG DENALI_PI_126

2240

#define LPDDR4__PI_BIST_ADDR_MASK_7_0__FLD LPDDR4__DENALI_PI_126__PI_BIST_ADDR_MASK_7_0

2241

2242

#define LPDDR4__DENALI_PI_127_READ_MASK 0x0000000FU

2243

#define LPDDR4__DENALI_PI_127_WRITE_MASK 0x0000000FU

2244

#define LPDDR4__DENALI_PI_127__PI_BIST_ADDR_MASK_7_1_MASK 0x0000000FU

2245

#define LPDDR4__DENALI_PI_127__PI_BIST_ADDR_MASK_7_1_SHIFT 0U

2246

#define LPDDR4__DENALI_PI_127__PI_BIST_ADDR_MASK_7_1_WIDTH 4U

2247

#define LPDDR4__PI_BIST_ADDR_MASK_7_1__REG DENALI_PI_127

2248

#define LPDDR4__PI_BIST_ADDR_MASK_7_1__FLD LPDDR4__DENALI_PI_127__PI_BIST_ADDR_MASK_7_1

2249

2250

#define LPDDR4__DENALI_PI_128_READ_MASK 0xFFFFFFFFU

2251

#define LPDDR4__DENALI_PI_128_WRITE_MASK 0xFFFFFFFFU

2252

#define LPDDR4__DENALI_PI_128__PI_BIST_ADDR_MASK_8_0_MASK 0xFFFFFFFFU

2253

#define LPDDR4__DENALI_PI_128__PI_BIST_ADDR_MASK_8_0_SHIFT 0U

2254

#define LPDDR4__DENALI_PI_128__PI_BIST_ADDR_MASK_8_0_WIDTH 32U

2255

#define LPDDR4__PI_BIST_ADDR_MASK_8_0__REG DENALI_PI_128

2256

#define LPDDR4__PI_BIST_ADDR_MASK_8_0__FLD LPDDR4__DENALI_PI_128__PI_BIST_ADDR_MASK_8_0

2257

2258

#define LPDDR4__DENALI_PI_129_READ_MASK 0x0000000FU

2259

#define LPDDR4__DENALI_PI_129_WRITE_MASK 0x0000000FU

2260

#define LPDDR4__DENALI_PI_129__PI_BIST_ADDR_MASK_8_1_MASK 0x0000000FU

2261

#define LPDDR4__DENALI_PI_129__PI_BIST_ADDR_MASK_8_1_SHIFT 0U

2262

#define LPDDR4__DENALI_PI_129__PI_BIST_ADDR_MASK_8_1_WIDTH 4U

2263

#define LPDDR4__PI_BIST_ADDR_MASK_8_1__REG DENALI_PI_129

2264

#define LPDDR4__PI_BIST_ADDR_MASK_8_1__FLD LPDDR4__DENALI_PI_129__PI_BIST_ADDR_MASK_8_1

2265

2266

#define LPDDR4__DENALI_PI_130_READ_MASK 0xFFFFFFFFU

2267

#define LPDDR4__DENALI_PI_130_WRITE_MASK 0xFFFFFFFFU

2268

#define LPDDR4__DENALI_PI_130__PI_BIST_ADDR_MASK_9_0_MASK 0xFFFFFFFFU

2269

#define LPDDR4__DENALI_PI_130__PI_BIST_ADDR_MASK_9_0_SHIFT 0U

2270

#define LPDDR4__DENALI_PI_130__PI_BIST_ADDR_MASK_9_0_WIDTH 32U

2271

#define LPDDR4__PI_BIST_ADDR_MASK_9_0__REG DENALI_PI_130

2272

#define LPDDR4__PI_BIST_ADDR_MASK_9_0__FLD LPDDR4__DENALI_PI_130__PI_BIST_ADDR_MASK_9_0

2273

2274

#define LPDDR4__DENALI_PI_131_READ_MASK 0x0303070FU

2275

#define LPDDR4__DENALI_PI_131_WRITE_MASK 0x0303070FU

2276

#define LPDDR4__DENALI_PI_131__PI_BIST_ADDR_MASK_9_1_MASK 0x0000000FU

2277

#define LPDDR4__DENALI_PI_131__PI_BIST_ADDR_MASK_9_1_SHIFT 0U

2278

#define LPDDR4__DENALI_PI_131__PI_BIST_ADDR_MASK_9_1_WIDTH 4U

2279

#define LPDDR4__PI_BIST_ADDR_MASK_9_1__REG DENALI_PI_131

2280

#define LPDDR4__PI_BIST_ADDR_MASK_9_1__FLD LPDDR4__DENALI_PI_131__PI_BIST_ADDR_MASK_9_1

2281

2282

#define LPDDR4__DENALI_PI_131__PI_BIST_MODE_MASK 0x00000700U

2283

#define LPDDR4__DENALI_PI_131__PI_BIST_MODE_SHIFT 8U

2284

#define LPDDR4__DENALI_PI_131__PI_BIST_MODE_WIDTH 3U

2285

#define LPDDR4__PI_BIST_MODE__REG DENALI_PI_131

2286

#define LPDDR4__PI_BIST_MODE__FLD LPDDR4__DENALI_PI_131__PI_BIST_MODE

2287

2288

#define LPDDR4__DENALI_PI_131__PI_BIST_ADDR_MODE_MASK 0x00030000U

2289

#define LPDDR4__DENALI_PI_131__PI_BIST_ADDR_MODE_SHIFT 16U

2290

#define LPDDR4__DENALI_PI_131__PI_BIST_ADDR_MODE_WIDTH 2U

2291

#define LPDDR4__PI_BIST_ADDR_MODE__REG DENALI_PI_131

2292

#define LPDDR4__PI_BIST_ADDR_MODE__FLD LPDDR4__DENALI_PI_131__PI_BIST_ADDR_MODE

2293

2294

#define LPDDR4__DENALI_PI_131__PI_BIST_PAT_MODE_MASK 0x03000000U

2295

#define LPDDR4__DENALI_PI_131__PI_BIST_PAT_MODE_SHIFT 24U

2296

#define LPDDR4__DENALI_PI_131__PI_BIST_PAT_MODE_WIDTH 2U

2297

#define LPDDR4__PI_BIST_PAT_MODE__REG DENALI_PI_131

2298

#define LPDDR4__PI_BIST_PAT_MODE__FLD LPDDR4__DENALI_PI_131__PI_BIST_PAT_MODE

2299

2300

#define LPDDR4__DENALI_PI_132_READ_MASK 0xFFFFFFFFU

2301

#define LPDDR4__DENALI_PI_132_WRITE_MASK 0xFFFFFFFFU

2302

#define LPDDR4__DENALI_PI_132__PI_BIST_USER_PAT_0_MASK 0xFFFFFFFFU

2303

#define LPDDR4__DENALI_PI_132__PI_BIST_USER_PAT_0_SHIFT 0U

2304

#define LPDDR4__DENALI_PI_132__PI_BIST_USER_PAT_0_WIDTH 32U

2305

#define LPDDR4__PI_BIST_USER_PAT_0__REG DENALI_PI_132

2306

#define LPDDR4__PI_BIST_USER_PAT_0__FLD LPDDR4__DENALI_PI_132__PI_BIST_USER_PAT_0

2307

2308

#define LPDDR4__DENALI_PI_133_READ_MASK 0xFFFFFFFFU

2309

#define LPDDR4__DENALI_PI_133_WRITE_MASK 0xFFFFFFFFU

2310

#define LPDDR4__DENALI_PI_133__PI_BIST_USER_PAT_1_MASK 0xFFFFFFFFU

2311

#define LPDDR4__DENALI_PI_133__PI_BIST_USER_PAT_1_SHIFT 0U

2312

#define LPDDR4__DENALI_PI_133__PI_BIST_USER_PAT_1_WIDTH 32U

2313

#define LPDDR4__PI_BIST_USER_PAT_1__REG DENALI_PI_133

2314

#define LPDDR4__PI_BIST_USER_PAT_1__FLD LPDDR4__DENALI_PI_133__PI_BIST_USER_PAT_1

2315

2316

#define LPDDR4__DENALI_PI_134_READ_MASK 0xFFFFFFFFU

2317

#define LPDDR4__DENALI_PI_134_WRITE_MASK 0xFFFFFFFFU

2318

#define LPDDR4__DENALI_PI_134__PI_BIST_USER_PAT_2_MASK 0xFFFFFFFFU

2319

#define LPDDR4__DENALI_PI_134__PI_BIST_USER_PAT_2_SHIFT 0U

2320

#define LPDDR4__DENALI_PI_134__PI_BIST_USER_PAT_2_WIDTH 32U

2321

#define LPDDR4__PI_BIST_USER_PAT_2__REG DENALI_PI_134

2322

#define LPDDR4__PI_BIST_USER_PAT_2__FLD LPDDR4__DENALI_PI_134__PI_BIST_USER_PAT_2

2323

2324

#define LPDDR4__DENALI_PI_135_READ_MASK 0xFFFFFFFFU

2325

#define LPDDR4__DENALI_PI_135_WRITE_MASK 0xFFFFFFFFU

2326

#define LPDDR4__DENALI_PI_135__PI_BIST_USER_PAT_3_MASK 0xFFFFFFFFU

2327

#define LPDDR4__DENALI_PI_135__PI_BIST_USER_PAT_3_SHIFT 0U

2328

#define LPDDR4__DENALI_PI_135__PI_BIST_USER_PAT_3_WIDTH 32U

2329

#define LPDDR4__PI_BIST_USER_PAT_3__REG DENALI_PI_135

2330

#define LPDDR4__PI_BIST_USER_PAT_3__FLD LPDDR4__DENALI_PI_135__PI_BIST_USER_PAT_3

2331

2332

#define LPDDR4__DENALI_PI_136_READ_MASK 0x0000007FU

2333

#define LPDDR4__DENALI_PI_136_WRITE_MASK 0x0000007FU

2334

#define LPDDR4__DENALI_PI_136__PI_BIST_PAT_NUM_MASK 0x0000007FU

2335

#define LPDDR4__DENALI_PI_136__PI_BIST_PAT_NUM_SHIFT 0U

2336

#define LPDDR4__DENALI_PI_136__PI_BIST_PAT_NUM_WIDTH 7U

2337

#define LPDDR4__PI_BIST_PAT_NUM__REG DENALI_PI_136

2338

#define LPDDR4__PI_BIST_PAT_NUM__FLD LPDDR4__DENALI_PI_136__PI_BIST_PAT_NUM

2339

2340

#define LPDDR4__DENALI_PI_137_READ_MASK 0x3FFFFFFFU

2341

#define LPDDR4__DENALI_PI_137_WRITE_MASK 0x3FFFFFFFU

2342

#define LPDDR4__DENALI_PI_137__PI_BIST_STAGE_0_MASK 0x3FFFFFFFU

2343

#define LPDDR4__DENALI_PI_137__PI_BIST_STAGE_0_SHIFT 0U

2344

#define LPDDR4__DENALI_PI_137__PI_BIST_STAGE_0_WIDTH 30U

2345

#define LPDDR4__PI_BIST_STAGE_0__REG DENALI_PI_137

2346

#define LPDDR4__PI_BIST_STAGE_0__FLD LPDDR4__DENALI_PI_137__PI_BIST_STAGE_0

2347

2348

#define LPDDR4__DENALI_PI_138_READ_MASK 0x3FFFFFFFU

2349

#define LPDDR4__DENALI_PI_138_WRITE_MASK 0x3FFFFFFFU

2350

#define LPDDR4__DENALI_PI_138__PI_BIST_STAGE_1_MASK 0x3FFFFFFFU

2351

#define LPDDR4__DENALI_PI_138__PI_BIST_STAGE_1_SHIFT 0U

2352

#define LPDDR4__DENALI_PI_138__PI_BIST_STAGE_1_WIDTH 30U

2353

#define LPDDR4__PI_BIST_STAGE_1__REG DENALI_PI_138

2354

#define LPDDR4__PI_BIST_STAGE_1__FLD LPDDR4__DENALI_PI_138__PI_BIST_STAGE_1

2355

2356

#define LPDDR4__DENALI_PI_139_READ_MASK 0x3FFFFFFFU

2357

#define LPDDR4__DENALI_PI_139_WRITE_MASK 0x3FFFFFFFU

2358

#define LPDDR4__DENALI_PI_139__PI_BIST_STAGE_2_MASK 0x3FFFFFFFU

2359

#define LPDDR4__DENALI_PI_139__PI_BIST_STAGE_2_SHIFT 0U

2360

#define LPDDR4__DENALI_PI_139__PI_BIST_STAGE_2_WIDTH 30U

2361

#define LPDDR4__PI_BIST_STAGE_2__REG DENALI_PI_139

2362

#define LPDDR4__PI_BIST_STAGE_2__FLD LPDDR4__DENALI_PI_139__PI_BIST_STAGE_2

2363

2364

#define LPDDR4__DENALI_PI_140_READ_MASK 0x3FFFFFFFU

2365

#define LPDDR4__DENALI_PI_140_WRITE_MASK 0x3FFFFFFFU

2366

#define LPDDR4__DENALI_PI_140__PI_BIST_STAGE_3_MASK 0x3FFFFFFFU

2367

#define LPDDR4__DENALI_PI_140__PI_BIST_STAGE_3_SHIFT 0U

2368

#define LPDDR4__DENALI_PI_140__PI_BIST_STAGE_3_WIDTH 30U

2369

#define LPDDR4__PI_BIST_STAGE_3__REG DENALI_PI_140

2370

#define LPDDR4__PI_BIST_STAGE_3__FLD LPDDR4__DENALI_PI_140__PI_BIST_STAGE_3

2371

2372

#define LPDDR4__DENALI_PI_141_READ_MASK 0x3FFFFFFFU

2373

#define LPDDR4__DENALI_PI_141_WRITE_MASK 0x3FFFFFFFU

2374

#define LPDDR4__DENALI_PI_141__PI_BIST_STAGE_4_MASK 0x3FFFFFFFU

2375

#define LPDDR4__DENALI_PI_141__PI_BIST_STAGE_4_SHIFT 0U

2376

#define LPDDR4__DENALI_PI_141__PI_BIST_STAGE_4_WIDTH 30U

2377

#define LPDDR4__PI_BIST_STAGE_4__REG DENALI_PI_141

2378

#define LPDDR4__PI_BIST_STAGE_4__FLD LPDDR4__DENALI_PI_141__PI_BIST_STAGE_4

2379

2380

#define LPDDR4__DENALI_PI_142_READ_MASK 0x3FFFFFFFU

2381

#define LPDDR4__DENALI_PI_142_WRITE_MASK 0x3FFFFFFFU

2382

#define LPDDR4__DENALI_PI_142__PI_BIST_STAGE_5_MASK 0x3FFFFFFFU

2383

#define LPDDR4__DENALI_PI_142__PI_BIST_STAGE_5_SHIFT 0U

2384

#define LPDDR4__DENALI_PI_142__PI_BIST_STAGE_5_WIDTH 30U

2385

#define LPDDR4__PI_BIST_STAGE_5__REG DENALI_PI_142

2386

#define LPDDR4__PI_BIST_STAGE_5__FLD LPDDR4__DENALI_PI_142__PI_BIST_STAGE_5

2387

2388

#define LPDDR4__DENALI_PI_143_READ_MASK 0x3FFFFFFFU

2389

#define LPDDR4__DENALI_PI_143_WRITE_MASK 0x3FFFFFFFU

2390

#define LPDDR4__DENALI_PI_143__PI_BIST_STAGE_6_MASK 0x3FFFFFFFU

2391

#define LPDDR4__DENALI_PI_143__PI_BIST_STAGE_6_SHIFT 0U

2392

#define LPDDR4__DENALI_PI_143__PI_BIST_STAGE_6_WIDTH 30U

2393

#define LPDDR4__PI_BIST_STAGE_6__REG DENALI_PI_143

2394

#define LPDDR4__PI_BIST_STAGE_6__FLD LPDDR4__DENALI_PI_143__PI_BIST_STAGE_6

2395

2396

#define LPDDR4__DENALI_PI_144_READ_MASK 0x3FFFFFFFU

2397

#define LPDDR4__DENALI_PI_144_WRITE_MASK 0x3FFFFFFFU

2398

#define LPDDR4__DENALI_PI_144__PI_BIST_STAGE_7_MASK 0x3FFFFFFFU

2399

#define LPDDR4__DENALI_PI_144__PI_BIST_STAGE_7_SHIFT 0U

2400

#define LPDDR4__DENALI_PI_144__PI_BIST_STAGE_7_WIDTH 30U

2401

#define LPDDR4__PI_BIST_STAGE_7__REG DENALI_PI_144

2402

#define LPDDR4__PI_BIST_STAGE_7__FLD LPDDR4__DENALI_PI_144__PI_BIST_STAGE_7

2403

2404

#define LPDDR4__DENALI_PI_145_READ_MASK 0x0101010FU

2405

#define LPDDR4__DENALI_PI_145_WRITE_MASK 0x0101010FU

2406

#define LPDDR4__DENALI_PI_145__PI_COL_DIFF_MASK 0x0000000FU

2407

#define LPDDR4__DENALI_PI_145__PI_COL_DIFF_SHIFT 0U

2408

#define LPDDR4__DENALI_PI_145__PI_COL_DIFF_WIDTH 4U

2409

#define LPDDR4__PI_COL_DIFF__REG DENALI_PI_145

2410

#define LPDDR4__PI_COL_DIFF__FLD LPDDR4__DENALI_PI_145__PI_COL_DIFF

2411

2412

#define LPDDR4__DENALI_PI_145__PI_BG_ROTATE_EN_MASK 0x00000100U

2413

#define LPDDR4__DENALI_PI_145__PI_BG_ROTATE_EN_SHIFT 8U

2414

#define LPDDR4__DENALI_PI_145__PI_BG_ROTATE_EN_WIDTH 1U

2415

#define LPDDR4__DENALI_PI_145__PI_BG_ROTATE_EN_WOCLR 0U

2416

#define LPDDR4__DENALI_PI_145__PI_BG_ROTATE_EN_WOSET 0U

2417

#define LPDDR4__PI_BG_ROTATE_EN__REG DENALI_PI_145

2418

#define LPDDR4__PI_BG_ROTATE_EN__FLD LPDDR4__DENALI_PI_145__PI_BG_ROTATE_EN

2419

2420

#define LPDDR4__DENALI_PI_145__PI_CRC_CALC_MASK 0x00010000U

2421

#define LPDDR4__DENALI_PI_145__PI_CRC_CALC_SHIFT 16U

2422

#define LPDDR4__DENALI_PI_145__PI_CRC_CALC_WIDTH 1U

2423

#define LPDDR4__DENALI_PI_145__PI_CRC_CALC_WOCLR 0U

2424

#define LPDDR4__DENALI_PI_145__PI_CRC_CALC_WOSET 0U

2425

#define LPDDR4__PI_CRC_CALC__REG DENALI_PI_145

2426

#define LPDDR4__PI_CRC_CALC__FLD LPDDR4__DENALI_PI_145__PI_CRC_CALC

2427

2428

#define LPDDR4__DENALI_PI_145__PI_SELF_REFRESH_EN_MASK 0x01000000U

2429

#define LPDDR4__DENALI_PI_145__PI_SELF_REFRESH_EN_SHIFT 24U

2430

#define LPDDR4__DENALI_PI_145__PI_SELF_REFRESH_EN_WIDTH 1U

2431

#define LPDDR4__DENALI_PI_145__PI_SELF_REFRESH_EN_WOCLR 0U

2432

#define LPDDR4__DENALI_PI_145__PI_SELF_REFRESH_EN_WOSET 0U

2433

#define LPDDR4__PI_SELF_REFRESH_EN__REG DENALI_PI_145

2434

#define LPDDR4__PI_SELF_REFRESH_EN__FLD LPDDR4__DENALI_PI_145__PI_SELF_REFRESH_EN

2435

2436

#define LPDDR4__DENALI_PI_146_READ_MASK 0x00010101U

2437

#define LPDDR4__DENALI_PI_146_WRITE_MASK 0x00010101U

2438

#define LPDDR4__DENALI_PI_146__PI_MC_PWRUP_SREFRESH_EXIT_MASK 0x00000001U

2439

#define LPDDR4__DENALI_PI_146__PI_MC_PWRUP_SREFRESH_EXIT_SHIFT 0U

2440

#define LPDDR4__DENALI_PI_146__PI_MC_PWRUP_SREFRESH_EXIT_WIDTH 1U

2441

#define LPDDR4__DENALI_PI_146__PI_MC_PWRUP_SREFRESH_EXIT_WOCLR 0U

2442

#define LPDDR4__DENALI_PI_146__PI_MC_PWRUP_SREFRESH_EXIT_WOSET 0U

2443

#define LPDDR4__PI_MC_PWRUP_SREFRESH_EXIT__REG DENALI_PI_146

2444

#define LPDDR4__PI_MC_PWRUP_SREFRESH_EXIT__FLD LPDDR4__DENALI_PI_146__PI_MC_PWRUP_SREFRESH_EXIT

2445

2446

#define LPDDR4__DENALI_PI_146__PI_PWRUP_SREFRESH_EXIT_MASK 0x00000100U

2447

#define LPDDR4__DENALI_PI_146__PI_PWRUP_SREFRESH_EXIT_SHIFT 8U

2448

#define LPDDR4__DENALI_PI_146__PI_PWRUP_SREFRESH_EXIT_WIDTH 1U

2449

#define LPDDR4__DENALI_PI_146__PI_PWRUP_SREFRESH_EXIT_WOCLR 0U

2450

#define LPDDR4__DENALI_PI_146__PI_PWRUP_SREFRESH_EXIT_WOSET 0U

2451

#define LPDDR4__PI_PWRUP_SREFRESH_EXIT__REG DENALI_PI_146

2452

#define LPDDR4__PI_PWRUP_SREFRESH_EXIT__FLD LPDDR4__DENALI_PI_146__PI_PWRUP_SREFRESH_EXIT

2453

2454

#define LPDDR4__DENALI_PI_146__PI_SREFRESH_EXIT_NO_REFRESH_MASK 0x00010000U

2455

#define LPDDR4__DENALI_PI_146__PI_SREFRESH_EXIT_NO_REFRESH_SHIFT 16U

2456

#define LPDDR4__DENALI_PI_146__PI_SREFRESH_EXIT_NO_REFRESH_WIDTH 1U

2457

#define LPDDR4__DENALI_PI_146__PI_SREFRESH_EXIT_NO_REFRESH_WOCLR 0U

2458

#define LPDDR4__DENALI_PI_146__PI_SREFRESH_EXIT_NO_REFRESH_WOSET 0U

2459

#define LPDDR4__PI_SREFRESH_EXIT_NO_REFRESH__REG DENALI_PI_146

2460

#define LPDDR4__PI_SREFRESH_EXIT_NO_REFRESH__FLD LPDDR4__DENALI_PI_146__PI_SREFRESH_EXIT_NO_REFRESH

2461

2462

#define LPDDR4__DENALI_PI_146__PI_SREF_ENTRY_REQ_MASK 0x01000000U

2463

#define LPDDR4__DENALI_PI_146__PI_SREF_ENTRY_REQ_SHIFT 24U

2464

#define LPDDR4__DENALI_PI_146__PI_SREF_ENTRY_REQ_WIDTH 1U

2465

#define LPDDR4__DENALI_PI_146__PI_SREF_ENTRY_REQ_WOCLR 0U

2466

#define LPDDR4__DENALI_PI_146__PI_SREF_ENTRY_REQ_WOSET 0U

2467

#define LPDDR4__PI_SREF_ENTRY_REQ__REG DENALI_PI_146

2468

#define LPDDR4__PI_SREF_ENTRY_REQ__FLD LPDDR4__DENALI_PI_146__PI_SREF_ENTRY_REQ

2469

2470

#define LPDDR4__DENALI_PI_147_READ_MASK 0x01010101U

2471

#define LPDDR4__DENALI_PI_147_WRITE_MASK 0x01010101U

2472

#define LPDDR4__DENALI_PI_147__PI_NO_MRW_BT_INIT_MASK 0x00000001U

2473

#define LPDDR4__DENALI_PI_147__PI_NO_MRW_BT_INIT_SHIFT 0U

2474

#define LPDDR4__DENALI_PI_147__PI_NO_MRW_BT_INIT_WIDTH 1U

2475

#define LPDDR4__DENALI_PI_147__PI_NO_MRW_BT_INIT_WOCLR 0U

2476

#define LPDDR4__DENALI_PI_147__PI_NO_MRW_BT_INIT_WOSET 0U

2477

#define LPDDR4__PI_NO_MRW_BT_INIT__REG DENALI_PI_147

2478

#define LPDDR4__PI_NO_MRW_BT_INIT__FLD LPDDR4__DENALI_PI_147__PI_NO_MRW_BT_INIT

2479

2480

#define LPDDR4__DENALI_PI_147__PI_NO_MRW_INIT_MASK 0x00000100U

2481

#define LPDDR4__DENALI_PI_147__PI_NO_MRW_INIT_SHIFT 8U

2482

#define LPDDR4__DENALI_PI_147__PI_NO_MRW_INIT_WIDTH 1U

2483

#define LPDDR4__DENALI_PI_147__PI_NO_MRW_INIT_WOCLR 0U

2484

#define LPDDR4__DENALI_PI_147__PI_NO_MRW_INIT_WOSET 0U

2485

#define LPDDR4__PI_NO_MRW_INIT__REG DENALI_PI_147

2486

#define LPDDR4__PI_NO_MRW_INIT__FLD LPDDR4__DENALI_PI_147__PI_NO_MRW_INIT

2487

2488

#define LPDDR4__DENALI_PI_147__PI_NO_PHY_IND_TRAIN_INIT_MASK 0x00010000U

2489

#define LPDDR4__DENALI_PI_147__PI_NO_PHY_IND_TRAIN_INIT_SHIFT 16U

2490

#define LPDDR4__DENALI_PI_147__PI_NO_PHY_IND_TRAIN_INIT_WIDTH 1U

2491

#define LPDDR4__DENALI_PI_147__PI_NO_PHY_IND_TRAIN_INIT_WOCLR 0U

2492

#define LPDDR4__DENALI_PI_147__PI_NO_PHY_IND_TRAIN_INIT_WOSET 0U

2493

#define LPDDR4__PI_NO_PHY_IND_TRAIN_INIT__REG DENALI_PI_147

2494

#define LPDDR4__PI_NO_PHY_IND_TRAIN_INIT__FLD LPDDR4__DENALI_PI_147__PI_NO_PHY_IND_TRAIN_INIT

2495

2496

#define LPDDR4__DENALI_PI_147__PI_NO_AUTO_MRR_INIT_MASK 0x01000000U

2497

#define LPDDR4__DENALI_PI_147__PI_NO_AUTO_MRR_INIT_SHIFT 24U

2498

#define LPDDR4__DENALI_PI_147__PI_NO_AUTO_MRR_INIT_WIDTH 1U

2499

#define LPDDR4__DENALI_PI_147__PI_NO_AUTO_MRR_INIT_WOCLR 0U

2500

#define LPDDR4__DENALI_PI_147__PI_NO_AUTO_MRR_INIT_WOSET 0U

2501

#define LPDDR4__PI_NO_AUTO_MRR_INIT__REG DENALI_PI_147

2502

#define LPDDR4__PI_NO_AUTO_MRR_INIT__FLD LPDDR4__DENALI_PI_147__PI_NO_AUTO_MRR_INIT

2503

2504

#define LPDDR4__DENALI_PI_148_READ_MASK 0xFFFFFFFFU

2505

#define LPDDR4__DENALI_PI_148_WRITE_MASK 0xFFFFFFFFU

2506

#define LPDDR4__DENALI_PI_148__PI_TRST_PWRON_MASK 0xFFFFFFFFU

2507

#define LPDDR4__DENALI_PI_148__PI_TRST_PWRON_SHIFT 0U

2508

#define LPDDR4__DENALI_PI_148__PI_TRST_PWRON_WIDTH 32U

2509

#define LPDDR4__PI_TRST_PWRON__REG DENALI_PI_148

2510

#define LPDDR4__PI_TRST_PWRON__FLD LPDDR4__DENALI_PI_148__PI_TRST_PWRON

2511

2512

#define LPDDR4__DENALI_PI_149_READ_MASK 0xFFFFFFFFU

2513

#define LPDDR4__DENALI_PI_149_WRITE_MASK 0xFFFFFFFFU

2514

#define LPDDR4__DENALI_PI_149__PI_CKE_INACTIVE_MASK 0xFFFFFFFFU

2515

#define LPDDR4__DENALI_PI_149__PI_CKE_INACTIVE_SHIFT 0U

2516

#define LPDDR4__DENALI_PI_149__PI_CKE_INACTIVE_WIDTH 32U

2517

#define LPDDR4__PI_CKE_INACTIVE__REG DENALI_PI_149

2518

#define LPDDR4__PI_CKE_INACTIVE__FLD LPDDR4__DENALI_PI_149__PI_CKE_INACTIVE

2519

2520

#define LPDDR4__DENALI_PI_150_READ_MASK 0xFFFF0101U

2521

#define LPDDR4__DENALI_PI_150_WRITE_MASK 0xFFFF0101U

2522

#define LPDDR4__DENALI_PI_150__PI_DLL_RST_MASK 0x00000001U

2523

#define LPDDR4__DENALI_PI_150__PI_DLL_RST_SHIFT 0U

2524

#define LPDDR4__DENALI_PI_150__PI_DLL_RST_WIDTH 1U

2525

#define LPDDR4__DENALI_PI_150__PI_DLL_RST_WOCLR 0U

2526

#define LPDDR4__DENALI_PI_150__PI_DLL_RST_WOSET 0U

2527

#define LPDDR4__PI_DLL_RST__REG DENALI_PI_150

2528

#define LPDDR4__PI_DLL_RST__FLD LPDDR4__DENALI_PI_150__PI_DLL_RST

2529

2530

#define LPDDR4__DENALI_PI_150__PI_DRAM_INIT_EN_MASK 0x00000100U

2531

#define LPDDR4__DENALI_PI_150__PI_DRAM_INIT_EN_SHIFT 8U

2532

#define LPDDR4__DENALI_PI_150__PI_DRAM_INIT_EN_WIDTH 1U

2533

#define LPDDR4__DENALI_PI_150__PI_DRAM_INIT_EN_WOCLR 0U

2534

#define LPDDR4__DENALI_PI_150__PI_DRAM_INIT_EN_WOSET 0U

2535

#define LPDDR4__PI_DRAM_INIT_EN__REG DENALI_PI_150

2536

#define LPDDR4__PI_DRAM_INIT_EN__FLD LPDDR4__DENALI_PI_150__PI_DRAM_INIT_EN

2537

2538

#define LPDDR4__DENALI_PI_150__PI_DLL_RST_DELAY_MASK 0xFFFF0000U

2539

#define LPDDR4__DENALI_PI_150__PI_DLL_RST_DELAY_SHIFT 16U

2540

#define LPDDR4__DENALI_PI_150__PI_DLL_RST_DELAY_WIDTH 16U

2541

#define LPDDR4__PI_DLL_RST_DELAY__REG DENALI_PI_150

2542

#define LPDDR4__PI_DLL_RST_DELAY__FLD LPDDR4__DENALI_PI_150__PI_DLL_RST_DELAY

2543

2544

#define LPDDR4__DENALI_PI_151_READ_MASK 0x000000FFU

2545

#define LPDDR4__DENALI_PI_151_WRITE_MASK 0x000000FFU

2546

#define LPDDR4__DENALI_PI_151__PI_DLL_RST_ADJ_DLY_MASK 0x000000FFU

2547

#define LPDDR4__DENALI_PI_151__PI_DLL_RST_ADJ_DLY_SHIFT 0U

2548

#define LPDDR4__DENALI_PI_151__PI_DLL_RST_ADJ_DLY_WIDTH 8U

2549

#define LPDDR4__PI_DLL_RST_ADJ_DLY__REG DENALI_PI_151

2550

#define LPDDR4__PI_DLL_RST_ADJ_DLY__FLD LPDDR4__DENALI_PI_151__PI_DLL_RST_ADJ_DLY

2551

2552

#define LPDDR4__DENALI_PI_152_READ_MASK 0x03FFFFFFU

2553

#define LPDDR4__DENALI_PI_152_WRITE_MASK 0x03FFFFFFU

2554

#define LPDDR4__DENALI_PI_152__PI_WRITE_MODEREG_MASK 0x03FFFFFFU

2555

#define LPDDR4__DENALI_PI_152__PI_WRITE_MODEREG_SHIFT 0U

2556

#define LPDDR4__DENALI_PI_152__PI_WRITE_MODEREG_WIDTH 26U

2557

#define LPDDR4__PI_WRITE_MODEREG__REG DENALI_PI_152

2558

#define LPDDR4__PI_WRITE_MODEREG__FLD LPDDR4__DENALI_PI_152__PI_WRITE_MODEREG

2559

2560

#define LPDDR4__DENALI_PI_153_READ_MASK 0x000001FFU

2561

#define LPDDR4__DENALI_PI_153_WRITE_MASK 0x000001FFU

2562

#define LPDDR4__DENALI_PI_153__PI_MRW_STATUS_MASK 0x000000FFU

2563

#define LPDDR4__DENALI_PI_153__PI_MRW_STATUS_SHIFT 0U

2564

#define LPDDR4__DENALI_PI_153__PI_MRW_STATUS_WIDTH 8U

2565

#define LPDDR4__PI_MRW_STATUS__REG DENALI_PI_153

2566

#define LPDDR4__PI_MRW_STATUS__FLD LPDDR4__DENALI_PI_153__PI_MRW_STATUS

2567

2568

#define LPDDR4__DENALI_PI_153__PI_RESERVED27_MASK 0x00000100U

2569

#define LPDDR4__DENALI_PI_153__PI_RESERVED27_SHIFT 8U

2570

#define LPDDR4__DENALI_PI_153__PI_RESERVED27_WIDTH 1U

2571

#define LPDDR4__DENALI_PI_153__PI_RESERVED27_WOCLR 0U

2572

#define LPDDR4__DENALI_PI_153__PI_RESERVED27_WOSET 0U

2573

#define LPDDR4__PI_RESERVED27__REG DENALI_PI_153

2574

#define LPDDR4__PI_RESERVED27__FLD LPDDR4__DENALI_PI_153__PI_RESERVED27

2575

2576

#define LPDDR4__DENALI_PI_154_READ_MASK 0x0001FFFFU

2577

#define LPDDR4__DENALI_PI_154_WRITE_MASK 0x0001FFFFU

2578

#define LPDDR4__DENALI_PI_154__PI_READ_MODEREG_MASK 0x0001FFFFU

2579

#define LPDDR4__DENALI_PI_154__PI_READ_MODEREG_SHIFT 0U

2580

#define LPDDR4__DENALI_PI_154__PI_READ_MODEREG_WIDTH 17U

2581

#define LPDDR4__PI_READ_MODEREG__REG DENALI_PI_154

2582

#define LPDDR4__PI_READ_MODEREG__FLD LPDDR4__DENALI_PI_154__PI_READ_MODEREG

2583

2584

#define LPDDR4__DENALI_PI_155_READ_MASK 0x01FFFFFFU

2585

#define LPDDR4__DENALI_PI_155_WRITE_MASK 0x01FFFFFFU

2586

#define LPDDR4__DENALI_PI_155__PI_PERIPHERAL_MRR_DATA_0_MASK 0x00FFFFFFU

2587

#define LPDDR4__DENALI_PI_155__PI_PERIPHERAL_MRR_DATA_0_SHIFT 0U

2588

#define LPDDR4__DENALI_PI_155__PI_PERIPHERAL_MRR_DATA_0_WIDTH 24U

2589

#define LPDDR4__PI_PERIPHERAL_MRR_DATA_0__REG DENALI_PI_155

2590

#define LPDDR4__PI_PERIPHERAL_MRR_DATA_0__FLD LPDDR4__DENALI_PI_155__PI_PERIPHERAL_MRR_DATA_0

2591

2592

#define LPDDR4__DENALI_PI_155__PI_NO_ZQ_INIT_MASK 0x01000000U

2593

#define LPDDR4__DENALI_PI_155__PI_NO_ZQ_INIT_SHIFT 24U

2594

#define LPDDR4__DENALI_PI_155__PI_NO_ZQ_INIT_WIDTH 1U

2595

#define LPDDR4__DENALI_PI_155__PI_NO_ZQ_INIT_WOCLR 0U

2596

#define LPDDR4__DENALI_PI_155__PI_NO_ZQ_INIT_WOSET 0U

2597

#define LPDDR4__PI_NO_ZQ_INIT__REG DENALI_PI_155

2598

#define LPDDR4__PI_NO_ZQ_INIT__FLD LPDDR4__DENALI_PI_155__PI_NO_ZQ_INIT

2599

2600

#define LPDDR4__DENALI_PI_156_READ_MASK 0x0101000FU

2601

#define LPDDR4__DENALI_PI_156_WRITE_MASK 0x0101000FU

2602

#define LPDDR4__DENALI_PI_156__PI_RESERVED28_MASK 0x0000000FU

2603

#define LPDDR4__DENALI_PI_156__PI_RESERVED28_SHIFT 0U

2604

#define LPDDR4__DENALI_PI_156__PI_RESERVED28_WIDTH 4U

2605

#define LPDDR4__PI_RESERVED28__REG DENALI_PI_156

2606

#define LPDDR4__PI_RESERVED28__FLD LPDDR4__DENALI_PI_156__PI_RESERVED28

2607

2608

#define LPDDR4__DENALI_PI_156__PI_RESERVED29_MASK 0x00000F00U

2609

#define LPDDR4__DENALI_PI_156__PI_RESERVED29_SHIFT 8U

2610

#define LPDDR4__DENALI_PI_156__PI_RESERVED29_WIDTH 4U

2611

#define LPDDR4__PI_RESERVED29__REG DENALI_PI_156

2612

#define LPDDR4__PI_RESERVED29__FLD LPDDR4__DENALI_PI_156__PI_RESERVED29

2613

2614

#define LPDDR4__DENALI_PI_156__PI_ZQ_REQ_PENDING_MASK 0x00010000U

2615

#define LPDDR4__DENALI_PI_156__PI_ZQ_REQ_PENDING_SHIFT 16U

2616

#define LPDDR4__DENALI_PI_156__PI_ZQ_REQ_PENDING_WIDTH 1U

2617

#define LPDDR4__DENALI_PI_156__PI_ZQ_REQ_PENDING_WOCLR 0U

2618

#define LPDDR4__DENALI_PI_156__PI_ZQ_REQ_PENDING_WOSET 0U

2619

#define LPDDR4__PI_ZQ_REQ_PENDING__REG DENALI_PI_156

2620

#define LPDDR4__PI_ZQ_REQ_PENDING__FLD LPDDR4__DENALI_PI_156__PI_ZQ_REQ_PENDING

2621

2622

#define LPDDR4__DENALI_PI_156__PI_RESERVED30_MASK 0x01000000U

2623

#define LPDDR4__DENALI_PI_156__PI_RESERVED30_SHIFT 24U

2624

#define LPDDR4__DENALI_PI_156__PI_RESERVED30_WIDTH 1U

2625

#define LPDDR4__DENALI_PI_156__PI_RESERVED30_WOCLR 0U

2626

#define LPDDR4__DENALI_PI_156__PI_RESERVED30_WOSET 0U

2627

#define LPDDR4__PI_RESERVED30__REG DENALI_PI_156

2628

#define LPDDR4__PI_RESERVED30__FLD LPDDR4__DENALI_PI_156__PI_RESERVED30

2629

2630

#define LPDDR4__DENALI_PI_157_READ_MASK 0xFF010F07U

2631

#define LPDDR4__DENALI_PI_157_WRITE_MASK 0xFF010F07U

2632

#define LPDDR4__DENALI_PI_157__PI_RESERVED31_MASK 0x00000007U

2633

#define LPDDR4__DENALI_PI_157__PI_RESERVED31_SHIFT 0U

2634

#define LPDDR4__DENALI_PI_157__PI_RESERVED31_WIDTH 3U

2635

#define LPDDR4__PI_RESERVED31__REG DENALI_PI_157

2636

#define LPDDR4__PI_RESERVED31__FLD LPDDR4__DENALI_PI_157__PI_RESERVED31

2637

2638

#define LPDDR4__DENALI_PI_157__PI_MONITOR_SRC_SEL_0_MASK 0x00000F00U

2639

#define LPDDR4__DENALI_PI_157__PI_MONITOR_SRC_SEL_0_SHIFT 8U

2640

#define LPDDR4__DENALI_PI_157__PI_MONITOR_SRC_SEL_0_WIDTH 4U

2641

#define LPDDR4__PI_MONITOR_SRC_SEL_0__REG DENALI_PI_157

2642

#define LPDDR4__PI_MONITOR_SRC_SEL_0__FLD LPDDR4__DENALI_PI_157__PI_MONITOR_SRC_SEL_0

2643

2644

#define LPDDR4__DENALI_PI_157__PI_MONITOR_CAP_SEL_0_MASK 0x00010000U

2645

#define LPDDR4__DENALI_PI_157__PI_MONITOR_CAP_SEL_0_SHIFT 16U

2646

#define LPDDR4__DENALI_PI_157__PI_MONITOR_CAP_SEL_0_WIDTH 1U

2647

#define LPDDR4__DENALI_PI_157__PI_MONITOR_CAP_SEL_0_WOCLR 0U

2648

#define LPDDR4__DENALI_PI_157__PI_MONITOR_CAP_SEL_0_WOSET 0U

2649

#define LPDDR4__PI_MONITOR_CAP_SEL_0__REG DENALI_PI_157

2650

#define LPDDR4__PI_MONITOR_CAP_SEL_0__FLD LPDDR4__DENALI_PI_157__PI_MONITOR_CAP_SEL_0

2651

2652

#define LPDDR4__DENALI_PI_157__PI_MONITOR_0_MASK 0xFF000000U

2653

#define LPDDR4__DENALI_PI_157__PI_MONITOR_0_SHIFT 24U

2654

#define LPDDR4__DENALI_PI_157__PI_MONITOR_0_WIDTH 8U

2655

#define LPDDR4__PI_MONITOR_0__REG DENALI_PI_157

2656

#define LPDDR4__PI_MONITOR_0__FLD LPDDR4__DENALI_PI_157__PI_MONITOR_0

2657

2658

#define LPDDR4__DENALI_PI_158_READ_MASK 0x0FFF010FU

2659

#define LPDDR4__DENALI_PI_158_WRITE_MASK 0x0FFF010FU

2660

#define LPDDR4__DENALI_PI_158__PI_MONITOR_SRC_SEL_1_MASK 0x0000000FU

2661

#define LPDDR4__DENALI_PI_158__PI_MONITOR_SRC_SEL_1_SHIFT 0U

2662

#define LPDDR4__DENALI_PI_158__PI_MONITOR_SRC_SEL_1_WIDTH 4U

2663

#define LPDDR4__PI_MONITOR_SRC_SEL_1__REG DENALI_PI_158

2664

#define LPDDR4__PI_MONITOR_SRC_SEL_1__FLD LPDDR4__DENALI_PI_158__PI_MONITOR_SRC_SEL_1

2665

2666

#define LPDDR4__DENALI_PI_158__PI_MONITOR_CAP_SEL_1_MASK 0x00000100U

2667

#define LPDDR4__DENALI_PI_158__PI_MONITOR_CAP_SEL_1_SHIFT 8U

2668

#define LPDDR4__DENALI_PI_158__PI_MONITOR_CAP_SEL_1_WIDTH 1U

2669

#define LPDDR4__DENALI_PI_158__PI_MONITOR_CAP_SEL_1_WOCLR 0U

2670

#define LPDDR4__DENALI_PI_158__PI_MONITOR_CAP_SEL_1_WOSET 0U

2671

#define LPDDR4__PI_MONITOR_CAP_SEL_1__REG DENALI_PI_158

2672

#define LPDDR4__PI_MONITOR_CAP_SEL_1__FLD LPDDR4__DENALI_PI_158__PI_MONITOR_CAP_SEL_1

2673

2674

#define LPDDR4__DENALI_PI_158__PI_MONITOR_1_MASK 0x00FF0000U

2675

#define LPDDR4__DENALI_PI_158__PI_MONITOR_1_SHIFT 16U

2676

#define LPDDR4__DENALI_PI_158__PI_MONITOR_1_WIDTH 8U

2677

#define LPDDR4__PI_MONITOR_1__REG DENALI_PI_158

2678

#define LPDDR4__PI_MONITOR_1__FLD LPDDR4__DENALI_PI_158__PI_MONITOR_1

2679

2680

#define LPDDR4__DENALI_PI_158__PI_MONITOR_SRC_SEL_2_MASK 0x0F000000U

2681

#define LPDDR4__DENALI_PI_158__PI_MONITOR_SRC_SEL_2_SHIFT 24U

2682

#define LPDDR4__DENALI_PI_158__PI_MONITOR_SRC_SEL_2_WIDTH 4U

2683

#define LPDDR4__PI_MONITOR_SRC_SEL_2__REG DENALI_PI_158

2684

#define LPDDR4__PI_MONITOR_SRC_SEL_2__FLD LPDDR4__DENALI_PI_158__PI_MONITOR_SRC_SEL_2

2685

2686

#define LPDDR4__DENALI_PI_159_READ_MASK 0x010FFF01U

2687

#define LPDDR4__DENALI_PI_159_WRITE_MASK 0x010FFF01U

2688

#define LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_2_MASK 0x00000001U

2689

#define LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_2_SHIFT 0U

2690

#define LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_2_WIDTH 1U

2691

#define LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_2_WOCLR 0U

2692

#define LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_2_WOSET 0U

2693

#define LPDDR4__PI_MONITOR_CAP_SEL_2__REG DENALI_PI_159

2694

#define LPDDR4__PI_MONITOR_CAP_SEL_2__FLD LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_2

2695

2696

#define LPDDR4__DENALI_PI_159__PI_MONITOR_2_MASK 0x0000FF00U

2697

#define LPDDR4__DENALI_PI_159__PI_MONITOR_2_SHIFT 8U

2698

#define LPDDR4__DENALI_PI_159__PI_MONITOR_2_WIDTH 8U

2699

#define LPDDR4__PI_MONITOR_2__REG DENALI_PI_159

2700

#define LPDDR4__PI_MONITOR_2__FLD LPDDR4__DENALI_PI_159__PI_MONITOR_2

2701

2702

#define LPDDR4__DENALI_PI_159__PI_MONITOR_SRC_SEL_3_MASK 0x000F0000U

2703

#define LPDDR4__DENALI_PI_159__PI_MONITOR_SRC_SEL_3_SHIFT 16U

2704

#define LPDDR4__DENALI_PI_159__PI_MONITOR_SRC_SEL_3_WIDTH 4U

2705

#define LPDDR4__PI_MONITOR_SRC_SEL_3__REG DENALI_PI_159

2706

#define LPDDR4__PI_MONITOR_SRC_SEL_3__FLD LPDDR4__DENALI_PI_159__PI_MONITOR_SRC_SEL_3

2707

2708

#define LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_3_MASK 0x01000000U

2709

#define LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_3_SHIFT 24U

2710

#define LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_3_WIDTH 1U

2711

#define LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_3_WOCLR 0U

2712

#define LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_3_WOSET 0U

2713

#define LPDDR4__PI_MONITOR_CAP_SEL_3__REG DENALI_PI_159

2714

#define LPDDR4__PI_MONITOR_CAP_SEL_3__FLD LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_3

2715

2716

#define LPDDR4__DENALI_PI_160_READ_MASK 0xFF010FFFU

2717

#define LPDDR4__DENALI_PI_160_WRITE_MASK 0xFF010FFFU

2718

#define LPDDR4__DENALI_PI_160__PI_MONITOR_3_MASK 0x000000FFU

2719

#define LPDDR4__DENALI_PI_160__PI_MONITOR_3_SHIFT 0U

2720

#define LPDDR4__DENALI_PI_160__PI_MONITOR_3_WIDTH 8U

2721

#define LPDDR4__PI_MONITOR_3__REG DENALI_PI_160

2722

#define LPDDR4__PI_MONITOR_3__FLD LPDDR4__DENALI_PI_160__PI_MONITOR_3

2723

2724

#define LPDDR4__DENALI_PI_160__PI_MONITOR_SRC_SEL_4_MASK 0x00000F00U

2725

#define LPDDR4__DENALI_PI_160__PI_MONITOR_SRC_SEL_4_SHIFT 8U

2726

#define LPDDR4__DENALI_PI_160__PI_MONITOR_SRC_SEL_4_WIDTH 4U

2727

#define LPDDR4__PI_MONITOR_SRC_SEL_4__REG DENALI_PI_160

2728

#define LPDDR4__PI_MONITOR_SRC_SEL_4__FLD LPDDR4__DENALI_PI_160__PI_MONITOR_SRC_SEL_4

2729

2730

#define LPDDR4__DENALI_PI_160__PI_MONITOR_CAP_SEL_4_MASK 0x00010000U

2731

#define LPDDR4__DENALI_PI_160__PI_MONITOR_CAP_SEL_4_SHIFT 16U

2732

#define LPDDR4__DENALI_PI_160__PI_MONITOR_CAP_SEL_4_WIDTH 1U

2733

#define LPDDR4__DENALI_PI_160__PI_MONITOR_CAP_SEL_4_WOCLR 0U

2734

#define LPDDR4__DENALI_PI_160__PI_MONITOR_CAP_SEL_4_WOSET 0U

2735

#define LPDDR4__PI_MONITOR_CAP_SEL_4__REG DENALI_PI_160

2736

#define LPDDR4__PI_MONITOR_CAP_SEL_4__FLD LPDDR4__DENALI_PI_160__PI_MONITOR_CAP_SEL_4

2737

2738

#define LPDDR4__DENALI_PI_160__PI_MONITOR_4_MASK 0xFF000000U

2739

#define LPDDR4__DENALI_PI_160__PI_MONITOR_4_SHIFT 24U

2740

#define LPDDR4__DENALI_PI_160__PI_MONITOR_4_WIDTH 8U

2741

#define LPDDR4__PI_MONITOR_4__REG DENALI_PI_160

2742

#define LPDDR4__PI_MONITOR_4__FLD LPDDR4__DENALI_PI_160__PI_MONITOR_4

2743

2744

#define LPDDR4__DENALI_PI_161_READ_MASK 0x0FFF010FU

2745

#define LPDDR4__DENALI_PI_161_WRITE_MASK 0x0FFF010FU

2746

#define LPDDR4__DENALI_PI_161__PI_MONITOR_SRC_SEL_5_MASK 0x0000000FU

2747

#define LPDDR4__DENALI_PI_161__PI_MONITOR_SRC_SEL_5_SHIFT 0U

2748

#define LPDDR4__DENALI_PI_161__PI_MONITOR_SRC_SEL_5_WIDTH 4U

2749

#define LPDDR4__PI_MONITOR_SRC_SEL_5__REG DENALI_PI_161

2750

#define LPDDR4__PI_MONITOR_SRC_SEL_5__FLD LPDDR4__DENALI_PI_161__PI_MONITOR_SRC_SEL_5

2751

2752

#define LPDDR4__DENALI_PI_161__PI_MONITOR_CAP_SEL_5_MASK 0x00000100U

2753

#define LPDDR4__DENALI_PI_161__PI_MONITOR_CAP_SEL_5_SHIFT 8U

2754

#define LPDDR4__DENALI_PI_161__PI_MONITOR_CAP_SEL_5_WIDTH 1U

2755

#define LPDDR4__DENALI_PI_161__PI_MONITOR_CAP_SEL_5_WOCLR 0U

2756

#define LPDDR4__DENALI_PI_161__PI_MONITOR_CAP_SEL_5_WOSET 0U

2757

#define LPDDR4__PI_MONITOR_CAP_SEL_5__REG DENALI_PI_161

2758

#define LPDDR4__PI_MONITOR_CAP_SEL_5__FLD LPDDR4__DENALI_PI_161__PI_MONITOR_CAP_SEL_5

2759

2760

#define LPDDR4__DENALI_PI_161__PI_MONITOR_5_MASK 0x00FF0000U

2761

#define LPDDR4__DENALI_PI_161__PI_MONITOR_5_SHIFT 16U

2762

#define LPDDR4__DENALI_PI_161__PI_MONITOR_5_WIDTH 8U

2763

#define LPDDR4__PI_MONITOR_5__REG DENALI_PI_161

2764

#define LPDDR4__PI_MONITOR_5__FLD LPDDR4__DENALI_PI_161__PI_MONITOR_5

2765

2766

#define LPDDR4__DENALI_PI_161__PI_MONITOR_SRC_SEL_6_MASK 0x0F000000U

2767

#define LPDDR4__DENALI_PI_161__PI_MONITOR_SRC_SEL_6_SHIFT 24U

2768

#define LPDDR4__DENALI_PI_161__PI_MONITOR_SRC_SEL_6_WIDTH 4U

2769

#define LPDDR4__PI_MONITOR_SRC_SEL_6__REG DENALI_PI_161

2770

#define LPDDR4__PI_MONITOR_SRC_SEL_6__FLD LPDDR4__DENALI_PI_161__PI_MONITOR_SRC_SEL_6

2771

2772

#define LPDDR4__DENALI_PI_162_READ_MASK 0x010FFF01U

2773

#define LPDDR4__DENALI_PI_162_WRITE_MASK 0x010FFF01U

2774

#define LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_6_MASK 0x00000001U

2775

#define LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_6_SHIFT 0U

2776

#define LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_6_WIDTH 1U

2777

#define LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_6_WOCLR 0U

2778

#define LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_6_WOSET 0U

2779

#define LPDDR4__PI_MONITOR_CAP_SEL_6__REG DENALI_PI_162

2780

#define LPDDR4__PI_MONITOR_CAP_SEL_6__FLD LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_6

2781

2782

#define LPDDR4__DENALI_PI_162__PI_MONITOR_6_MASK 0x0000FF00U

2783

#define LPDDR4__DENALI_PI_162__PI_MONITOR_6_SHIFT 8U

2784

#define LPDDR4__DENALI_PI_162__PI_MONITOR_6_WIDTH 8U

2785

#define LPDDR4__PI_MONITOR_6__REG DENALI_PI_162

2786

#define LPDDR4__PI_MONITOR_6__FLD LPDDR4__DENALI_PI_162__PI_MONITOR_6

2787

2788

#define LPDDR4__DENALI_PI_162__PI_MONITOR_SRC_SEL_7_MASK 0x000F0000U

2789

#define LPDDR4__DENALI_PI_162__PI_MONITOR_SRC_SEL_7_SHIFT 16U

2790

#define LPDDR4__DENALI_PI_162__PI_MONITOR_SRC_SEL_7_WIDTH 4U

2791

#define LPDDR4__PI_MONITOR_SRC_SEL_7__REG DENALI_PI_162

2792

#define LPDDR4__PI_MONITOR_SRC_SEL_7__FLD LPDDR4__DENALI_PI_162__PI_MONITOR_SRC_SEL_7

2793

2794

#define LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_7_MASK 0x01000000U

2795

#define LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_7_SHIFT 24U

2796

#define LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_7_WIDTH 1U

2797

#define LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_7_WOCLR 0U

2798

#define LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_7_WOSET 0U

2799

#define LPDDR4__PI_MONITOR_CAP_SEL_7__REG DENALI_PI_162

2800

#define LPDDR4__PI_MONITOR_CAP_SEL_7__FLD LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_7

2801

2802

#define LPDDR4__DENALI_PI_163_READ_MASK 0x000000FFU

2803

#define LPDDR4__DENALI_PI_163_WRITE_MASK 0x000000FFU

2804

#define LPDDR4__DENALI_PI_163__PI_MONITOR_7_MASK 0x000000FFU

2805

#define LPDDR4__DENALI_PI_163__PI_MONITOR_7_SHIFT 0U

2806

#define LPDDR4__DENALI_PI_163__PI_MONITOR_7_WIDTH 8U

2807

#define LPDDR4__PI_MONITOR_7__REG DENALI_PI_163

2808

#define LPDDR4__PI_MONITOR_7__FLD LPDDR4__DENALI_PI_163__PI_MONITOR_7

2809

2810

#define LPDDR4__DENALI_PI_164__PI_MONITOR_STROBE_MASK 0x000000FFU

2811

#define LPDDR4__DENALI_PI_164__PI_MONITOR_STROBE_SHIFT 0U

2812

#define LPDDR4__DENALI_PI_164__PI_MONITOR_STROBE_WIDTH 8U

2813

#define LPDDR4__PI_MONITOR_STROBE__REG DENALI_PI_164

2814

#define LPDDR4__PI_MONITOR_STROBE__FLD LPDDR4__DENALI_PI_164__PI_MONITOR_STROBE

2815

2816

#define LPDDR4__DENALI_PI_165_READ_MASK 0x011F1F01U

2817

#define LPDDR4__DENALI_PI_165_WRITE_MASK 0x011F1F01U

2818

#define LPDDR4__DENALI_PI_165__PI_DLL_LOCK_MASK 0x00000001U

2819

#define LPDDR4__DENALI_PI_165__PI_DLL_LOCK_SHIFT 0U

2820

#define LPDDR4__DENALI_PI_165__PI_DLL_LOCK_WIDTH 1U

2821

#define LPDDR4__DENALI_PI_165__PI_DLL_LOCK_WOCLR 0U

2822

#define LPDDR4__DENALI_PI_165__PI_DLL_LOCK_WOSET 0U

2823

#define LPDDR4__PI_DLL_LOCK__REG DENALI_PI_165

2824

#define LPDDR4__PI_DLL_LOCK__FLD LPDDR4__DENALI_PI_165__PI_DLL_LOCK

2825

2826

#define LPDDR4__DENALI_PI_165__PI_FREQ_NUMBER_STATUS_MASK 0x00001F00U

2827

#define LPDDR4__DENALI_PI_165__PI_FREQ_NUMBER_STATUS_SHIFT 8U

2828

#define LPDDR4__DENALI_PI_165__PI_FREQ_NUMBER_STATUS_WIDTH 5U

2829

#define LPDDR4__PI_FREQ_NUMBER_STATUS__REG DENALI_PI_165

2830

#define LPDDR4__PI_FREQ_NUMBER_STATUS__FLD LPDDR4__DENALI_PI_165__PI_FREQ_NUMBER_STATUS

2831

2832

#define LPDDR4__DENALI_PI_165__PI_FREQ_RETENTION_NUM_MASK 0x001F0000U

2833

#define LPDDR4__DENALI_PI_165__PI_FREQ_RETENTION_NUM_SHIFT 16U

2834

#define LPDDR4__DENALI_PI_165__PI_FREQ_RETENTION_NUM_WIDTH 5U

2835

#define LPDDR4__PI_FREQ_RETENTION_NUM__REG DENALI_PI_165

2836

#define LPDDR4__PI_FREQ_RETENTION_NUM__FLD LPDDR4__DENALI_PI_165__PI_FREQ_RETENTION_NUM

2837

2838

#define LPDDR4__DENALI_PI_165__PI_RESERVED32_MASK 0x01000000U

2839

#define LPDDR4__DENALI_PI_165__PI_RESERVED32_SHIFT 24U

2840

#define LPDDR4__DENALI_PI_165__PI_RESERVED32_WIDTH 1U

2841

#define LPDDR4__DENALI_PI_165__PI_RESERVED32_WOCLR 0U

2842

#define LPDDR4__DENALI_PI_165__PI_RESERVED32_WOSET 0U

2843

#define LPDDR4__PI_RESERVED32__REG DENALI_PI_165

2844

#define LPDDR4__PI_RESERVED32__FLD LPDDR4__DENALI_PI_165__PI_RESERVED32

2845

2846

#define LPDDR4__DENALI_PI_166_READ_MASK 0x01010103U

2847

#define LPDDR4__DENALI_PI_166_WRITE_MASK 0x01010103U

2848

#define LPDDR4__DENALI_PI_166__PI_PHYMSTR_TYPE_MASK 0x00000003U

2849

#define LPDDR4__DENALI_PI_166__PI_PHYMSTR_TYPE_SHIFT 0U

2850

#define LPDDR4__DENALI_PI_166__PI_PHYMSTR_TYPE_WIDTH 2U

2851

#define LPDDR4__PI_PHYMSTR_TYPE__REG DENALI_PI_166

2852

#define LPDDR4__PI_PHYMSTR_TYPE__FLD LPDDR4__DENALI_PI_166__PI_PHYMSTR_TYPE

2853

2854

#define LPDDR4__DENALI_PI_166__PI_RESERVED33_MASK 0x00000100U

2855

#define LPDDR4__DENALI_PI_166__PI_RESERVED33_SHIFT 8U

2856

#define LPDDR4__DENALI_PI_166__PI_RESERVED33_WIDTH 1U

2857

#define LPDDR4__DENALI_PI_166__PI_RESERVED33_WOCLR 0U

2858

#define LPDDR4__DENALI_PI_166__PI_RESERVED33_WOSET 0U

2859

#define LPDDR4__PI_RESERVED33__REG DENALI_PI_166

2860

#define LPDDR4__PI_RESERVED33__FLD LPDDR4__DENALI_PI_166__PI_RESERVED33

2861

2862

#define LPDDR4__DENALI_PI_166__PI_POWER_REDUC_EN_MASK 0x00010000U

2863

#define LPDDR4__DENALI_PI_166__PI_POWER_REDUC_EN_SHIFT 16U

2864

#define LPDDR4__DENALI_PI_166__PI_POWER_REDUC_EN_WIDTH 1U

2865

#define LPDDR4__DENALI_PI_166__PI_POWER_REDUC_EN_WOCLR 0U

2866

#define LPDDR4__DENALI_PI_166__PI_POWER_REDUC_EN_WOSET 0U

2867

#define LPDDR4__PI_POWER_REDUC_EN__REG DENALI_PI_166

2868

#define LPDDR4__PI_POWER_REDUC_EN__FLD LPDDR4__DENALI_PI_166__PI_POWER_REDUC_EN

2869

2870

#define LPDDR4__DENALI_PI_166__PI_RESERVED34_MASK 0x01000000U

2871

#define LPDDR4__DENALI_PI_166__PI_RESERVED34_SHIFT 24U

2872

#define LPDDR4__DENALI_PI_166__PI_RESERVED34_WIDTH 1U

2873

#define LPDDR4__DENALI_PI_166__PI_RESERVED34_WOCLR 0U

2874

#define LPDDR4__DENALI_PI_166__PI_RESERVED34_WOSET 0U

2875

#define LPDDR4__PI_RESERVED34__REG DENALI_PI_166

2876

#define LPDDR4__PI_RESERVED34__FLD LPDDR4__DENALI_PI_166__PI_RESERVED34

2877

2878

#define LPDDR4__DENALI_PI_167_READ_MASK 0x01010101U

2879

#define LPDDR4__DENALI_PI_167_WRITE_MASK 0x01010101U

2880

#define LPDDR4__DENALI_PI_167__PI_RESERVED35_MASK 0x00000001U

2881

#define LPDDR4__DENALI_PI_167__PI_RESERVED35_SHIFT 0U

2882

#define LPDDR4__DENALI_PI_167__PI_RESERVED35_WIDTH 1U

2883

#define LPDDR4__DENALI_PI_167__PI_RESERVED35_WOCLR 0U

2884

#define LPDDR4__DENALI_PI_167__PI_RESERVED35_WOSET 0U

2885

#define LPDDR4__PI_RESERVED35__REG DENALI_PI_167

2886

#define LPDDR4__PI_RESERVED35__FLD LPDDR4__DENALI_PI_167__PI_RESERVED35

2887

2888

#define LPDDR4__DENALI_PI_167__PI_RESERVED36_MASK 0x00000100U

2889

#define LPDDR4__DENALI_PI_167__PI_RESERVED36_SHIFT 8U

2890

#define LPDDR4__DENALI_PI_167__PI_RESERVED36_WIDTH 1U

2891

#define LPDDR4__DENALI_PI_167__PI_RESERVED36_WOCLR 0U

2892

#define LPDDR4__DENALI_PI_167__PI_RESERVED36_WOSET 0U

2893

#define LPDDR4__PI_RESERVED36__REG DENALI_PI_167

2894

#define LPDDR4__PI_RESERVED36__FLD LPDDR4__DENALI_PI_167__PI_RESERVED36

2895

2896

#define LPDDR4__DENALI_PI_167__PI_RESERVED37_MASK 0x00010000U

2897

#define LPDDR4__DENALI_PI_167__PI_RESERVED37_SHIFT 16U

2898

#define LPDDR4__DENALI_PI_167__PI_RESERVED37_WIDTH 1U

2899

#define LPDDR4__DENALI_PI_167__PI_RESERVED37_WOCLR 0U

2900

#define LPDDR4__DENALI_PI_167__PI_RESERVED37_WOSET 0U

2901

#define LPDDR4__PI_RESERVED37__REG DENALI_PI_167

2902

#define LPDDR4__PI_RESERVED37__FLD LPDDR4__DENALI_PI_167__PI_RESERVED37

2903

2904

#define LPDDR4__DENALI_PI_167__PI_RESERVED38_MASK 0x01000000U

2905

#define LPDDR4__DENALI_PI_167__PI_RESERVED38_SHIFT 24U

2906

#define LPDDR4__DENALI_PI_167__PI_RESERVED38_WIDTH 1U

2907

#define LPDDR4__DENALI_PI_167__PI_RESERVED38_WOCLR 0U

2908

#define LPDDR4__DENALI_PI_167__PI_RESERVED38_WOSET 0U

2909

#define LPDDR4__PI_RESERVED38__REG DENALI_PI_167

2910

#define LPDDR4__PI_RESERVED38__FLD LPDDR4__DENALI_PI_167__PI_RESERVED38

2911

2912

#define LPDDR4__DENALI_PI_168_READ_MASK 0x01010101U

2913

#define LPDDR4__DENALI_PI_168_WRITE_MASK 0x01010101U

2914

#define LPDDR4__DENALI_PI_168__PI_RESERVED39_MASK 0x00000001U

2915

#define LPDDR4__DENALI_PI_168__PI_RESERVED39_SHIFT 0U

2916

#define LPDDR4__DENALI_PI_168__PI_RESERVED39_WIDTH 1U

2917

#define LPDDR4__DENALI_PI_168__PI_RESERVED39_WOCLR 0U

2918

#define LPDDR4__DENALI_PI_168__PI_RESERVED39_WOSET 0U

2919

#define LPDDR4__PI_RESERVED39__REG DENALI_PI_168

2920

#define LPDDR4__PI_RESERVED39__FLD LPDDR4__DENALI_PI_168__PI_RESERVED39

2921

2922

#define LPDDR4__DENALI_PI_168__PI_RESERVED40_MASK 0x00000100U

2923

#define LPDDR4__DENALI_PI_168__PI_RESERVED40_SHIFT 8U

2924

#define LPDDR4__DENALI_PI_168__PI_RESERVED40_WIDTH 1U

2925

#define LPDDR4__DENALI_PI_168__PI_RESERVED40_WOCLR 0U

2926

#define LPDDR4__DENALI_PI_168__PI_RESERVED40_WOSET 0U

2927

#define LPDDR4__PI_RESERVED40__REG DENALI_PI_168

2928

#define LPDDR4__PI_RESERVED40__FLD LPDDR4__DENALI_PI_168__PI_RESERVED40

2929

2930

#define LPDDR4__DENALI_PI_168__PI_RESERVED41_MASK 0x00010000U

2931

#define LPDDR4__DENALI_PI_168__PI_RESERVED41_SHIFT 16U

2932

#define LPDDR4__DENALI_PI_168__PI_RESERVED41_WIDTH 1U

2933

#define LPDDR4__DENALI_PI_168__PI_RESERVED41_WOCLR 0U

2934

#define LPDDR4__DENALI_PI_168__PI_RESERVED41_WOSET 0U

2935

#define LPDDR4__PI_RESERVED41__REG DENALI_PI_168

2936

#define LPDDR4__PI_RESERVED41__FLD LPDDR4__DENALI_PI_168__PI_RESERVED41

2937

2938

#define LPDDR4__DENALI_PI_168__PI_RESERVED42_MASK 0x01000000U

2939

#define LPDDR4__DENALI_PI_168__PI_RESERVED42_SHIFT 24U

2940

#define LPDDR4__DENALI_PI_168__PI_RESERVED42_WIDTH 1U

2941

#define LPDDR4__DENALI_PI_168__PI_RESERVED42_WOCLR 0U

2942

#define LPDDR4__DENALI_PI_168__PI_RESERVED42_WOSET 0U

2943

#define LPDDR4__PI_RESERVED42__REG DENALI_PI_168

2944

#define LPDDR4__PI_RESERVED42__FLD LPDDR4__DENALI_PI_168__PI_RESERVED42

2945

2946

#define LPDDR4__DENALI_PI_169_READ_MASK 0x01010101U

2947

#define LPDDR4__DENALI_PI_169_WRITE_MASK 0x01010101U

2948

#define LPDDR4__DENALI_PI_169__PI_RESERVED43_MASK 0x00000001U

2949

#define LPDDR4__DENALI_PI_169__PI_RESERVED43_SHIFT 0U

2950

#define LPDDR4__DENALI_PI_169__PI_RESERVED43_WIDTH 1U

2951

#define LPDDR4__DENALI_PI_169__PI_RESERVED43_WOCLR 0U

2952

#define LPDDR4__DENALI_PI_169__PI_RESERVED43_WOSET 0U

2953

#define LPDDR4__PI_RESERVED43__REG DENALI_PI_169

2954

#define LPDDR4__PI_RESERVED43__FLD LPDDR4__DENALI_PI_169__PI_RESERVED43

2955

2956

#define LPDDR4__DENALI_PI_169__PI_RESERVED44_MASK 0x00000100U

2957

#define LPDDR4__DENALI_PI_169__PI_RESERVED44_SHIFT 8U

2958

#define LPDDR4__DENALI_PI_169__PI_RESERVED44_WIDTH 1U

2959

#define LPDDR4__DENALI_PI_169__PI_RESERVED44_WOCLR 0U

2960

#define LPDDR4__DENALI_PI_169__PI_RESERVED44_WOSET 0U

2961

#define LPDDR4__PI_RESERVED44__REG DENALI_PI_169

2962

#define LPDDR4__PI_RESERVED44__FLD LPDDR4__DENALI_PI_169__PI_RESERVED44

2963

2964

#define LPDDR4__DENALI_PI_169__PI_RESERVED45_MASK 0x00010000U

2965

#define LPDDR4__DENALI_PI_169__PI_RESERVED45_SHIFT 16U

2966

#define LPDDR4__DENALI_PI_169__PI_RESERVED45_WIDTH 1U

2967

#define LPDDR4__DENALI_PI_169__PI_RESERVED45_WOCLR 0U

2968

#define LPDDR4__DENALI_PI_169__PI_RESERVED45_WOSET 0U

2969

#define LPDDR4__PI_RESERVED45__REG DENALI_PI_169

2970

#define LPDDR4__PI_RESERVED45__FLD LPDDR4__DENALI_PI_169__PI_RESERVED45

2971

2972

#define LPDDR4__DENALI_PI_169__PI_RESERVED46_MASK 0x01000000U

2973

#define LPDDR4__DENALI_PI_169__PI_RESERVED46_SHIFT 24U

2974

#define LPDDR4__DENALI_PI_169__PI_RESERVED46_WIDTH 1U

2975

#define LPDDR4__DENALI_PI_169__PI_RESERVED46_WOCLR 0U

2976

#define LPDDR4__DENALI_PI_169__PI_RESERVED46_WOSET 0U

2977

#define LPDDR4__PI_RESERVED46__REG DENALI_PI_169

2978

#define LPDDR4__PI_RESERVED46__FLD LPDDR4__DENALI_PI_169__PI_RESERVED46

2979

2980

#define LPDDR4__DENALI_PI_170_READ_MASK 0x01010101U

2981

#define LPDDR4__DENALI_PI_170_WRITE_MASK 0x01010101U

2982

#define LPDDR4__DENALI_PI_170__PI_RESERVED47_MASK 0x00000001U

2983

#define LPDDR4__DENALI_PI_170__PI_RESERVED47_SHIFT 0U

2984

#define LPDDR4__DENALI_PI_170__PI_RESERVED47_WIDTH 1U

2985

#define LPDDR4__DENALI_PI_170__PI_RESERVED47_WOCLR 0U

2986

#define LPDDR4__DENALI_PI_170__PI_RESERVED47_WOSET 0U

2987

#define LPDDR4__PI_RESERVED47__REG DENALI_PI_170

2988

#define LPDDR4__PI_RESERVED47__FLD LPDDR4__DENALI_PI_170__PI_RESERVED47

2989

2990

#define LPDDR4__DENALI_PI_170__PI_RESERVED48_MASK 0x00000100U

2991

#define LPDDR4__DENALI_PI_170__PI_RESERVED48_SHIFT 8U

2992

#define LPDDR4__DENALI_PI_170__PI_RESERVED48_WIDTH 1U

2993

#define LPDDR4__DENALI_PI_170__PI_RESERVED48_WOCLR 0U

2994

#define LPDDR4__DENALI_PI_170__PI_RESERVED48_WOSET 0U

2995

#define LPDDR4__PI_RESERVED48__REG DENALI_PI_170

2996

#define LPDDR4__PI_RESERVED48__FLD LPDDR4__DENALI_PI_170__PI_RESERVED48

2997

2998

#define LPDDR4__DENALI_PI_170__PI_RESERVED49_MASK 0x00010000U

2999

#define LPDDR4__DENALI_PI_170__PI_RESERVED49_SHIFT 16U

3000

#define LPDDR4__DENALI_PI_170__PI_RESERVED49_WIDTH 1U

3001

#define LPDDR4__DENALI_PI_170__PI_RESERVED49_WOCLR 0U

3002

#define LPDDR4__DENALI_PI_170__PI_RESERVED49_WOSET 0U

3003

#define LPDDR4__PI_RESERVED49__REG DENALI_PI_170

3004

#define LPDDR4__PI_RESERVED49__FLD LPDDR4__DENALI_PI_170__PI_RESERVED49

3005

3006

#define LPDDR4__DENALI_PI_170__PI_RESERVED50_MASK 0x01000000U

3007

#define LPDDR4__DENALI_PI_170__PI_RESERVED50_SHIFT 24U

3008

#define LPDDR4__DENALI_PI_170__PI_RESERVED50_WIDTH 1U

3009

#define LPDDR4__DENALI_PI_170__PI_RESERVED50_WOCLR 0U

3010

#define LPDDR4__DENALI_PI_170__PI_RESERVED50_WOSET 0U

3011

#define LPDDR4__PI_RESERVED50__REG DENALI_PI_170

3012

#define LPDDR4__PI_RESERVED50__FLD LPDDR4__DENALI_PI_170__PI_RESERVED50

3013

3014

#define LPDDR4__DENALI_PI_171_READ_MASK 0x00FF0101U

3015

#define LPDDR4__DENALI_PI_171_WRITE_MASK 0x00FF0101U

3016

#define LPDDR4__DENALI_PI_171__PI_RESERVED51_MASK 0x00000001U

3017

#define LPDDR4__DENALI_PI_171__PI_RESERVED51_SHIFT 0U

3018

#define LPDDR4__DENALI_PI_171__PI_RESERVED51_WIDTH 1U

3019

#define LPDDR4__DENALI_PI_171__PI_RESERVED51_WOCLR 0U

3020

#define LPDDR4__DENALI_PI_171__PI_RESERVED51_WOSET 0U

3021

#define LPDDR4__PI_RESERVED51__REG DENALI_PI_171

3022

#define LPDDR4__PI_RESERVED51__FLD LPDDR4__DENALI_PI_171__PI_RESERVED51

3023

3024

#define LPDDR4__DENALI_PI_171__PI_RESERVED52_MASK 0x00000100U

3025

#define LPDDR4__DENALI_PI_171__PI_RESERVED52_SHIFT 8U

3026

#define LPDDR4__DENALI_PI_171__PI_RESERVED52_WIDTH 1U

3027

#define LPDDR4__DENALI_PI_171__PI_RESERVED52_WOCLR 0U

3028

#define LPDDR4__DENALI_PI_171__PI_RESERVED52_WOSET 0U

3029

#define LPDDR4__PI_RESERVED52__REG DENALI_PI_171

3030

#define LPDDR4__PI_RESERVED52__FLD LPDDR4__DENALI_PI_171__PI_RESERVED52

3031

3032

#define LPDDR4__DENALI_PI_171__PI_WRLVL_MAX_STROBE_PEND_MASK 0x00FF0000U

3033

#define LPDDR4__DENALI_PI_171__PI_WRLVL_MAX_STROBE_PEND_SHIFT 16U

3034

#define LPDDR4__DENALI_PI_171__PI_WRLVL_MAX_STROBE_PEND_WIDTH 8U

3035

#define LPDDR4__PI_WRLVL_MAX_STROBE_PEND__REG DENALI_PI_171

3036

#define LPDDR4__PI_WRLVL_MAX_STROBE_PEND__FLD LPDDR4__DENALI_PI_171__PI_WRLVL_MAX_STROBE_PEND

3037

3038

#define LPDDR4__DENALI_PI_172_READ_MASK 0x000001FFU

3039

#define LPDDR4__DENALI_PI_172_WRITE_MASK 0x000001FFU

3040

#define LPDDR4__DENALI_PI_172__PI_TREFBW_THR_MASK 0x000001FFU

3041

#define LPDDR4__DENALI_PI_172__PI_TREFBW_THR_SHIFT 0U

3042

#define LPDDR4__DENALI_PI_172__PI_TREFBW_THR_WIDTH 9U

3043

#define LPDDR4__PI_TREFBW_THR__REG DENALI_PI_172

3044

#define LPDDR4__PI_TREFBW_THR__FLD LPDDR4__DENALI_PI_172__PI_TREFBW_THR

3045

3046

#define LPDDR4__DENALI_PI_173_READ_MASK 0x0000001FU

3047

#define LPDDR4__DENALI_PI_173_WRITE_MASK 0x0000001FU

3048

#define LPDDR4__DENALI_PI_173__PI_FREQ_CHANGE_REG_COPY_MASK 0x0000001FU

3049

#define LPDDR4__DENALI_PI_173__PI_FREQ_CHANGE_REG_COPY_SHIFT 0U

3050

#define LPDDR4__DENALI_PI_173__PI_FREQ_CHANGE_REG_COPY_WIDTH 5U

3051

#define LPDDR4__PI_FREQ_CHANGE_REG_COPY__REG DENALI_PI_173

3052

#define LPDDR4__PI_FREQ_CHANGE_REG_COPY__FLD LPDDR4__DENALI_PI_173__PI_FREQ_CHANGE_REG_COPY

3053

3054

#define LPDDR4__DENALI_PI_174_READ_MASK 0x0F011F01U

3055

#define LPDDR4__DENALI_PI_174_WRITE_MASK 0x0F011F01U

3056

#define LPDDR4__DENALI_PI_174__PI_FREQ_SEL_FROM_REGIF_MASK 0x00000001U

3057

#define LPDDR4__DENALI_PI_174__PI_FREQ_SEL_FROM_REGIF_SHIFT 0U

3058

#define LPDDR4__DENALI_PI_174__PI_FREQ_SEL_FROM_REGIF_WIDTH 1U

3059

#define LPDDR4__DENALI_PI_174__PI_FREQ_SEL_FROM_REGIF_WOCLR 0U

3060

#define LPDDR4__DENALI_PI_174__PI_FREQ_SEL_FROM_REGIF_WOSET 0U

3061

#define LPDDR4__PI_FREQ_SEL_FROM_REGIF__REG DENALI_PI_174

3062

#define LPDDR4__PI_FREQ_SEL_FROM_REGIF__FLD LPDDR4__DENALI_PI_174__PI_FREQ_SEL_FROM_REGIF

3063

3064

#define LPDDR4__DENALI_PI_174__PI_RESERVED53_MASK 0x00001F00U

3065

#define LPDDR4__DENALI_PI_174__PI_RESERVED53_SHIFT 8U

3066

#define LPDDR4__DENALI_PI_174__PI_RESERVED53_WIDTH 5U

3067

#define LPDDR4__PI_RESERVED53__REG DENALI_PI_174

3068

#define LPDDR4__PI_RESERVED53__FLD LPDDR4__DENALI_PI_174__PI_RESERVED53

3069

3070

#define LPDDR4__DENALI_PI_174__PI_PARALLEL_CALVL_EN_MASK 0x00010000U

3071

#define LPDDR4__DENALI_PI_174__PI_PARALLEL_CALVL_EN_SHIFT 16U

3072

#define LPDDR4__DENALI_PI_174__PI_PARALLEL_CALVL_EN_WIDTH 1U

3073

#define LPDDR4__DENALI_PI_174__PI_PARALLEL_CALVL_EN_WOCLR 0U

3074

#define LPDDR4__DENALI_PI_174__PI_PARALLEL_CALVL_EN_WOSET 0U

3075

#define LPDDR4__PI_PARALLEL_CALVL_EN__REG DENALI_PI_174

3076

#define LPDDR4__PI_PARALLEL_CALVL_EN__FLD LPDDR4__DENALI_PI_174__PI_PARALLEL_CALVL_EN

3077

3078

#define LPDDR4__DENALI_PI_174__PI_CATR_MASK 0x0F000000U

3079

#define LPDDR4__DENALI_PI_174__PI_CATR_SHIFT 24U

3080

#define LPDDR4__DENALI_PI_174__PI_CATR_WIDTH 4U

3081

#define LPDDR4__PI_CATR__REG DENALI_PI_174

3082

#define LPDDR4__PI_CATR__FLD LPDDR4__DENALI_PI_174__PI_CATR

3083

3084

#define LPDDR4__DENALI_PI_175_READ_MASK 0x01010101U

3085

#define LPDDR4__DENALI_PI_175_WRITE_MASK 0x01010101U

3086

#define LPDDR4__DENALI_PI_175__PI_NO_CATR_READ_MASK 0x00000001U

3087

#define LPDDR4__DENALI_PI_175__PI_NO_CATR_READ_SHIFT 0U

3088

#define LPDDR4__DENALI_PI_175__PI_NO_CATR_READ_WIDTH 1U

3089

#define LPDDR4__DENALI_PI_175__PI_NO_CATR_READ_WOCLR 0U

3090

#define LPDDR4__DENALI_PI_175__PI_NO_CATR_READ_WOSET 0U

3091

#define LPDDR4__PI_NO_CATR_READ__REG DENALI_PI_175

3092

#define LPDDR4__PI_NO_CATR_READ__FLD LPDDR4__DENALI_PI_175__PI_NO_CATR_READ

3093

3094

#define LPDDR4__DENALI_PI_175__PI_MASK_INIT_COMPLETE_MASK 0x00000100U

3095

#define LPDDR4__DENALI_PI_175__PI_MASK_INIT_COMPLETE_SHIFT 8U

3096

#define LPDDR4__DENALI_PI_175__PI_MASK_INIT_COMPLETE_WIDTH 1U

3097

#define LPDDR4__DENALI_PI_175__PI_MASK_INIT_COMPLETE_WOCLR 0U

3098

#define LPDDR4__DENALI_PI_175__PI_MASK_INIT_COMPLETE_WOSET 0U

3099

#define LPDDR4__PI_MASK_INIT_COMPLETE__REG DENALI_PI_175

3100

#define LPDDR4__PI_MASK_INIT_COMPLETE__FLD LPDDR4__DENALI_PI_175__PI_MASK_INIT_COMPLETE

3101

3102

#define LPDDR4__DENALI_PI_175__PI_DISCONNECT_MC_MASK 0x00010000U

3103

#define LPDDR4__DENALI_PI_175__PI_DISCONNECT_MC_SHIFT 16U

3104

#define LPDDR4__DENALI_PI_175__PI_DISCONNECT_MC_WIDTH 1U

3105

#define LPDDR4__DENALI_PI_175__PI_DISCONNECT_MC_WOCLR 0U

3106

#define LPDDR4__DENALI_PI_175__PI_DISCONNECT_MC_WOSET 0U

3107

#define LPDDR4__PI_DISCONNECT_MC__REG DENALI_PI_175

3108

#define LPDDR4__PI_DISCONNECT_MC__FLD LPDDR4__DENALI_PI_175__PI_DISCONNECT_MC

3109

3110

#define LPDDR4__DENALI_PI_175__PI_DISABLE_PHYMSTR_REQ_MASK 0x01000000U

3111

#define LPDDR4__DENALI_PI_175__PI_DISABLE_PHYMSTR_REQ_SHIFT 24U

3112

#define LPDDR4__DENALI_PI_175__PI_DISABLE_PHYMSTR_REQ_WIDTH 1U

3113

#define LPDDR4__DENALI_PI_175__PI_DISABLE_PHYMSTR_REQ_WOCLR 0U

3114

#define LPDDR4__DENALI_PI_175__PI_DISABLE_PHYMSTR_REQ_WOSET 0U

3115

#define LPDDR4__PI_DISABLE_PHYMSTR_REQ__REG DENALI_PI_175

3116

#define LPDDR4__PI_DISABLE_PHYMSTR_REQ__FLD LPDDR4__DENALI_PI_175__PI_DISABLE_PHYMSTR_REQ

3117

3118

#define LPDDR4__DENALI_PI_176_READ_MASK 0xFFFF0701U

3119

#define LPDDR4__DENALI_PI_176_WRITE_MASK 0xFFFF0701U

3120

#define LPDDR4__DENALI_PI_176__PI_NOTCARE_MC_INIT_START_MASK 0x00000001U

3121

#define LPDDR4__DENALI_PI_176__PI_NOTCARE_MC_INIT_START_SHIFT 0U

3122

#define LPDDR4__DENALI_PI_176__PI_NOTCARE_MC_INIT_START_WIDTH 1U

3123

#define LPDDR4__DENALI_PI_176__PI_NOTCARE_MC_INIT_START_WOCLR 0U

3124

#define LPDDR4__DENALI_PI_176__PI_NOTCARE_MC_INIT_START_WOSET 0U

3125

#define LPDDR4__PI_NOTCARE_MC_INIT_START__REG DENALI_PI_176

3126

#define LPDDR4__PI_NOTCARE_MC_INIT_START__FLD LPDDR4__DENALI_PI_176__PI_NOTCARE_MC_INIT_START

3127

3128

#define LPDDR4__DENALI_PI_176__PI_PHYMSTR_REQ_ACK_LOOP_DELAY_MASK 0x00000700U

3129

#define LPDDR4__DENALI_PI_176__PI_PHYMSTR_REQ_ACK_LOOP_DELAY_SHIFT 8U

3130

#define LPDDR4__DENALI_PI_176__PI_PHYMSTR_REQ_ACK_LOOP_DELAY_WIDTH 3U

3131

#define LPDDR4__PI_PHYMSTR_REQ_ACK_LOOP_DELAY__REG DENALI_PI_176

3132

#define LPDDR4__PI_PHYMSTR_REQ_ACK_LOOP_DELAY__FLD LPDDR4__DENALI_PI_176__PI_PHYMSTR_REQ_ACK_LOOP_DELAY

3133

3134

#define LPDDR4__DENALI_PI_176__PI_TVREF_F0_MASK 0xFFFF0000U

3135

#define LPDDR4__DENALI_PI_176__PI_TVREF_F0_SHIFT 16U

3136

#define LPDDR4__DENALI_PI_176__PI_TVREF_F0_WIDTH 16U

3137

#define LPDDR4__PI_TVREF_F0__REG DENALI_PI_176

3138

#define LPDDR4__PI_TVREF_F0__FLD LPDDR4__DENALI_PI_176__PI_TVREF_F0

3139

3140

#define LPDDR4__DENALI_PI_177_READ_MASK 0xFFFFFFFFU

3141

#define LPDDR4__DENALI_PI_177_WRITE_MASK 0xFFFFFFFFU

3142

#define LPDDR4__DENALI_PI_177__PI_TVREF_F1_MASK 0x0000FFFFU

3143

#define LPDDR4__DENALI_PI_177__PI_TVREF_F1_SHIFT 0U

3144

#define LPDDR4__DENALI_PI_177__PI_TVREF_F1_WIDTH 16U

3145

#define LPDDR4__PI_TVREF_F1__REG DENALI_PI_177

3146

#define LPDDR4__PI_TVREF_F1__FLD LPDDR4__DENALI_PI_177__PI_TVREF_F1

3147

3148

#define LPDDR4__DENALI_PI_177__PI_TVREF_F2_MASK 0xFFFF0000U

3149

#define LPDDR4__DENALI_PI_177__PI_TVREF_F2_SHIFT 16U

3150

#define LPDDR4__DENALI_PI_177__PI_TVREF_F2_WIDTH 16U

3151

#define LPDDR4__PI_TVREF_F2__REG DENALI_PI_177

3152

#define LPDDR4__PI_TVREF_F2__FLD LPDDR4__DENALI_PI_177__PI_TVREF_F2

3153

3154

#define LPDDR4__DENALI_PI_178_READ_MASK 0x00FFFFFFU

3155

#define LPDDR4__DENALI_PI_178_WRITE_MASK 0x00FFFFFFU

3156

#define LPDDR4__DENALI_PI_178__PI_TSDO_F0_MASK 0x000000FFU

3157

#define LPDDR4__DENALI_PI_178__PI_TSDO_F0_SHIFT 0U

3158

#define LPDDR4__DENALI_PI_178__PI_TSDO_F0_WIDTH 8U

3159

#define LPDDR4__PI_TSDO_F0__REG DENALI_PI_178

3160

#define LPDDR4__PI_TSDO_F0__FLD LPDDR4__DENALI_PI_178__PI_TSDO_F0

3161

3162

#define LPDDR4__DENALI_PI_178__PI_TSDO_F1_MASK 0x0000FF00U

3163

#define LPDDR4__DENALI_PI_178__PI_TSDO_F1_SHIFT 8U

3164

#define LPDDR4__DENALI_PI_178__PI_TSDO_F1_WIDTH 8U

3165

#define LPDDR4__PI_TSDO_F1__REG DENALI_PI_178

3166

#define LPDDR4__PI_TSDO_F1__FLD LPDDR4__DENALI_PI_178__PI_TSDO_F1

3167

3168

#define LPDDR4__DENALI_PI_178__PI_TSDO_F2_MASK 0x00FF0000U

3169

#define LPDDR4__DENALI_PI_178__PI_TSDO_F2_SHIFT 16U

3170

#define LPDDR4__DENALI_PI_178__PI_TSDO_F2_WIDTH 8U

3171

#define LPDDR4__PI_TSDO_F2__REG DENALI_PI_178

3172

#define LPDDR4__PI_TSDO_F2__FLD LPDDR4__DENALI_PI_178__PI_TSDO_F2

3173

3174

#define LPDDR4__DENALI_PI_179_READ_MASK 0x000000FFU

3175

#define LPDDR4__DENALI_PI_179_WRITE_MASK 0x000000FFU

3176

#define LPDDR4__DENALI_PI_179__PI_TDELAY_RDWR_2_BUS_IDLE_F0_MASK 0x000000FFU

3177

#define LPDDR4__DENALI_PI_179__PI_TDELAY_RDWR_2_BUS_IDLE_F0_SHIFT 0U

3178

#define LPDDR4__DENALI_PI_179__PI_TDELAY_RDWR_2_BUS_IDLE_F0_WIDTH 8U

3179

#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F0__REG DENALI_PI_179

3180

#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F0__FLD LPDDR4__DENALI_PI_179__PI_TDELAY_RDWR_2_BUS_IDLE_F0

3181

3182

#define LPDDR4__DENALI_PI_180_READ_MASK 0x000000FFU

3183

#define LPDDR4__DENALI_PI_180_WRITE_MASK 0x000000FFU

3184

#define LPDDR4__DENALI_PI_180__PI_TDELAY_RDWR_2_BUS_IDLE_F1_MASK 0x000000FFU

3185

#define LPDDR4__DENALI_PI_180__PI_TDELAY_RDWR_2_BUS_IDLE_F1_SHIFT 0U

3186

#define LPDDR4__DENALI_PI_180__PI_TDELAY_RDWR_2_BUS_IDLE_F1_WIDTH 8U

3187

#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F1__REG DENALI_PI_180

3188

#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F1__FLD LPDDR4__DENALI_PI_180__PI_TDELAY_RDWR_2_BUS_IDLE_F1

3189

3190

#define LPDDR4__DENALI_PI_181_READ_MASK 0x000FFFFFU

3191

#define LPDDR4__DENALI_PI_181_WRITE_MASK 0x000FFFFFU

3192

#define LPDDR4__DENALI_PI_181__PI_TDELAY_RDWR_2_BUS_IDLE_F2_MASK 0x000000FFU

3193

#define LPDDR4__DENALI_PI_181__PI_TDELAY_RDWR_2_BUS_IDLE_F2_SHIFT 0U

3194

#define LPDDR4__DENALI_PI_181__PI_TDELAY_RDWR_2_BUS_IDLE_F2_WIDTH 8U

3195

#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F2__REG DENALI_PI_181

3196

#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F2__FLD LPDDR4__DENALI_PI_181__PI_TDELAY_RDWR_2_BUS_IDLE_F2

3197

3198

#define LPDDR4__DENALI_PI_181__PI_ZQINIT_F0_MASK 0x000FFF00U

3199

#define LPDDR4__DENALI_PI_181__PI_ZQINIT_F0_SHIFT 8U

3200

#define LPDDR4__DENALI_PI_181__PI_ZQINIT_F0_WIDTH 12U

3201

#define LPDDR4__PI_ZQINIT_F0__REG DENALI_PI_181

3202

#define LPDDR4__PI_ZQINIT_F0__FLD LPDDR4__DENALI_PI_181__PI_ZQINIT_F0

3203

3204

#define LPDDR4__DENALI_PI_182_READ_MASK 0x0FFF0FFFU

3205

#define LPDDR4__DENALI_PI_182_WRITE_MASK 0x0FFF0FFFU

3206

#define LPDDR4__DENALI_PI_182__PI_ZQINIT_F1_MASK 0x00000FFFU

3207

#define LPDDR4__DENALI_PI_182__PI_ZQINIT_F1_SHIFT 0U

3208

#define LPDDR4__DENALI_PI_182__PI_ZQINIT_F1_WIDTH 12U

3209

#define LPDDR4__PI_ZQINIT_F1__REG DENALI_PI_182

3210

#define LPDDR4__PI_ZQINIT_F1__FLD LPDDR4__DENALI_PI_182__PI_ZQINIT_F1

3211

3212

#define LPDDR4__DENALI_PI_182__PI_ZQINIT_F2_MASK 0x0FFF0000U

3213

#define LPDDR4__DENALI_PI_182__PI_ZQINIT_F2_SHIFT 16U

3214

#define LPDDR4__DENALI_PI_182__PI_ZQINIT_F2_WIDTH 12U

3215

#define LPDDR4__PI_ZQINIT_F2__REG DENALI_PI_182

3216

#define LPDDR4__PI_ZQINIT_F2__FLD LPDDR4__DENALI_PI_182__PI_ZQINIT_F2

3217

3218

#define LPDDR4__DENALI_PI_183_READ_MASK 0xFF0F3F7FU

3219

#define LPDDR4__DENALI_PI_183_WRITE_MASK 0xFF0F3F7FU

3220

#define LPDDR4__DENALI_PI_183__PI_WRLAT_F0_MASK 0x0000007FU

3221

#define LPDDR4__DENALI_PI_183__PI_WRLAT_F0_SHIFT 0U

3222

#define LPDDR4__DENALI_PI_183__PI_WRLAT_F0_WIDTH 7U

3223

#define LPDDR4__PI_WRLAT_F0__REG DENALI_PI_183

3224

#define LPDDR4__PI_WRLAT_F0__FLD LPDDR4__DENALI_PI_183__PI_WRLAT_F0

3225

3226

#define LPDDR4__DENALI_PI_183__PI_ADDITIVE_LAT_F0_MASK 0x00003F00U

3227

#define LPDDR4__DENALI_PI_183__PI_ADDITIVE_LAT_F0_SHIFT 8U

3228

#define LPDDR4__DENALI_PI_183__PI_ADDITIVE_LAT_F0_WIDTH 6U

3229

#define LPDDR4__PI_ADDITIVE_LAT_F0__REG DENALI_PI_183

3230

#define LPDDR4__PI_ADDITIVE_LAT_F0__FLD LPDDR4__DENALI_PI_183__PI_ADDITIVE_LAT_F0

3231

3232

#define LPDDR4__DENALI_PI_183__PI_CA_PARITY_LAT_F0_MASK 0x000F0000U

3233

#define LPDDR4__DENALI_PI_183__PI_CA_PARITY_LAT_F0_SHIFT 16U

3234

#define LPDDR4__DENALI_PI_183__PI_CA_PARITY_LAT_F0_WIDTH 4U

3235

#define LPDDR4__PI_CA_PARITY_LAT_F0__REG DENALI_PI_183

3236

#define LPDDR4__PI_CA_PARITY_LAT_F0__FLD LPDDR4__DENALI_PI_183__PI_CA_PARITY_LAT_F0

3237

3238

#define LPDDR4__DENALI_PI_183__PI_TPARITY_ERROR_CMD_INHIBIT_F0_MASK 0xFF000000U

3239

#define LPDDR4__DENALI_PI_183__PI_TPARITY_ERROR_CMD_INHIBIT_F0_SHIFT 24U

3240

#define LPDDR4__DENALI_PI_183__PI_TPARITY_ERROR_CMD_INHIBIT_F0_WIDTH 8U

3241

#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F0__REG DENALI_PI_183

3242

#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F0__FLD LPDDR4__DENALI_PI_183__PI_TPARITY_ERROR_CMD_INHIBIT_F0

3243

3244

#define LPDDR4__DENALI_PI_184_READ_MASK 0x0F3F7F7FU

3245

#define LPDDR4__DENALI_PI_184_WRITE_MASK 0x0F3F7F7FU

3246

#define LPDDR4__DENALI_PI_184__PI_CASLAT_LIN_F0_MASK 0x0000007FU

3247

#define LPDDR4__DENALI_PI_184__PI_CASLAT_LIN_F0_SHIFT 0U

3248

#define LPDDR4__DENALI_PI_184__PI_CASLAT_LIN_F0_WIDTH 7U

3249

#define LPDDR4__PI_CASLAT_LIN_F0__REG DENALI_PI_184

3250

#define LPDDR4__PI_CASLAT_LIN_F0__FLD LPDDR4__DENALI_PI_184__PI_CASLAT_LIN_F0

3251

3252

#define LPDDR4__DENALI_PI_184__PI_WRLAT_F1_MASK 0x00007F00U

3253

#define LPDDR4__DENALI_PI_184__PI_WRLAT_F1_SHIFT 8U

3254

#define LPDDR4__DENALI_PI_184__PI_WRLAT_F1_WIDTH 7U

3255

#define LPDDR4__PI_WRLAT_F1__REG DENALI_PI_184

3256

#define LPDDR4__PI_WRLAT_F1__FLD LPDDR4__DENALI_PI_184__PI_WRLAT_F1

3257

3258

#define LPDDR4__DENALI_PI_184__PI_ADDITIVE_LAT_F1_MASK 0x003F0000U

3259

#define LPDDR4__DENALI_PI_184__PI_ADDITIVE_LAT_F1_SHIFT 16U

3260

#define LPDDR4__DENALI_PI_184__PI_ADDITIVE_LAT_F1_WIDTH 6U

3261

#define LPDDR4__PI_ADDITIVE_LAT_F1__REG DENALI_PI_184

3262

#define LPDDR4__PI_ADDITIVE_LAT_F1__FLD LPDDR4__DENALI_PI_184__PI_ADDITIVE_LAT_F1

3263

3264

#define LPDDR4__DENALI_PI_184__PI_CA_PARITY_LAT_F1_MASK 0x0F000000U

3265

#define LPDDR4__DENALI_PI_184__PI_CA_PARITY_LAT_F1_SHIFT 24U

3266

#define LPDDR4__DENALI_PI_184__PI_CA_PARITY_LAT_F1_WIDTH 4U

3267

#define LPDDR4__PI_CA_PARITY_LAT_F1__REG DENALI_PI_184

3268

#define LPDDR4__PI_CA_PARITY_LAT_F1__FLD LPDDR4__DENALI_PI_184__PI_CA_PARITY_LAT_F1

3269

3270

#define LPDDR4__DENALI_PI_185_READ_MASK 0x3F7F7FFFU

3271

#define LPDDR4__DENALI_PI_185_WRITE_MASK 0x3F7F7FFFU

3272

#define LPDDR4__DENALI_PI_185__PI_TPARITY_ERROR_CMD_INHIBIT_F1_MASK 0x000000FFU

3273

#define LPDDR4__DENALI_PI_185__PI_TPARITY_ERROR_CMD_INHIBIT_F1_SHIFT 0U

3274

#define LPDDR4__DENALI_PI_185__PI_TPARITY_ERROR_CMD_INHIBIT_F1_WIDTH 8U

3275

#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F1__REG DENALI_PI_185

3276

#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F1__FLD LPDDR4__DENALI_PI_185__PI_TPARITY_ERROR_CMD_INHIBIT_F1

3277

3278

#define LPDDR4__DENALI_PI_185__PI_CASLAT_LIN_F1_MASK 0x00007F00U

3279

#define LPDDR4__DENALI_PI_185__PI_CASLAT_LIN_F1_SHIFT 8U

3280

#define LPDDR4__DENALI_PI_185__PI_CASLAT_LIN_F1_WIDTH 7U

3281

#define LPDDR4__PI_CASLAT_LIN_F1__REG DENALI_PI_185

3282

#define LPDDR4__PI_CASLAT_LIN_F1__FLD LPDDR4__DENALI_PI_185__PI_CASLAT_LIN_F1

3283

3284

#define LPDDR4__DENALI_PI_185__PI_WRLAT_F2_MASK 0x007F0000U

3285

#define LPDDR4__DENALI_PI_185__PI_WRLAT_F2_SHIFT 16U

3286

#define LPDDR4__DENALI_PI_185__PI_WRLAT_F2_WIDTH 7U

3287

#define LPDDR4__PI_WRLAT_F2__REG DENALI_PI_185

3288

#define LPDDR4__PI_WRLAT_F2__FLD LPDDR4__DENALI_PI_185__PI_WRLAT_F2

3289

3290

#define LPDDR4__DENALI_PI_185__PI_ADDITIVE_LAT_F2_MASK 0x3F000000U

3291

#define LPDDR4__DENALI_PI_185__PI_ADDITIVE_LAT_F2_SHIFT 24U

3292

#define LPDDR4__DENALI_PI_185__PI_ADDITIVE_LAT_F2_WIDTH 6U

3293

#define LPDDR4__PI_ADDITIVE_LAT_F2__REG DENALI_PI_185

3294

#define LPDDR4__PI_ADDITIVE_LAT_F2__FLD LPDDR4__DENALI_PI_185__PI_ADDITIVE_LAT_F2

3295

3296

#define LPDDR4__DENALI_PI_186_READ_MASK 0x007FFF0FU

3297

#define LPDDR4__DENALI_PI_186_WRITE_MASK 0x007FFF0FU

3298

#define LPDDR4__DENALI_PI_186__PI_CA_PARITY_LAT_F2_MASK 0x0000000FU

3299

#define LPDDR4__DENALI_PI_186__PI_CA_PARITY_LAT_F2_SHIFT 0U

3300

#define LPDDR4__DENALI_PI_186__PI_CA_PARITY_LAT_F2_WIDTH 4U

3301

#define LPDDR4__PI_CA_PARITY_LAT_F2__REG DENALI_PI_186

3302

#define LPDDR4__PI_CA_PARITY_LAT_F2__FLD LPDDR4__DENALI_PI_186__PI_CA_PARITY_LAT_F2

3303

3304

#define LPDDR4__DENALI_PI_186__PI_TPARITY_ERROR_CMD_INHIBIT_F2_MASK 0x0000FF00U

3305

#define LPDDR4__DENALI_PI_186__PI_TPARITY_ERROR_CMD_INHIBIT_F2_SHIFT 8U

3306

#define LPDDR4__DENALI_PI_186__PI_TPARITY_ERROR_CMD_INHIBIT_F2_WIDTH 8U

3307

#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F2__REG DENALI_PI_186

3308

#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F2__FLD LPDDR4__DENALI_PI_186__PI_TPARITY_ERROR_CMD_INHIBIT_F2

3309

3310

#define LPDDR4__DENALI_PI_186__PI_CASLAT_LIN_F2_MASK 0x007F0000U

3311

#define LPDDR4__DENALI_PI_186__PI_CASLAT_LIN_F2_SHIFT 16U

3312

#define LPDDR4__DENALI_PI_186__PI_CASLAT_LIN_F2_WIDTH 7U

3313

#define LPDDR4__PI_CASLAT_LIN_F2__REG DENALI_PI_186

3314

#define LPDDR4__PI_CASLAT_LIN_F2__FLD LPDDR4__DENALI_PI_186__PI_CASLAT_LIN_F2

3315

3316

#define LPDDR4__DENALI_PI_187_READ_MASK 0x000003FFU

3317

#define LPDDR4__DENALI_PI_187_WRITE_MASK 0x000003FFU

3318

#define LPDDR4__DENALI_PI_187__PI_TRFC_F0_MASK 0x000003FFU

3319

#define LPDDR4__DENALI_PI_187__PI_TRFC_F0_SHIFT 0U

3320

#define LPDDR4__DENALI_PI_187__PI_TRFC_F0_WIDTH 10U

3321

#define LPDDR4__PI_TRFC_F0__REG DENALI_PI_187

3322

#define LPDDR4__PI_TRFC_F0__FLD LPDDR4__DENALI_PI_187__PI_TRFC_F0

3323

3324

#define LPDDR4__DENALI_PI_188_READ_MASK 0x000FFFFFU

3325

#define LPDDR4__DENALI_PI_188_WRITE_MASK 0x000FFFFFU

3326

#define LPDDR4__DENALI_PI_188__PI_TREF_F0_MASK 0x000FFFFFU

3327

#define LPDDR4__DENALI_PI_188__PI_TREF_F0_SHIFT 0U

3328

#define LPDDR4__DENALI_PI_188__PI_TREF_F0_WIDTH 20U

3329

#define LPDDR4__PI_TREF_F0__REG DENALI_PI_188

3330

#define LPDDR4__PI_TREF_F0__FLD LPDDR4__DENALI_PI_188__PI_TREF_F0

3331

3332

#define LPDDR4__DENALI_PI_189_READ_MASK 0x000003FFU

3333

#define LPDDR4__DENALI_PI_189_WRITE_MASK 0x000003FFU

3334

#define LPDDR4__DENALI_PI_189__PI_TRFC_F1_MASK 0x000003FFU

3335

#define LPDDR4__DENALI_PI_189__PI_TRFC_F1_SHIFT 0U

3336

#define LPDDR4__DENALI_PI_189__PI_TRFC_F1_WIDTH 10U

3337

#define LPDDR4__PI_TRFC_F1__REG DENALI_PI_189

3338

#define LPDDR4__PI_TRFC_F1__FLD LPDDR4__DENALI_PI_189__PI_TRFC_F1

3339

3340

#define LPDDR4__DENALI_PI_190_READ_MASK 0x000FFFFFU

3341

#define LPDDR4__DENALI_PI_190_WRITE_MASK 0x000FFFFFU

3342

#define LPDDR4__DENALI_PI_190__PI_TREF_F1_MASK 0x000FFFFFU

3343

#define LPDDR4__DENALI_PI_190__PI_TREF_F1_SHIFT 0U

3344

#define LPDDR4__DENALI_PI_190__PI_TREF_F1_WIDTH 20U

3345

#define LPDDR4__PI_TREF_F1__REG DENALI_PI_190

3346

#define LPDDR4__PI_TREF_F1__FLD LPDDR4__DENALI_PI_190__PI_TREF_F1

3347

3348

#define LPDDR4__DENALI_PI_191_READ_MASK 0x000003FFU

3349

#define LPDDR4__DENALI_PI_191_WRITE_MASK 0x000003FFU

3350

#define LPDDR4__DENALI_PI_191__PI_TRFC_F2_MASK 0x000003FFU

3351

#define LPDDR4__DENALI_PI_191__PI_TRFC_F2_SHIFT 0U

3352

#define LPDDR4__DENALI_PI_191__PI_TRFC_F2_WIDTH 10U

3353

#define LPDDR4__PI_TRFC_F2__REG DENALI_PI_191

3354

#define LPDDR4__PI_TRFC_F2__FLD LPDDR4__DENALI_PI_191__PI_TRFC_F2

3355

3356

#define LPDDR4__DENALI_PI_192_READ_MASK 0x0F0FFFFFU

3357

#define LPDDR4__DENALI_PI_192_WRITE_MASK 0x0F0FFFFFU

3358

#define LPDDR4__DENALI_PI_192__PI_TREF_F2_MASK 0x000FFFFFU

3359

#define LPDDR4__DENALI_PI_192__PI_TREF_F2_SHIFT 0U

3360

#define LPDDR4__DENALI_PI_192__PI_TREF_F2_WIDTH 20U

3361

#define LPDDR4__PI_TREF_F2__REG DENALI_PI_192

3362

#define LPDDR4__PI_TREF_F2__FLD LPDDR4__DENALI_PI_192__PI_TREF_F2

3363

3364

#define LPDDR4__DENALI_PI_192__PI_TDFI_CTRL_DELAY_F0_MASK 0x0F000000U

3365

#define LPDDR4__DENALI_PI_192__PI_TDFI_CTRL_DELAY_F0_SHIFT 24U

3366

#define LPDDR4__DENALI_PI_192__PI_TDFI_CTRL_DELAY_F0_WIDTH 4U

3367

#define LPDDR4__PI_TDFI_CTRL_DELAY_F0__REG DENALI_PI_192

3368

#define LPDDR4__PI_TDFI_CTRL_DELAY_F0__FLD LPDDR4__DENALI_PI_192__PI_TDFI_CTRL_DELAY_F0

3369

3370

#define LPDDR4__DENALI_PI_193_READ_MASK 0x03030F0FU

3371

#define LPDDR4__DENALI_PI_193_WRITE_MASK 0x03030F0FU

3372

#define LPDDR4__DENALI_PI_193__PI_TDFI_CTRL_DELAY_F1_MASK 0x0000000FU

3373

#define LPDDR4__DENALI_PI_193__PI_TDFI_CTRL_DELAY_F1_SHIFT 0U

3374

#define LPDDR4__DENALI_PI_193__PI_TDFI_CTRL_DELAY_F1_WIDTH 4U

3375

#define LPDDR4__PI_TDFI_CTRL_DELAY_F1__REG DENALI_PI_193

3376

#define LPDDR4__PI_TDFI_CTRL_DELAY_F1__FLD LPDDR4__DENALI_PI_193__PI_TDFI_CTRL_DELAY_F1

3377

3378

#define LPDDR4__DENALI_PI_193__PI_TDFI_CTRL_DELAY_F2_MASK 0x00000F00U

3379

#define LPDDR4__DENALI_PI_193__PI_TDFI_CTRL_DELAY_F2_SHIFT 8U

3380

#define LPDDR4__DENALI_PI_193__PI_TDFI_CTRL_DELAY_F2_WIDTH 4U

3381

#define LPDDR4__PI_TDFI_CTRL_DELAY_F2__REG DENALI_PI_193

3382

#define LPDDR4__PI_TDFI_CTRL_DELAY_F2__FLD LPDDR4__DENALI_PI_193__PI_TDFI_CTRL_DELAY_F2

3383

3384

#define LPDDR4__DENALI_PI_193__PI_WRLVL_EN_F0_MASK 0x00030000U

3385

#define LPDDR4__DENALI_PI_193__PI_WRLVL_EN_F0_SHIFT 16U

3386

#define LPDDR4__DENALI_PI_193__PI_WRLVL_EN_F0_WIDTH 2U

3387

#define LPDDR4__PI_WRLVL_EN_F0__REG DENALI_PI_193

3388

#define LPDDR4__PI_WRLVL_EN_F0__FLD LPDDR4__DENALI_PI_193__PI_WRLVL_EN_F0

3389

3390

#define LPDDR4__DENALI_PI_193__PI_WRLVL_EN_F1_MASK 0x03000000U

3391

#define LPDDR4__DENALI_PI_193__PI_WRLVL_EN_F1_SHIFT 24U

3392

#define LPDDR4__DENALI_PI_193__PI_WRLVL_EN_F1_WIDTH 2U

3393

#define LPDDR4__PI_WRLVL_EN_F1__REG DENALI_PI_193

3394

#define LPDDR4__PI_WRLVL_EN_F1__FLD LPDDR4__DENALI_PI_193__PI_WRLVL_EN_F1

3395

3396

#define LPDDR4__DENALI_PI_194_READ_MASK 0x0003FF03U

3397

#define LPDDR4__DENALI_PI_194_WRITE_MASK 0x0003FF03U

3398

#define LPDDR4__DENALI_PI_194__PI_WRLVL_EN_F2_MASK 0x00000003U

3399

#define LPDDR4__DENALI_PI_194__PI_WRLVL_EN_F2_SHIFT 0U

3400

#define LPDDR4__DENALI_PI_194__PI_WRLVL_EN_F2_WIDTH 2U

3401

#define LPDDR4__PI_WRLVL_EN_F2__REG DENALI_PI_194

3402

#define LPDDR4__PI_WRLVL_EN_F2__FLD LPDDR4__DENALI_PI_194__PI_WRLVL_EN_F2

3403

3404

#define LPDDR4__DENALI_PI_194__PI_TDFI_WRLVL_WW_F0_MASK 0x0003FF00U

3405

#define LPDDR4__DENALI_PI_194__PI_TDFI_WRLVL_WW_F0_SHIFT 8U

3406

#define LPDDR4__DENALI_PI_194__PI_TDFI_WRLVL_WW_F0_WIDTH 10U

3407

#define LPDDR4__PI_TDFI_WRLVL_WW_F0__REG DENALI_PI_194

3408

#define LPDDR4__PI_TDFI_WRLVL_WW_F0__FLD LPDDR4__DENALI_PI_194__PI_TDFI_WRLVL_WW_F0

3409

3410

#define LPDDR4__DENALI_PI_195_READ_MASK 0x03FF03FFU

3411

#define LPDDR4__DENALI_PI_195_WRITE_MASK 0x03FF03FFU

3412

#define LPDDR4__DENALI_PI_195__PI_TDFI_WRLVL_WW_F1_MASK 0x000003FFU

3413

#define LPDDR4__DENALI_PI_195__PI_TDFI_WRLVL_WW_F1_SHIFT 0U

3414

#define LPDDR4__DENALI_PI_195__PI_TDFI_WRLVL_WW_F1_WIDTH 10U

3415

#define LPDDR4__PI_TDFI_WRLVL_WW_F1__REG DENALI_PI_195

3416

#define LPDDR4__PI_TDFI_WRLVL_WW_F1__FLD LPDDR4__DENALI_PI_195__PI_TDFI_WRLVL_WW_F1

3417

3418

#define LPDDR4__DENALI_PI_195__PI_TDFI_WRLVL_WW_F2_MASK 0x03FF0000U

3419

#define LPDDR4__DENALI_PI_195__PI_TDFI_WRLVL_WW_F2_SHIFT 16U

3420

#define LPDDR4__DENALI_PI_195__PI_TDFI_WRLVL_WW_F2_WIDTH 10U

3421

#define LPDDR4__PI_TDFI_WRLVL_WW_F2__REG DENALI_PI_195

3422

#define LPDDR4__PI_TDFI_WRLVL_WW_F2__FLD LPDDR4__DENALI_PI_195__PI_TDFI_WRLVL_WW_F2

3423

3424

#define LPDDR4__DENALI_PI_196_READ_MASK 0x01FF01FFU

3425

#define LPDDR4__DENALI_PI_196_WRITE_MASK 0x01FF01FFU

3426

#define LPDDR4__DENALI_PI_196__PI_TODTL_2CMD_F0_MASK 0x000000FFU

3427

#define LPDDR4__DENALI_PI_196__PI_TODTL_2CMD_F0_SHIFT 0U

3428

#define LPDDR4__DENALI_PI_196__PI_TODTL_2CMD_F0_WIDTH 8U

3429

#define LPDDR4__PI_TODTL_2CMD_F0__REG DENALI_PI_196

3430

#define LPDDR4__PI_TODTL_2CMD_F0__FLD LPDDR4__DENALI_PI_196__PI_TODTL_2CMD_F0

3431

3432

#define LPDDR4__DENALI_PI_196__PI_ODT_EN_F0_MASK 0x00000100U

3433

#define LPDDR4__DENALI_PI_196__PI_ODT_EN_F0_SHIFT 8U

3434

#define LPDDR4__DENALI_PI_196__PI_ODT_EN_F0_WIDTH 1U

3435

#define LPDDR4__DENALI_PI_196__PI_ODT_EN_F0_WOCLR 0U

3436

#define LPDDR4__DENALI_PI_196__PI_ODT_EN_F0_WOSET 0U

3437

#define LPDDR4__PI_ODT_EN_F0__REG DENALI_PI_196

3438

#define LPDDR4__PI_ODT_EN_F0__FLD LPDDR4__DENALI_PI_196__PI_ODT_EN_F0

3439

3440

#define LPDDR4__DENALI_PI_196__PI_TODTL_2CMD_F1_MASK 0x00FF0000U

3441

#define LPDDR4__DENALI_PI_196__PI_TODTL_2CMD_F1_SHIFT 16U

3442

#define LPDDR4__DENALI_PI_196__PI_TODTL_2CMD_F1_WIDTH 8U

3443

#define LPDDR4__PI_TODTL_2CMD_F1__REG DENALI_PI_196

3444

#define LPDDR4__PI_TODTL_2CMD_F1__FLD LPDDR4__DENALI_PI_196__PI_TODTL_2CMD_F1

3445

3446

#define LPDDR4__DENALI_PI_196__PI_ODT_EN_F1_MASK 0x01000000U

3447

#define LPDDR4__DENALI_PI_196__PI_ODT_EN_F1_SHIFT 24U

3448

#define LPDDR4__DENALI_PI_196__PI_ODT_EN_F1_WIDTH 1U

3449

#define LPDDR4__DENALI_PI_196__PI_ODT_EN_F1_WOCLR 0U

3450

#define LPDDR4__DENALI_PI_196__PI_ODT_EN_F1_WOSET 0U

3451

#define LPDDR4__PI_ODT_EN_F1__REG DENALI_PI_196

3452

#define LPDDR4__PI_ODT_EN_F1__FLD LPDDR4__DENALI_PI_196__PI_ODT_EN_F1

3453

3454

#define LPDDR4__DENALI_PI_197_READ_MASK 0x0F0F01FFU

3455

#define LPDDR4__DENALI_PI_197_WRITE_MASK 0x0F0F01FFU

3456

#define LPDDR4__DENALI_PI_197__PI_TODTL_2CMD_F2_MASK 0x000000FFU

3457

#define LPDDR4__DENALI_PI_197__PI_TODTL_2CMD_F2_SHIFT 0U

3458

#define LPDDR4__DENALI_PI_197__PI_TODTL_2CMD_F2_WIDTH 8U

3459

#define LPDDR4__PI_TODTL_2CMD_F2__REG DENALI_PI_197

3460

#define LPDDR4__PI_TODTL_2CMD_F2__FLD LPDDR4__DENALI_PI_197__PI_TODTL_2CMD_F2

3461

3462

#define LPDDR4__DENALI_PI_197__PI_ODT_EN_F2_MASK 0x00000100U

3463

#define LPDDR4__DENALI_PI_197__PI_ODT_EN_F2_SHIFT 8U

3464

#define LPDDR4__DENALI_PI_197__PI_ODT_EN_F2_WIDTH 1U

3465

#define LPDDR4__DENALI_PI_197__PI_ODT_EN_F2_WOCLR 0U

3466

#define LPDDR4__DENALI_PI_197__PI_ODT_EN_F2_WOSET 0U

3467

#define LPDDR4__PI_ODT_EN_F2__REG DENALI_PI_197

3468

#define LPDDR4__PI_ODT_EN_F2__FLD LPDDR4__DENALI_PI_197__PI_ODT_EN_F2

3469

3470

#define LPDDR4__DENALI_PI_197__PI_ODTLON_F0_MASK 0x000F0000U

3471

#define LPDDR4__DENALI_PI_197__PI_ODTLON_F0_SHIFT 16U

3472

#define LPDDR4__DENALI_PI_197__PI_ODTLON_F0_WIDTH 4U

3473

#define LPDDR4__PI_ODTLON_F0__REG DENALI_PI_197

3474

#define LPDDR4__PI_ODTLON_F0__FLD LPDDR4__DENALI_PI_197__PI_ODTLON_F0

3475

3476

#define LPDDR4__DENALI_PI_197__PI_TODTON_MIN_F0_MASK 0x0F000000U

3477

#define LPDDR4__DENALI_PI_197__PI_TODTON_MIN_F0_SHIFT 24U

3478

#define LPDDR4__DENALI_PI_197__PI_TODTON_MIN_F0_WIDTH 4U

3479

#define LPDDR4__PI_TODTON_MIN_F0__REG DENALI_PI_197

3480

#define LPDDR4__PI_TODTON_MIN_F0__FLD LPDDR4__DENALI_PI_197__PI_TODTON_MIN_F0

3481

3482

#define LPDDR4__DENALI_PI_198_READ_MASK 0x0F0F0F0FU

3483

#define LPDDR4__DENALI_PI_198_WRITE_MASK 0x0F0F0F0FU

3484

#define LPDDR4__DENALI_PI_198__PI_ODTLON_F1_MASK 0x0000000FU

3485

#define LPDDR4__DENALI_PI_198__PI_ODTLON_F1_SHIFT 0U

3486

#define LPDDR4__DENALI_PI_198__PI_ODTLON_F1_WIDTH 4U

3487

#define LPDDR4__PI_ODTLON_F1__REG DENALI_PI_198

3488

#define LPDDR4__PI_ODTLON_F1__FLD LPDDR4__DENALI_PI_198__PI_ODTLON_F1

3489

3490

#define LPDDR4__DENALI_PI_198__PI_TODTON_MIN_F1_MASK 0x00000F00U

3491

#define LPDDR4__DENALI_PI_198__PI_TODTON_MIN_F1_SHIFT 8U

3492

#define LPDDR4__DENALI_PI_198__PI_TODTON_MIN_F1_WIDTH 4U

3493

#define LPDDR4__PI_TODTON_MIN_F1__REG DENALI_PI_198

3494

#define LPDDR4__PI_TODTON_MIN_F1__FLD LPDDR4__DENALI_PI_198__PI_TODTON_MIN_F1

3495

3496

#define LPDDR4__DENALI_PI_198__PI_ODTLON_F2_MASK 0x000F0000U

3497

#define LPDDR4__DENALI_PI_198__PI_ODTLON_F2_SHIFT 16U

3498

#define LPDDR4__DENALI_PI_198__PI_ODTLON_F2_WIDTH 4U

3499

#define LPDDR4__PI_ODTLON_F2__REG DENALI_PI_198

3500

#define LPDDR4__PI_ODTLON_F2__FLD LPDDR4__DENALI_PI_198__PI_ODTLON_F2

3501

3502

#define LPDDR4__DENALI_PI_198__PI_TODTON_MIN_F2_MASK 0x0F000000U

3503

#define LPDDR4__DENALI_PI_198__PI_TODTON_MIN_F2_SHIFT 24U

3504

#define LPDDR4__DENALI_PI_198__PI_TODTON_MIN_F2_WIDTH 4U

3505

#define LPDDR4__PI_TODTON_MIN_F2__REG DENALI_PI_198

3506

#define LPDDR4__PI_TODTON_MIN_F2__FLD LPDDR4__DENALI_PI_198__PI_TODTON_MIN_F2

3507

3508

#define LPDDR4__DENALI_PI_199_READ_MASK 0x3F3F3F3FU

3509

#define LPDDR4__DENALI_PI_199_WRITE_MASK 0x3F3F3F3FU

3510

#define LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F0_MASK 0x0000003FU

3511

#define LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F0_SHIFT 0U

3512

#define LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F0_WIDTH 6U

3513

#define LPDDR4__PI_WR_TO_ODTH_F0__REG DENALI_PI_199

3514

#define LPDDR4__PI_WR_TO_ODTH_F0__FLD LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F0

3515

3516

#define LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F1_MASK 0x00003F00U

3517

#define LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F1_SHIFT 8U

3518

#define LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F1_WIDTH 6U

3519

#define LPDDR4__PI_WR_TO_ODTH_F1__REG DENALI_PI_199

3520

#define LPDDR4__PI_WR_TO_ODTH_F1__FLD LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F1

3521

3522

#define LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F2_MASK 0x003F0000U

3523

#define LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F2_SHIFT 16U

3524

#define LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F2_WIDTH 6U

3525

#define LPDDR4__PI_WR_TO_ODTH_F2__REG DENALI_PI_199

3526

#define LPDDR4__PI_WR_TO_ODTH_F2__FLD LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F2

3527

3528

#define LPDDR4__DENALI_PI_199__PI_RD_TO_ODTH_F0_MASK 0x3F000000U

3529

#define LPDDR4__DENALI_PI_199__PI_RD_TO_ODTH_F0_SHIFT 24U

3530

#define LPDDR4__DENALI_PI_199__PI_RD_TO_ODTH_F0_WIDTH 6U

3531

#define LPDDR4__PI_RD_TO_ODTH_F0__REG DENALI_PI_199

3532

#define LPDDR4__PI_RD_TO_ODTH_F0__FLD LPDDR4__DENALI_PI_199__PI_RD_TO_ODTH_F0

3533

3534

#define LPDDR4__DENALI_PI_200_READ_MASK 0x03033F3FU

3535

#define LPDDR4__DENALI_PI_200_WRITE_MASK 0x03033F3FU

3536

#define LPDDR4__DENALI_PI_200__PI_RD_TO_ODTH_F1_MASK 0x0000003FU

3537

#define LPDDR4__DENALI_PI_200__PI_RD_TO_ODTH_F1_SHIFT 0U

3538

#define LPDDR4__DENALI_PI_200__PI_RD_TO_ODTH_F1_WIDTH 6U

3539

#define LPDDR4__PI_RD_TO_ODTH_F1__REG DENALI_PI_200

3540

#define LPDDR4__PI_RD_TO_ODTH_F1__FLD LPDDR4__DENALI_PI_200__PI_RD_TO_ODTH_F1

3541

3542

#define LPDDR4__DENALI_PI_200__PI_RD_TO_ODTH_F2_MASK 0x00003F00U

3543

#define LPDDR4__DENALI_PI_200__PI_RD_TO_ODTH_F2_SHIFT 8U

3544

#define LPDDR4__DENALI_PI_200__PI_RD_TO_ODTH_F2_WIDTH 6U

3545

#define LPDDR4__PI_RD_TO_ODTH_F2__REG DENALI_PI_200

3546

#define LPDDR4__PI_RD_TO_ODTH_F2__FLD LPDDR4__DENALI_PI_200__PI_RD_TO_ODTH_F2

3547

3548

#define LPDDR4__DENALI_PI_200__PI_RDLVL_EN_F0_MASK 0x00030000U

3549

#define LPDDR4__DENALI_PI_200__PI_RDLVL_EN_F0_SHIFT 16U

3550

#define LPDDR4__DENALI_PI_200__PI_RDLVL_EN_F0_WIDTH 2U

3551

#define LPDDR4__PI_RDLVL_EN_F0__REG DENALI_PI_200

3552

#define LPDDR4__PI_RDLVL_EN_F0__FLD LPDDR4__DENALI_PI_200__PI_RDLVL_EN_F0

3553

3554

#define LPDDR4__DENALI_PI_200__PI_RDLVL_GATE_EN_F0_MASK 0x03000000U

3555

#define LPDDR4__DENALI_PI_200__PI_RDLVL_GATE_EN_F0_SHIFT 24U

3556

#define LPDDR4__DENALI_PI_200__PI_RDLVL_GATE_EN_F0_WIDTH 2U

3557

#define LPDDR4__PI_RDLVL_GATE_EN_F0__REG DENALI_PI_200

3558

#define LPDDR4__PI_RDLVL_GATE_EN_F0__FLD LPDDR4__DENALI_PI_200__PI_RDLVL_GATE_EN_F0

3559

3560

#define LPDDR4__DENALI_PI_201_READ_MASK 0x03030303U

3561

#define LPDDR4__DENALI_PI_201_WRITE_MASK 0x03030303U

3562

#define LPDDR4__DENALI_PI_201__PI_RDLVL_EN_F1_MASK 0x00000003U

3563

#define LPDDR4__DENALI_PI_201__PI_RDLVL_EN_F1_SHIFT 0U

3564

#define LPDDR4__DENALI_PI_201__PI_RDLVL_EN_F1_WIDTH 2U

3565

#define LPDDR4__PI_RDLVL_EN_F1__REG DENALI_PI_201

3566

#define LPDDR4__PI_RDLVL_EN_F1__FLD LPDDR4__DENALI_PI_201__PI_RDLVL_EN_F1

3567

3568

#define LPDDR4__DENALI_PI_201__PI_RDLVL_GATE_EN_F1_MASK 0x00000300U

3569

#define LPDDR4__DENALI_PI_201__PI_RDLVL_GATE_EN_F1_SHIFT 8U

3570

#define LPDDR4__DENALI_PI_201__PI_RDLVL_GATE_EN_F1_WIDTH 2U

3571

#define LPDDR4__PI_RDLVL_GATE_EN_F1__REG DENALI_PI_201

3572

#define LPDDR4__PI_RDLVL_GATE_EN_F1__FLD LPDDR4__DENALI_PI_201__PI_RDLVL_GATE_EN_F1

3573

3574

#define LPDDR4__DENALI_PI_201__PI_RDLVL_EN_F2_MASK 0x00030000U

3575

#define LPDDR4__DENALI_PI_201__PI_RDLVL_EN_F2_SHIFT 16U

3576

#define LPDDR4__DENALI_PI_201__PI_RDLVL_EN_F2_WIDTH 2U

3577

#define LPDDR4__PI_RDLVL_EN_F2__REG DENALI_PI_201

3578

#define LPDDR4__PI_RDLVL_EN_F2__FLD LPDDR4__DENALI_PI_201__PI_RDLVL_EN_F2

3579

3580

#define LPDDR4__DENALI_PI_201__PI_RDLVL_GATE_EN_F2_MASK 0x03000000U

3581

#define LPDDR4__DENALI_PI_201__PI_RDLVL_GATE_EN_F2_SHIFT 24U

3582

#define LPDDR4__DENALI_PI_201__PI_RDLVL_GATE_EN_F2_WIDTH 2U

3583

#define LPDDR4__PI_RDLVL_GATE_EN_F2__REG DENALI_PI_201

3584

#define LPDDR4__PI_RDLVL_GATE_EN_F2__FLD LPDDR4__DENALI_PI_201__PI_RDLVL_GATE_EN_F2

3585

3586

#define LPDDR4__DENALI_PI_202_READ_MASK 0x03FFFFFFU

3587

#define LPDDR4__DENALI_PI_202_WRITE_MASK 0x03FFFFFFU

3588

#define LPDDR4__DENALI_PI_202__PI_TWR_MPR_F0_MASK 0x000000FFU

3589

#define LPDDR4__DENALI_PI_202__PI_TWR_MPR_F0_SHIFT 0U

3590

#define LPDDR4__DENALI_PI_202__PI_TWR_MPR_F0_WIDTH 8U

3591

#define LPDDR4__PI_TWR_MPR_F0__REG DENALI_PI_202

3592

#define LPDDR4__PI_TWR_MPR_F0__FLD LPDDR4__DENALI_PI_202__PI_TWR_MPR_F0

3593

3594

#define LPDDR4__DENALI_PI_202__PI_TWR_MPR_F1_MASK 0x0000FF00U

3595

#define LPDDR4__DENALI_PI_202__PI_TWR_MPR_F1_SHIFT 8U

3596

#define LPDDR4__DENALI_PI_202__PI_TWR_MPR_F1_WIDTH 8U

3597

#define LPDDR4__PI_TWR_MPR_F1__REG DENALI_PI_202

3598

#define LPDDR4__PI_TWR_MPR_F1__FLD LPDDR4__DENALI_PI_202__PI_TWR_MPR_F1

3599

3600

#define LPDDR4__DENALI_PI_202__PI_TWR_MPR_F2_MASK 0x00FF0000U

3601

#define LPDDR4__DENALI_PI_202__PI_TWR_MPR_F2_SHIFT 16U

3602

#define LPDDR4__DENALI_PI_202__PI_TWR_MPR_F2_WIDTH 8U

3603

#define LPDDR4__PI_TWR_MPR_F2__REG DENALI_PI_202

3604

#define LPDDR4__PI_TWR_MPR_F2__FLD LPDDR4__DENALI_PI_202__PI_TWR_MPR_F2

3605

3606

#define LPDDR4__DENALI_PI_202__PI_RDLVL_PAT0_EN_F0_MASK 0x03000000U

3607

#define LPDDR4__DENALI_PI_202__PI_RDLVL_PAT0_EN_F0_SHIFT 24U

3608

#define LPDDR4__DENALI_PI_202__PI_RDLVL_PAT0_EN_F0_WIDTH 2U

3609

#define LPDDR4__PI_RDLVL_PAT0_EN_F0__REG DENALI_PI_202

3610

#define LPDDR4__PI_RDLVL_PAT0_EN_F0__FLD LPDDR4__DENALI_PI_202__PI_RDLVL_PAT0_EN_F0

3611

3612

#define LPDDR4__DENALI_PI_203_READ_MASK 0x03030303U

3613

#define LPDDR4__DENALI_PI_203_WRITE_MASK 0x03030303U

3614

#define LPDDR4__DENALI_PI_203__PI_RDLVL_RXCAL_EN_F0_MASK 0x00000003U

3615

#define LPDDR4__DENALI_PI_203__PI_RDLVL_RXCAL_EN_F0_SHIFT 0U

3616

#define LPDDR4__DENALI_PI_203__PI_RDLVL_RXCAL_EN_F0_WIDTH 2U

3617

#define LPDDR4__PI_RDLVL_RXCAL_EN_F0__REG DENALI_PI_203

3618

#define LPDDR4__PI_RDLVL_RXCAL_EN_F0__FLD LPDDR4__DENALI_PI_203__PI_RDLVL_RXCAL_EN_F0

3619

3620

#define LPDDR4__DENALI_PI_203__PI_RDLVL_DFE_EN_F0_MASK 0x00000300U

3621

#define LPDDR4__DENALI_PI_203__PI_RDLVL_DFE_EN_F0_SHIFT 8U

3622

#define LPDDR4__DENALI_PI_203__PI_RDLVL_DFE_EN_F0_WIDTH 2U

3623

#define LPDDR4__PI_RDLVL_DFE_EN_F0__REG DENALI_PI_203

3624

#define LPDDR4__PI_RDLVL_DFE_EN_F0__FLD LPDDR4__DENALI_PI_203__PI_RDLVL_DFE_EN_F0

3625

3626

#define LPDDR4__DENALI_PI_203__PI_RDLVL_MULTI_EN_F0_MASK 0x00030000U

3627

#define LPDDR4__DENALI_PI_203__PI_RDLVL_MULTI_EN_F0_SHIFT 16U

3628

#define LPDDR4__DENALI_PI_203__PI_RDLVL_MULTI_EN_F0_WIDTH 2U

3629

#define LPDDR4__PI_RDLVL_MULTI_EN_F0__REG DENALI_PI_203

3630

#define LPDDR4__PI_RDLVL_MULTI_EN_F0__FLD LPDDR4__DENALI_PI_203__PI_RDLVL_MULTI_EN_F0

3631

3632

#define LPDDR4__DENALI_PI_203__PI_RDLVL_PAT0_EN_F1_MASK 0x03000000U

3633

#define LPDDR4__DENALI_PI_203__PI_RDLVL_PAT0_EN_F1_SHIFT 24U

3634

#define LPDDR4__DENALI_PI_203__PI_RDLVL_PAT0_EN_F1_WIDTH 2U

3635

#define LPDDR4__PI_RDLVL_PAT0_EN_F1__REG DENALI_PI_203

3636

#define LPDDR4__PI_RDLVL_PAT0_EN_F1__FLD LPDDR4__DENALI_PI_203__PI_RDLVL_PAT0_EN_F1

3637

3638

#define LPDDR4__DENALI_PI_204_READ_MASK 0x03030303U

3639

#define LPDDR4__DENALI_PI_204_WRITE_MASK 0x03030303U

3640

#define LPDDR4__DENALI_PI_204__PI_RDLVL_RXCAL_EN_F1_MASK 0x00000003U

3641

#define LPDDR4__DENALI_PI_204__PI_RDLVL_RXCAL_EN_F1_SHIFT 0U

3642

#define LPDDR4__DENALI_PI_204__PI_RDLVL_RXCAL_EN_F1_WIDTH 2U

3643

#define LPDDR4__PI_RDLVL_RXCAL_EN_F1__REG DENALI_PI_204

3644

#define LPDDR4__PI_RDLVL_RXCAL_EN_F1__FLD LPDDR4__DENALI_PI_204__PI_RDLVL_RXCAL_EN_F1

3645

3646

#define LPDDR4__DENALI_PI_204__PI_RDLVL_DFE_EN_F1_MASK 0x00000300U

3647

#define LPDDR4__DENALI_PI_204__PI_RDLVL_DFE_EN_F1_SHIFT 8U

3648

#define LPDDR4__DENALI_PI_204__PI_RDLVL_DFE_EN_F1_WIDTH 2U

3649

#define LPDDR4__PI_RDLVL_DFE_EN_F1__REG DENALI_PI_204

3650

#define LPDDR4__PI_RDLVL_DFE_EN_F1__FLD LPDDR4__DENALI_PI_204__PI_RDLVL_DFE_EN_F1

3651

3652

#define LPDDR4__DENALI_PI_204__PI_RDLVL_MULTI_EN_F1_MASK 0x00030000U

3653

#define LPDDR4__DENALI_PI_204__PI_RDLVL_MULTI_EN_F1_SHIFT 16U

3654

#define LPDDR4__DENALI_PI_204__PI_RDLVL_MULTI_EN_F1_WIDTH 2U

3655

#define LPDDR4__PI_RDLVL_MULTI_EN_F1__REG DENALI_PI_204

3656

#define LPDDR4__PI_RDLVL_MULTI_EN_F1__FLD LPDDR4__DENALI_PI_204__PI_RDLVL_MULTI_EN_F1

3657

3658

#define LPDDR4__DENALI_PI_204__PI_RDLVL_PAT0_EN_F2_MASK 0x03000000U

3659

#define LPDDR4__DENALI_PI_204__PI_RDLVL_PAT0_EN_F2_SHIFT 24U

3660

#define LPDDR4__DENALI_PI_204__PI_RDLVL_PAT0_EN_F2_WIDTH 2U

3661

#define LPDDR4__PI_RDLVL_PAT0_EN_F2__REG DENALI_PI_204

3662

#define LPDDR4__PI_RDLVL_PAT0_EN_F2__FLD LPDDR4__DENALI_PI_204__PI_RDLVL_PAT0_EN_F2

3663

3664

#define LPDDR4__DENALI_PI_205_READ_MASK 0xFF030303U

3665

#define LPDDR4__DENALI_PI_205_WRITE_MASK 0xFF030303U

3666

#define LPDDR4__DENALI_PI_205__PI_RDLVL_RXCAL_EN_F2_MASK 0x00000003U

3667

#define LPDDR4__DENALI_PI_205__PI_RDLVL_RXCAL_EN_F2_SHIFT 0U

3668

#define LPDDR4__DENALI_PI_205__PI_RDLVL_RXCAL_EN_F2_WIDTH 2U

3669

#define LPDDR4__PI_RDLVL_RXCAL_EN_F2__REG DENALI_PI_205

3670

#define LPDDR4__PI_RDLVL_RXCAL_EN_F2__FLD LPDDR4__DENALI_PI_205__PI_RDLVL_RXCAL_EN_F2

3671

3672

#define LPDDR4__DENALI_PI_205__PI_RDLVL_DFE_EN_F2_MASK 0x00000300U

3673

#define LPDDR4__DENALI_PI_205__PI_RDLVL_DFE_EN_F2_SHIFT 8U

3674

#define LPDDR4__DENALI_PI_205__PI_RDLVL_DFE_EN_F2_WIDTH 2U

3675

#define LPDDR4__PI_RDLVL_DFE_EN_F2__REG DENALI_PI_205

3676

#define LPDDR4__PI_RDLVL_DFE_EN_F2__FLD LPDDR4__DENALI_PI_205__PI_RDLVL_DFE_EN_F2

3677

3678

#define LPDDR4__DENALI_PI_205__PI_RDLVL_MULTI_EN_F2_MASK 0x00030000U

3679

#define LPDDR4__DENALI_PI_205__PI_RDLVL_MULTI_EN_F2_SHIFT 16U

3680

#define LPDDR4__DENALI_PI_205__PI_RDLVL_MULTI_EN_F2_WIDTH 2U

3681

#define LPDDR4__PI_RDLVL_MULTI_EN_F2__REG DENALI_PI_205

3682

#define LPDDR4__PI_RDLVL_MULTI_EN_F2__FLD LPDDR4__DENALI_PI_205__PI_RDLVL_MULTI_EN_F2

3683

3684

#define LPDDR4__DENALI_PI_205__PI_RDLAT_ADJ_F0_MASK 0xFF000000U

3685

#define LPDDR4__DENALI_PI_205__PI_RDLAT_ADJ_F0_SHIFT 24U

3686

#define LPDDR4__DENALI_PI_205__PI_RDLAT_ADJ_F0_WIDTH 8U

3687

#define LPDDR4__PI_RDLAT_ADJ_F0__REG DENALI_PI_205

3688

#define LPDDR4__PI_RDLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_205__PI_RDLAT_ADJ_F0

3689

3690

#define LPDDR4__DENALI_PI_206_READ_MASK 0xFFFFFFFFU

3691

#define LPDDR4__DENALI_PI_206_WRITE_MASK 0xFFFFFFFFU

3692

#define LPDDR4__DENALI_PI_206__PI_RDLAT_ADJ_F1_MASK 0x000000FFU

3693

#define LPDDR4__DENALI_PI_206__PI_RDLAT_ADJ_F1_SHIFT 0U

3694

#define LPDDR4__DENALI_PI_206__PI_RDLAT_ADJ_F1_WIDTH 8U

3695

#define LPDDR4__PI_RDLAT_ADJ_F1__REG DENALI_PI_206

3696

#define LPDDR4__PI_RDLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_206__PI_RDLAT_ADJ_F1

3697

3698

#define LPDDR4__DENALI_PI_206__PI_RDLAT_ADJ_F2_MASK 0x0000FF00U

3699

#define LPDDR4__DENALI_PI_206__PI_RDLAT_ADJ_F2_SHIFT 8U

3700

#define LPDDR4__DENALI_PI_206__PI_RDLAT_ADJ_F2_WIDTH 8U

3701

#define LPDDR4__PI_RDLAT_ADJ_F2__REG DENALI_PI_206

3702

#define LPDDR4__PI_RDLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_206__PI_RDLAT_ADJ_F2

3703

3704

#define LPDDR4__DENALI_PI_206__PI_WRLAT_ADJ_F0_MASK 0x00FF0000U

3705

#define LPDDR4__DENALI_PI_206__PI_WRLAT_ADJ_F0_SHIFT 16U

3706

#define LPDDR4__DENALI_PI_206__PI_WRLAT_ADJ_F0_WIDTH 8U

3707

#define LPDDR4__PI_WRLAT_ADJ_F0__REG DENALI_PI_206

3708

#define LPDDR4__PI_WRLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_206__PI_WRLAT_ADJ_F0

3709

3710

#define LPDDR4__DENALI_PI_206__PI_WRLAT_ADJ_F1_MASK 0xFF000000U

3711

#define LPDDR4__DENALI_PI_206__PI_WRLAT_ADJ_F1_SHIFT 24U

3712

#define LPDDR4__DENALI_PI_206__PI_WRLAT_ADJ_F1_WIDTH 8U

3713

#define LPDDR4__PI_WRLAT_ADJ_F1__REG DENALI_PI_206

3714

#define LPDDR4__PI_WRLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_206__PI_WRLAT_ADJ_F1

3715

3716

#define LPDDR4__DENALI_PI_207_READ_MASK 0x070707FFU

3717

#define LPDDR4__DENALI_PI_207_WRITE_MASK 0x070707FFU

3718

#define LPDDR4__DENALI_PI_207__PI_WRLAT_ADJ_F2_MASK 0x000000FFU

3719

#define LPDDR4__DENALI_PI_207__PI_WRLAT_ADJ_F2_SHIFT 0U

3720

#define LPDDR4__DENALI_PI_207__PI_WRLAT_ADJ_F2_WIDTH 8U

3721

#define LPDDR4__PI_WRLAT_ADJ_F2__REG DENALI_PI_207

3722

#define LPDDR4__PI_WRLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_207__PI_WRLAT_ADJ_F2

3723

3724

#define LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F0_MASK 0x00000700U

3725

#define LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F0_SHIFT 8U

3726

#define LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F0_WIDTH 3U

3727

#define LPDDR4__PI_TDFI_PHY_WRDATA_F0__REG DENALI_PI_207

3728

#define LPDDR4__PI_TDFI_PHY_WRDATA_F0__FLD LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F0

3729

3730

#define LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F1_MASK 0x00070000U

3731

#define LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F1_SHIFT 16U

3732

#define LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F1_WIDTH 3U

3733

#define LPDDR4__PI_TDFI_PHY_WRDATA_F1__REG DENALI_PI_207

3734

#define LPDDR4__PI_TDFI_PHY_WRDATA_F1__FLD LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F1

3735

3736

#define LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F2_MASK 0x07000000U

3737

#define LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F2_SHIFT 24U

3738

#define LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F2_WIDTH 3U

3739

#define LPDDR4__PI_TDFI_PHY_WRDATA_F2__REG DENALI_PI_207

3740

#define LPDDR4__PI_TDFI_PHY_WRDATA_F2__FLD LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F2

3741

3742

#define LPDDR4__DENALI_PI_208_READ_MASK 0x03FF03FFU

3743

#define LPDDR4__DENALI_PI_208_WRITE_MASK 0x03FF03FFU

3744

#define LPDDR4__DENALI_PI_208__PI_TDFI_CALVL_CC_F0_MASK 0x000003FFU

3745

#define LPDDR4__DENALI_PI_208__PI_TDFI_CALVL_CC_F0_SHIFT 0U

3746

#define LPDDR4__DENALI_PI_208__PI_TDFI_CALVL_CC_F0_WIDTH 10U

3747

#define LPDDR4__PI_TDFI_CALVL_CC_F0__REG DENALI_PI_208

3748

#define LPDDR4__PI_TDFI_CALVL_CC_F0__FLD LPDDR4__DENALI_PI_208__PI_TDFI_CALVL_CC_F0

3749

3750

#define LPDDR4__DENALI_PI_208__PI_TDFI_CALVL_CAPTURE_F0_MASK 0x03FF0000U

3751

#define LPDDR4__DENALI_PI_208__PI_TDFI_CALVL_CAPTURE_F0_SHIFT 16U

3752

#define LPDDR4__DENALI_PI_208__PI_TDFI_CALVL_CAPTURE_F0_WIDTH 10U

3753

#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F0__REG DENALI_PI_208

3754

#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F0__FLD LPDDR4__DENALI_PI_208__PI_TDFI_CALVL_CAPTURE_F0

3755

3756

#define LPDDR4__DENALI_PI_209_READ_MASK 0x03FF03FFU

3757

#define LPDDR4__DENALI_PI_209_WRITE_MASK 0x03FF03FFU

3758

#define LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_CC_F1_MASK 0x000003FFU

3759

#define LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_CC_F1_SHIFT 0U

3760

#define LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_CC_F1_WIDTH 10U

3761

#define LPDDR4__PI_TDFI_CALVL_CC_F1__REG DENALI_PI_209

3762

#define LPDDR4__PI_TDFI_CALVL_CC_F1__FLD LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_CC_F1

3763

3764

#define LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_CAPTURE_F1_MASK 0x03FF0000U

3765

#define LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_CAPTURE_F1_SHIFT 16U

3766

#define LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_CAPTURE_F1_WIDTH 10U

3767

#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F1__REG DENALI_PI_209

3768

#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F1__FLD LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_CAPTURE_F1

3769

3770

#define LPDDR4__DENALI_PI_210_READ_MASK 0x03FF03FFU

3771

#define LPDDR4__DENALI_PI_210_WRITE_MASK 0x03FF03FFU

3772

#define LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_CC_F2_MASK 0x000003FFU

3773

#define LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_CC_F2_SHIFT 0U

3774

#define LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_CC_F2_WIDTH 10U

3775

#define LPDDR4__PI_TDFI_CALVL_CC_F2__REG DENALI_PI_210

3776

#define LPDDR4__PI_TDFI_CALVL_CC_F2__FLD LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_CC_F2

3777

3778

#define LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_CAPTURE_F2_MASK 0x03FF0000U

3779

#define LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_CAPTURE_F2_SHIFT 16U

3780

#define LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_CAPTURE_F2_WIDTH 10U

3781

#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F2__REG DENALI_PI_210

3782

#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F2__FLD LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_CAPTURE_F2

3783

3784

#define LPDDR4__DENALI_PI_211_READ_MASK 0x1F030303U

3785

#define LPDDR4__DENALI_PI_211_WRITE_MASK 0x1F030303U

3786

#define LPDDR4__DENALI_PI_211__PI_CALVL_EN_F0_MASK 0x00000003U

3787

#define LPDDR4__DENALI_PI_211__PI_CALVL_EN_F0_SHIFT 0U

3788

#define LPDDR4__DENALI_PI_211__PI_CALVL_EN_F0_WIDTH 2U

3789

#define LPDDR4__PI_CALVL_EN_F0__REG DENALI_PI_211

3790

#define LPDDR4__PI_CALVL_EN_F0__FLD LPDDR4__DENALI_PI_211__PI_CALVL_EN_F0

3791

3792

#define LPDDR4__DENALI_PI_211__PI_CALVL_EN_F1_MASK 0x00000300U

3793

#define LPDDR4__DENALI_PI_211__PI_CALVL_EN_F1_SHIFT 8U

3794

#define LPDDR4__DENALI_PI_211__PI_CALVL_EN_F1_WIDTH 2U

3795

#define LPDDR4__PI_CALVL_EN_F1__REG DENALI_PI_211

3796

#define LPDDR4__PI_CALVL_EN_F1__FLD LPDDR4__DENALI_PI_211__PI_CALVL_EN_F1

3797

3798

#define LPDDR4__DENALI_PI_211__PI_CALVL_EN_F2_MASK 0x00030000U

3799

#define LPDDR4__DENALI_PI_211__PI_CALVL_EN_F2_SHIFT 16U

3800

#define LPDDR4__DENALI_PI_211__PI_CALVL_EN_F2_WIDTH 2U

3801

#define LPDDR4__PI_CALVL_EN_F2__REG DENALI_PI_211

3802

#define LPDDR4__PI_CALVL_EN_F2__FLD LPDDR4__DENALI_PI_211__PI_CALVL_EN_F2

3803

3804

#define LPDDR4__DENALI_PI_211__PI_TMRZ_F0_MASK 0x1F000000U

3805

#define LPDDR4__DENALI_PI_211__PI_TMRZ_F0_SHIFT 24U

3806

#define LPDDR4__DENALI_PI_211__PI_TMRZ_F0_WIDTH 5U

3807

#define LPDDR4__PI_TMRZ_F0__REG DENALI_PI_211

3808

#define LPDDR4__PI_TMRZ_F0__FLD LPDDR4__DENALI_PI_211__PI_TMRZ_F0

3809

3810

#define LPDDR4__DENALI_PI_212_READ_MASK 0x001F3FFFU

3811

#define LPDDR4__DENALI_PI_212_WRITE_MASK 0x001F3FFFU

3812

#define LPDDR4__DENALI_PI_212__PI_TCAENT_F0_MASK 0x00003FFFU

3813

#define LPDDR4__DENALI_PI_212__PI_TCAENT_F0_SHIFT 0U

3814

#define LPDDR4__DENALI_PI_212__PI_TCAENT_F0_WIDTH 14U

3815

#define LPDDR4__PI_TCAENT_F0__REG DENALI_PI_212

3816

#define LPDDR4__PI_TCAENT_F0__FLD LPDDR4__DENALI_PI_212__PI_TCAENT_F0

3817

3818

#define LPDDR4__DENALI_PI_212__PI_TMRZ_F1_MASK 0x001F0000U

3819

#define LPDDR4__DENALI_PI_212__PI_TMRZ_F1_SHIFT 16U

3820

#define LPDDR4__DENALI_PI_212__PI_TMRZ_F1_WIDTH 5U

3821

#define LPDDR4__PI_TMRZ_F1__REG DENALI_PI_212

3822

#define LPDDR4__PI_TMRZ_F1__FLD LPDDR4__DENALI_PI_212__PI_TMRZ_F1

3823

3824

#define LPDDR4__DENALI_PI_213_READ_MASK 0x001F3FFFU

3825

#define LPDDR4__DENALI_PI_213_WRITE_MASK 0x001F3FFFU

3826

#define LPDDR4__DENALI_PI_213__PI_TCAENT_F1_MASK 0x00003FFFU

3827

#define LPDDR4__DENALI_PI_213__PI_TCAENT_F1_SHIFT 0U

3828

#define LPDDR4__DENALI_PI_213__PI_TCAENT_F1_WIDTH 14U

3829

#define LPDDR4__PI_TCAENT_F1__REG DENALI_PI_213

3830

#define LPDDR4__PI_TCAENT_F1__FLD LPDDR4__DENALI_PI_213__PI_TCAENT_F1

3831

3832

#define LPDDR4__DENALI_PI_213__PI_TMRZ_F2_MASK 0x001F0000U

3833

#define LPDDR4__DENALI_PI_213__PI_TMRZ_F2_SHIFT 16U

3834

#define LPDDR4__DENALI_PI_213__PI_TMRZ_F2_WIDTH 5U

3835

#define LPDDR4__PI_TMRZ_F2__REG DENALI_PI_213

3836

#define LPDDR4__PI_TMRZ_F2__FLD LPDDR4__DENALI_PI_213__PI_TMRZ_F2

3837

3838

#define LPDDR4__DENALI_PI_214_READ_MASK 0x1F1F3FFFU

3839

#define LPDDR4__DENALI_PI_214_WRITE_MASK 0x1F1F3FFFU

3840

#define LPDDR4__DENALI_PI_214__PI_TCAENT_F2_MASK 0x00003FFFU

3841

#define LPDDR4__DENALI_PI_214__PI_TCAENT_F2_SHIFT 0U

3842

#define LPDDR4__DENALI_PI_214__PI_TCAENT_F2_WIDTH 14U

3843

#define LPDDR4__PI_TCAENT_F2__REG DENALI_PI_214

3844

#define LPDDR4__PI_TCAENT_F2__FLD LPDDR4__DENALI_PI_214__PI_TCAENT_F2

3845

3846

#define LPDDR4__DENALI_PI_214__PI_TDFI_CACSCA_F0_MASK 0x001F0000U

3847

#define LPDDR4__DENALI_PI_214__PI_TDFI_CACSCA_F0_SHIFT 16U

3848

#define LPDDR4__DENALI_PI_214__PI_TDFI_CACSCA_F0_WIDTH 5U

3849

#define LPDDR4__PI_TDFI_CACSCA_F0__REG DENALI_PI_214

3850

#define LPDDR4__PI_TDFI_CACSCA_F0__FLD LPDDR4__DENALI_PI_214__PI_TDFI_CACSCA_F0

3851

3852

#define LPDDR4__DENALI_PI_214__PI_TDFI_CASEL_F0_MASK 0x1F000000U

3853

#define LPDDR4__DENALI_PI_214__PI_TDFI_CASEL_F0_SHIFT 24U

3854

#define LPDDR4__DENALI_PI_214__PI_TDFI_CASEL_F0_WIDTH 5U

3855

#define LPDDR4__PI_TDFI_CASEL_F0__REG DENALI_PI_214

3856

#define LPDDR4__PI_TDFI_CASEL_F0__FLD LPDDR4__DENALI_PI_214__PI_TDFI_CASEL_F0

3857

3858

#define LPDDR4__DENALI_PI_215_READ_MASK 0x03FF03FFU

3859

#define LPDDR4__DENALI_PI_215_WRITE_MASK 0x03FF03FFU

3860

#define LPDDR4__DENALI_PI_215__PI_TVREF_SHORT_F0_MASK 0x000003FFU

3861

#define LPDDR4__DENALI_PI_215__PI_TVREF_SHORT_F0_SHIFT 0U

3862

#define LPDDR4__DENALI_PI_215__PI_TVREF_SHORT_F0_WIDTH 10U

3863

#define LPDDR4__PI_TVREF_SHORT_F0__REG DENALI_PI_215

3864

#define LPDDR4__PI_TVREF_SHORT_F0__FLD LPDDR4__DENALI_PI_215__PI_TVREF_SHORT_F0

3865

3866

#define LPDDR4__DENALI_PI_215__PI_TVREF_LONG_F0_MASK 0x03FF0000U

3867

#define LPDDR4__DENALI_PI_215__PI_TVREF_LONG_F0_SHIFT 16U

3868

#define LPDDR4__DENALI_PI_215__PI_TVREF_LONG_F0_WIDTH 10U

3869

#define LPDDR4__PI_TVREF_LONG_F0__REG DENALI_PI_215

3870

#define LPDDR4__PI_TVREF_LONG_F0__FLD LPDDR4__DENALI_PI_215__PI_TVREF_LONG_F0

3871

3872

#define LPDDR4__DENALI_PI_216_READ_MASK 0x03FF1F1FU

3873

#define LPDDR4__DENALI_PI_216_WRITE_MASK 0x03FF1F1FU

3874

#define LPDDR4__DENALI_PI_216__PI_TDFI_CACSCA_F1_MASK 0x0000001FU

3875

#define LPDDR4__DENALI_PI_216__PI_TDFI_CACSCA_F1_SHIFT 0U

3876

#define LPDDR4__DENALI_PI_216__PI_TDFI_CACSCA_F1_WIDTH 5U

3877

#define LPDDR4__PI_TDFI_CACSCA_F1__REG DENALI_PI_216

3878

#define LPDDR4__PI_TDFI_CACSCA_F1__FLD LPDDR4__DENALI_PI_216__PI_TDFI_CACSCA_F1

3879

3880

#define LPDDR4__DENALI_PI_216__PI_TDFI_CASEL_F1_MASK 0x00001F00U

3881

#define LPDDR4__DENALI_PI_216__PI_TDFI_CASEL_F1_SHIFT 8U

3882

#define LPDDR4__DENALI_PI_216__PI_TDFI_CASEL_F1_WIDTH 5U

3883

#define LPDDR4__PI_TDFI_CASEL_F1__REG DENALI_PI_216

3884

#define LPDDR4__PI_TDFI_CASEL_F1__FLD LPDDR4__DENALI_PI_216__PI_TDFI_CASEL_F1

3885

3886

#define LPDDR4__DENALI_PI_216__PI_TVREF_SHORT_F1_MASK 0x03FF0000U

3887

#define LPDDR4__DENALI_PI_216__PI_TVREF_SHORT_F1_SHIFT 16U

3888

#define LPDDR4__DENALI_PI_216__PI_TVREF_SHORT_F1_WIDTH 10U

3889

#define LPDDR4__PI_TVREF_SHORT_F1__REG DENALI_PI_216

3890

#define LPDDR4__PI_TVREF_SHORT_F1__FLD LPDDR4__DENALI_PI_216__PI_TVREF_SHORT_F1

3891

3892

#define LPDDR4__DENALI_PI_217_READ_MASK 0x1F1F03FFU

3893

#define LPDDR4__DENALI_PI_217_WRITE_MASK 0x1F1F03FFU

3894

#define LPDDR4__DENALI_PI_217__PI_TVREF_LONG_F1_MASK 0x000003FFU

3895

#define LPDDR4__DENALI_PI_217__PI_TVREF_LONG_F1_SHIFT 0U

3896

#define LPDDR4__DENALI_PI_217__PI_TVREF_LONG_F1_WIDTH 10U

3897

#define LPDDR4__PI_TVREF_LONG_F1__REG DENALI_PI_217

3898

#define LPDDR4__PI_TVREF_LONG_F1__FLD LPDDR4__DENALI_PI_217__PI_TVREF_LONG_F1

3899

3900

#define LPDDR4__DENALI_PI_217__PI_TDFI_CACSCA_F2_MASK 0x001F0000U

3901

#define LPDDR4__DENALI_PI_217__PI_TDFI_CACSCA_F2_SHIFT 16U

3902

#define LPDDR4__DENALI_PI_217__PI_TDFI_CACSCA_F2_WIDTH 5U

3903

#define LPDDR4__PI_TDFI_CACSCA_F2__REG DENALI_PI_217

3904

#define LPDDR4__PI_TDFI_CACSCA_F2__FLD LPDDR4__DENALI_PI_217__PI_TDFI_CACSCA_F2

3905

3906

#define LPDDR4__DENALI_PI_217__PI_TDFI_CASEL_F2_MASK 0x1F000000U

3907

#define LPDDR4__DENALI_PI_217__PI_TDFI_CASEL_F2_SHIFT 24U

3908

#define LPDDR4__DENALI_PI_217__PI_TDFI_CASEL_F2_WIDTH 5U

3909

#define LPDDR4__PI_TDFI_CASEL_F2__REG DENALI_PI_217

3910

#define LPDDR4__PI_TDFI_CASEL_F2__FLD LPDDR4__DENALI_PI_217__PI_TDFI_CASEL_F2

3911

3912

#define LPDDR4__DENALI_PI_218_READ_MASK 0x03FF03FFU

3913

#define LPDDR4__DENALI_PI_218_WRITE_MASK 0x03FF03FFU

3914

#define LPDDR4__DENALI_PI_218__PI_TVREF_SHORT_F2_MASK 0x000003FFU

3915

#define LPDDR4__DENALI_PI_218__PI_TVREF_SHORT_F2_SHIFT 0U

3916

#define LPDDR4__DENALI_PI_218__PI_TVREF_SHORT_F2_WIDTH 10U

3917

#define LPDDR4__PI_TVREF_SHORT_F2__REG DENALI_PI_218

3918

#define LPDDR4__PI_TVREF_SHORT_F2__FLD LPDDR4__DENALI_PI_218__PI_TVREF_SHORT_F2

3919

3920

#define LPDDR4__DENALI_PI_218__PI_TVREF_LONG_F2_MASK 0x03FF0000U

3921

#define LPDDR4__DENALI_PI_218__PI_TVREF_LONG_F2_SHIFT 16U

3922

#define LPDDR4__DENALI_PI_218__PI_TVREF_LONG_F2_WIDTH 10U

3923

#define LPDDR4__PI_TVREF_LONG_F2__REG DENALI_PI_218

3924

#define LPDDR4__PI_TVREF_LONG_F2__FLD LPDDR4__DENALI_PI_218__PI_TVREF_LONG_F2

3925

3926

#define LPDDR4__DENALI_PI_219_READ_MASK 0x7F7F7F7FU

3927

#define LPDDR4__DENALI_PI_219_WRITE_MASK 0x7F7F7F7FU

3928

#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_START_POINT_F0_MASK 0x0000007FU

3929

#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_START_POINT_F0_SHIFT 0U

3930

#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_START_POINT_F0_WIDTH 7U

3931

#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F0__REG DENALI_PI_219

3932

#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F0__FLD LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_START_POINT_F0

3933

3934

#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_MASK 0x00007F00U

3935

#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_SHIFT 8U

3936

#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_WIDTH 7U

3937

#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F0__REG DENALI_PI_219

3938

#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F0__FLD LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_STOP_POINT_F0

3939

3940

#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_START_POINT_F1_MASK 0x007F0000U

3941

#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_START_POINT_F1_SHIFT 16U

3942

#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_START_POINT_F1_WIDTH 7U

3943

#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F1__REG DENALI_PI_219

3944

#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F1__FLD LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_START_POINT_F1

3945

3946

#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_MASK 0x7F000000U

3947

#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_SHIFT 24U

3948

#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_WIDTH 7U

3949

#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F1__REG DENALI_PI_219

3950

#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F1__FLD LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_STOP_POINT_F1

3951

3952

#define LPDDR4__DENALI_PI_220_READ_MASK 0x0F0F7F7FU

3953

#define LPDDR4__DENALI_PI_220_WRITE_MASK 0x0F0F7F7FU

3954

#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_INITIAL_START_POINT_F2_MASK 0x0000007FU

3955

#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_INITIAL_START_POINT_F2_SHIFT 0U

3956

#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_INITIAL_START_POINT_F2_WIDTH 7U

3957

#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F2__REG DENALI_PI_220

3958

#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F2__FLD LPDDR4__DENALI_PI_220__PI_CALVL_VREF_INITIAL_START_POINT_F2

3959

3960

#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_MASK 0x00007F00U

3961

#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_SHIFT 8U

3962

#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_WIDTH 7U

3963

#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F2__REG DENALI_PI_220

3964

#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F2__FLD LPDDR4__DENALI_PI_220__PI_CALVL_VREF_INITIAL_STOP_POINT_F2

3965

3966

#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_DELTA_F0_MASK 0x000F0000U

3967

#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_DELTA_F0_SHIFT 16U

3968

#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_DELTA_F0_WIDTH 4U

3969

#define LPDDR4__PI_CALVL_VREF_DELTA_F0__REG DENALI_PI_220

3970

#define LPDDR4__PI_CALVL_VREF_DELTA_F0__FLD LPDDR4__DENALI_PI_220__PI_CALVL_VREF_DELTA_F0

3971

3972

#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_DELTA_F1_MASK 0x0F000000U

3973

#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_DELTA_F1_SHIFT 24U

3974

#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_DELTA_F1_WIDTH 4U

3975

#define LPDDR4__PI_CALVL_VREF_DELTA_F1__REG DENALI_PI_220

3976

#define LPDDR4__PI_CALVL_VREF_DELTA_F1__FLD LPDDR4__DENALI_PI_220__PI_CALVL_VREF_DELTA_F1

3977

3978

#define LPDDR4__DENALI_PI_221_READ_MASK 0xFF1F0F0FU

3979

#define LPDDR4__DENALI_PI_221_WRITE_MASK 0xFF1F0F0FU

3980

#define LPDDR4__DENALI_PI_221__PI_CALVL_VREF_DELTA_F2_MASK 0x0000000FU

3981

#define LPDDR4__DENALI_PI_221__PI_CALVL_VREF_DELTA_F2_SHIFT 0U

3982

#define LPDDR4__DENALI_PI_221__PI_CALVL_VREF_DELTA_F2_WIDTH 4U

3983

#define LPDDR4__PI_CALVL_VREF_DELTA_F2__REG DENALI_PI_221

3984

#define LPDDR4__PI_CALVL_VREF_DELTA_F2__FLD LPDDR4__DENALI_PI_221__PI_CALVL_VREF_DELTA_F2

3985

3986

#define LPDDR4__DENALI_PI_221__PI_TDFI_CALVL_STROBE_F0_MASK 0x00000F00U

3987

#define LPDDR4__DENALI_PI_221__PI_TDFI_CALVL_STROBE_F0_SHIFT 8U

3988

#define LPDDR4__DENALI_PI_221__PI_TDFI_CALVL_STROBE_F0_WIDTH 4U

3989

#define LPDDR4__PI_TDFI_CALVL_STROBE_F0__REG DENALI_PI_221

3990

#define LPDDR4__PI_TDFI_CALVL_STROBE_F0__FLD LPDDR4__DENALI_PI_221__PI_TDFI_CALVL_STROBE_F0

3991

3992

#define LPDDR4__DENALI_PI_221__PI_TXP_F0_MASK 0x001F0000U

3993

#define LPDDR4__DENALI_PI_221__PI_TXP_F0_SHIFT 16U

3994

#define LPDDR4__DENALI_PI_221__PI_TXP_F0_WIDTH 5U

3995

#define LPDDR4__PI_TXP_F0__REG DENALI_PI_221

3996

#define LPDDR4__PI_TXP_F0__FLD LPDDR4__DENALI_PI_221__PI_TXP_F0

3997

3998

#define LPDDR4__DENALI_PI_221__PI_TMRWCKEL_F0_MASK 0xFF000000U

3999

#define LPDDR4__DENALI_PI_221__PI_TMRWCKEL_F0_SHIFT 24U

4000

#define LPDDR4__DENALI_PI_221__PI_TMRWCKEL_F0_WIDTH 8U

4001

#define LPDDR4__PI_TMRWCKEL_F0__REG DENALI_PI_221

4002

#define LPDDR4__PI_TMRWCKEL_F0__FLD LPDDR4__DENALI_PI_221__PI_TMRWCKEL_F0

4003

4004

#define LPDDR4__DENALI_PI_222_READ_MASK 0xFF1F0F1FU

4005

#define LPDDR4__DENALI_PI_222_WRITE_MASK 0xFF1F0F1FU

4006

#define LPDDR4__DENALI_PI_222__PI_TCKELCK_F0_MASK 0x0000001FU

4007

#define LPDDR4__DENALI_PI_222__PI_TCKELCK_F0_SHIFT 0U

4008

#define LPDDR4__DENALI_PI_222__PI_TCKELCK_F0_WIDTH 5U

4009

#define LPDDR4__PI_TCKELCK_F0__REG DENALI_PI_222

4010

#define LPDDR4__PI_TCKELCK_F0__FLD LPDDR4__DENALI_PI_222__PI_TCKELCK_F0

4011

4012

#define LPDDR4__DENALI_PI_222__PI_TDFI_CALVL_STROBE_F1_MASK 0x00000F00U

4013

#define LPDDR4__DENALI_PI_222__PI_TDFI_CALVL_STROBE_F1_SHIFT 8U

4014

#define LPDDR4__DENALI_PI_222__PI_TDFI_CALVL_STROBE_F1_WIDTH 4U

4015

#define LPDDR4__PI_TDFI_CALVL_STROBE_F1__REG DENALI_PI_222

4016

#define LPDDR4__PI_TDFI_CALVL_STROBE_F1__FLD LPDDR4__DENALI_PI_222__PI_TDFI_CALVL_STROBE_F1

4017

4018

#define LPDDR4__DENALI_PI_222__PI_TXP_F1_MASK 0x001F0000U

4019

#define LPDDR4__DENALI_PI_222__PI_TXP_F1_SHIFT 16U

4020

#define LPDDR4__DENALI_PI_222__PI_TXP_F1_WIDTH 5U

4021

#define LPDDR4__PI_TXP_F1__REG DENALI_PI_222

4022

#define LPDDR4__PI_TXP_F1__FLD LPDDR4__DENALI_PI_222__PI_TXP_F1

4023

4024

#define LPDDR4__DENALI_PI_222__PI_TMRWCKEL_F1_MASK 0xFF000000U

4025

#define LPDDR4__DENALI_PI_222__PI_TMRWCKEL_F1_SHIFT 24U

4026

#define LPDDR4__DENALI_PI_222__PI_TMRWCKEL_F1_WIDTH 8U

4027

#define LPDDR4__PI_TMRWCKEL_F1__REG DENALI_PI_222

4028

#define LPDDR4__PI_TMRWCKEL_F1__FLD LPDDR4__DENALI_PI_222__PI_TMRWCKEL_F1

4029

4030

#define LPDDR4__DENALI_PI_223_READ_MASK 0xFF1F0F1FU

4031

#define LPDDR4__DENALI_PI_223_WRITE_MASK 0xFF1F0F1FU

4032

#define LPDDR4__DENALI_PI_223__PI_TCKELCK_F1_MASK 0x0000001FU

4033

#define LPDDR4__DENALI_PI_223__PI_TCKELCK_F1_SHIFT 0U

4034

#define LPDDR4__DENALI_PI_223__PI_TCKELCK_F1_WIDTH 5U

4035

#define LPDDR4__PI_TCKELCK_F1__REG DENALI_PI_223

4036

#define LPDDR4__PI_TCKELCK_F1__FLD LPDDR4__DENALI_PI_223__PI_TCKELCK_F1

4037

4038

#define LPDDR4__DENALI_PI_223__PI_TDFI_CALVL_STROBE_F2_MASK 0x00000F00U

4039

#define LPDDR4__DENALI_PI_223__PI_TDFI_CALVL_STROBE_F2_SHIFT 8U

4040

#define LPDDR4__DENALI_PI_223__PI_TDFI_CALVL_STROBE_F2_WIDTH 4U

4041

#define LPDDR4__PI_TDFI_CALVL_STROBE_F2__REG DENALI_PI_223

4042

#define LPDDR4__PI_TDFI_CALVL_STROBE_F2__FLD LPDDR4__DENALI_PI_223__PI_TDFI_CALVL_STROBE_F2

4043

4044

#define LPDDR4__DENALI_PI_223__PI_TXP_F2_MASK 0x001F0000U

4045

#define LPDDR4__DENALI_PI_223__PI_TXP_F2_SHIFT 16U

4046

#define LPDDR4__DENALI_PI_223__PI_TXP_F2_WIDTH 5U

4047

#define LPDDR4__PI_TXP_F2__REG DENALI_PI_223

4048

#define LPDDR4__PI_TXP_F2__FLD LPDDR4__DENALI_PI_223__PI_TXP_F2

4049

4050

#define LPDDR4__DENALI_PI_223__PI_TMRWCKEL_F2_MASK 0xFF000000U

4051

#define LPDDR4__DENALI_PI_223__PI_TMRWCKEL_F2_SHIFT 24U

4052

#define LPDDR4__DENALI_PI_223__PI_TMRWCKEL_F2_WIDTH 8U

4053

#define LPDDR4__PI_TMRWCKEL_F2__REG DENALI_PI_223

4054

#define LPDDR4__PI_TMRWCKEL_F2__FLD LPDDR4__DENALI_PI_223__PI_TMRWCKEL_F2

4055

4056

#define LPDDR4__DENALI_PI_224_READ_MASK 0xFFFFFF1FU

4057

#define LPDDR4__DENALI_PI_224_WRITE_MASK 0xFFFFFF1FU

4058

#define LPDDR4__DENALI_PI_224__PI_TCKELCK_F2_MASK 0x0000001FU

4059

#define LPDDR4__DENALI_PI_224__PI_TCKELCK_F2_SHIFT 0U

4060

#define LPDDR4__DENALI_PI_224__PI_TCKELCK_F2_WIDTH 5U

4061

#define LPDDR4__PI_TCKELCK_F2__REG DENALI_PI_224

4062

#define LPDDR4__PI_TCKELCK_F2__FLD LPDDR4__DENALI_PI_224__PI_TCKELCK_F2

4063

4064

#define LPDDR4__DENALI_PI_224__PI_TDFI_INIT_START_F0_MASK 0xFFFFFF00U

4065

#define LPDDR4__DENALI_PI_224__PI_TDFI_INIT_START_F0_SHIFT 8U

4066

#define LPDDR4__DENALI_PI_224__PI_TDFI_INIT_START_F0_WIDTH 24U

4067

#define LPDDR4__PI_TDFI_INIT_START_F0__REG DENALI_PI_224

4068

#define LPDDR4__PI_TDFI_INIT_START_F0__FLD LPDDR4__DENALI_PI_224__PI_TDFI_INIT_START_F0

4069

4070

#define LPDDR4__DENALI_PI_225_READ_MASK 0x00FFFFFFU

4071

#define LPDDR4__DENALI_PI_225_WRITE_MASK 0x00FFFFFFU

4072

#define LPDDR4__DENALI_PI_225__PI_TDFI_INIT_COMPLETE_F0_MASK 0x00FFFFFFU

4073

#define LPDDR4__DENALI_PI_225__PI_TDFI_INIT_COMPLETE_F0_SHIFT 0U

4074

#define LPDDR4__DENALI_PI_225__PI_TDFI_INIT_COMPLETE_F0_WIDTH 24U

4075

#define LPDDR4__PI_TDFI_INIT_COMPLETE_F0__REG DENALI_PI_225

4076

#define LPDDR4__PI_TDFI_INIT_COMPLETE_F0__FLD LPDDR4__DENALI_PI_225__PI_TDFI_INIT_COMPLETE_F0

4077

4078

#define LPDDR4__DENALI_PI_226_READ_MASK 0x00FFFFFFU

4079

#define LPDDR4__DENALI_PI_226_WRITE_MASK 0x00FFFFFFU

4080

#define LPDDR4__DENALI_PI_226__PI_TDFI_INIT_START_F1_MASK 0x00FFFFFFU

4081

#define LPDDR4__DENALI_PI_226__PI_TDFI_INIT_START_F1_SHIFT 0U

4082

#define LPDDR4__DENALI_PI_226__PI_TDFI_INIT_START_F1_WIDTH 24U

4083

#define LPDDR4__PI_TDFI_INIT_START_F1__REG DENALI_PI_226

4084

#define LPDDR4__PI_TDFI_INIT_START_F1__FLD LPDDR4__DENALI_PI_226__PI_TDFI_INIT_START_F1

4085

4086

#define LPDDR4__DENALI_PI_227_READ_MASK 0x00FFFFFFU

4087

#define LPDDR4__DENALI_PI_227_WRITE_MASK 0x00FFFFFFU

4088

#define LPDDR4__DENALI_PI_227__PI_TDFI_INIT_COMPLETE_F1_MASK 0x00FFFFFFU

4089

#define LPDDR4__DENALI_PI_227__PI_TDFI_INIT_COMPLETE_F1_SHIFT 0U

4090

#define LPDDR4__DENALI_PI_227__PI_TDFI_INIT_COMPLETE_F1_WIDTH 24U

4091

#define LPDDR4__PI_TDFI_INIT_COMPLETE_F1__REG DENALI_PI_227

4092

#define LPDDR4__PI_TDFI_INIT_COMPLETE_F1__FLD LPDDR4__DENALI_PI_227__PI_TDFI_INIT_COMPLETE_F1

4093

4094

#define LPDDR4__DENALI_PI_228_READ_MASK 0x00FFFFFFU

4095

#define LPDDR4__DENALI_PI_228_WRITE_MASK 0x00FFFFFFU

4096

#define LPDDR4__DENALI_PI_228__PI_TDFI_INIT_START_F2_MASK 0x00FFFFFFU

4097

#define LPDDR4__DENALI_PI_228__PI_TDFI_INIT_START_F2_SHIFT 0U

4098

#define LPDDR4__DENALI_PI_228__PI_TDFI_INIT_START_F2_WIDTH 24U

4099

#define LPDDR4__PI_TDFI_INIT_START_F2__REG DENALI_PI_228

4100

#define LPDDR4__PI_TDFI_INIT_START_F2__FLD LPDDR4__DENALI_PI_228__PI_TDFI_INIT_START_F2

4101

4102

#define LPDDR4__DENALI_PI_229_READ_MASK 0x3FFFFFFFU

4103

#define LPDDR4__DENALI_PI_229_WRITE_MASK 0x3FFFFFFFU

4104

#define LPDDR4__DENALI_PI_229__PI_TDFI_INIT_COMPLETE_F2_MASK 0x00FFFFFFU

4105

#define LPDDR4__DENALI_PI_229__PI_TDFI_INIT_COMPLETE_F2_SHIFT 0U

4106

#define LPDDR4__DENALI_PI_229__PI_TDFI_INIT_COMPLETE_F2_WIDTH 24U

4107

#define LPDDR4__PI_TDFI_INIT_COMPLETE_F2__REG DENALI_PI_229

4108

#define LPDDR4__PI_TDFI_INIT_COMPLETE_F2__FLD LPDDR4__DENALI_PI_229__PI_TDFI_INIT_COMPLETE_F2

4109

4110

#define LPDDR4__DENALI_PI_229__PI_TCKEHDQS_F0_MASK 0x3F000000U

4111

#define LPDDR4__DENALI_PI_229__PI_TCKEHDQS_F0_SHIFT 24U

4112

#define LPDDR4__DENALI_PI_229__PI_TCKEHDQS_F0_WIDTH 6U

4113

#define LPDDR4__PI_TCKEHDQS_F0__REG DENALI_PI_229

4114

#define LPDDR4__PI_TCKEHDQS_F0__FLD LPDDR4__DENALI_PI_229__PI_TCKEHDQS_F0

4115

4116

#define LPDDR4__DENALI_PI_230_READ_MASK 0x003F03FFU

4117

#define LPDDR4__DENALI_PI_230_WRITE_MASK 0x003F03FFU

4118

#define LPDDR4__DENALI_PI_230__PI_TFC_F0_MASK 0x000003FFU

4119

#define LPDDR4__DENALI_PI_230__PI_TFC_F0_SHIFT 0U

4120

#define LPDDR4__DENALI_PI_230__PI_TFC_F0_WIDTH 10U

4121

#define LPDDR4__PI_TFC_F0__REG DENALI_PI_230

4122

#define LPDDR4__PI_TFC_F0__FLD LPDDR4__DENALI_PI_230__PI_TFC_F0

4123

4124

#define LPDDR4__DENALI_PI_230__PI_TCKEHDQS_F1_MASK 0x003F0000U

4125

#define LPDDR4__DENALI_PI_230__PI_TCKEHDQS_F1_SHIFT 16U

4126

#define LPDDR4__DENALI_PI_230__PI_TCKEHDQS_F1_WIDTH 6U

4127

#define LPDDR4__PI_TCKEHDQS_F1__REG DENALI_PI_230

4128

#define LPDDR4__PI_TCKEHDQS_F1__FLD LPDDR4__DENALI_PI_230__PI_TCKEHDQS_F1

4129

4130

#define LPDDR4__DENALI_PI_231_READ_MASK 0x003F03FFU

4131

#define LPDDR4__DENALI_PI_231_WRITE_MASK 0x003F03FFU

4132

#define LPDDR4__DENALI_PI_231__PI_TFC_F1_MASK 0x000003FFU

4133

#define LPDDR4__DENALI_PI_231__PI_TFC_F1_SHIFT 0U

4134

#define LPDDR4__DENALI_PI_231__PI_TFC_F1_WIDTH 10U

4135

#define LPDDR4__PI_TFC_F1__REG DENALI_PI_231

4136

#define LPDDR4__PI_TFC_F1__FLD LPDDR4__DENALI_PI_231__PI_TFC_F1

4137

4138

#define LPDDR4__DENALI_PI_231__PI_TCKEHDQS_F2_MASK 0x003F0000U

4139

#define LPDDR4__DENALI_PI_231__PI_TCKEHDQS_F2_SHIFT 16U

4140

#define LPDDR4__DENALI_PI_231__PI_TCKEHDQS_F2_WIDTH 6U

4141

#define LPDDR4__PI_TCKEHDQS_F2__REG DENALI_PI_231

4142

#define LPDDR4__PI_TCKEHDQS_F2__FLD LPDDR4__DENALI_PI_231__PI_TCKEHDQS_F2

4143

4144

#define LPDDR4__DENALI_PI_232_READ_MASK 0x030303FFU

4145

#define LPDDR4__DENALI_PI_232_WRITE_MASK 0x030303FFU

4146

#define LPDDR4__DENALI_PI_232__PI_TFC_F2_MASK 0x000003FFU

4147

#define LPDDR4__DENALI_PI_232__PI_TFC_F2_SHIFT 0U

4148

#define LPDDR4__DENALI_PI_232__PI_TFC_F2_WIDTH 10U

4149

#define LPDDR4__PI_TFC_F2__REG DENALI_PI_232

4150

#define LPDDR4__PI_TFC_F2__FLD LPDDR4__DENALI_PI_232__PI_TFC_F2

4151

4152

#define LPDDR4__DENALI_PI_232__PI_VREF_EN_F0_MASK 0x00030000U

4153

#define LPDDR4__DENALI_PI_232__PI_VREF_EN_F0_SHIFT 16U

4154

#define LPDDR4__DENALI_PI_232__PI_VREF_EN_F0_WIDTH 2U

4155

#define LPDDR4__PI_VREF_EN_F0__REG DENALI_PI_232

4156

#define LPDDR4__PI_VREF_EN_F0__FLD LPDDR4__DENALI_PI_232__PI_VREF_EN_F0

4157

4158

#define LPDDR4__DENALI_PI_232__PI_VREF_EN_F1_MASK 0x03000000U

4159

#define LPDDR4__DENALI_PI_232__PI_VREF_EN_F1_SHIFT 24U

4160

#define LPDDR4__DENALI_PI_232__PI_VREF_EN_F1_WIDTH 2U

4161

#define LPDDR4__PI_VREF_EN_F1__REG DENALI_PI_232

4162

#define LPDDR4__PI_VREF_EN_F1__FLD LPDDR4__DENALI_PI_232__PI_VREF_EN_F1

4163

4164

#define LPDDR4__DENALI_PI_233_READ_MASK 0x0003FF03U

4165

#define LPDDR4__DENALI_PI_233_WRITE_MASK 0x0003FF03U

4166

#define LPDDR4__DENALI_PI_233__PI_VREF_EN_F2_MASK 0x00000003U

4167

#define LPDDR4__DENALI_PI_233__PI_VREF_EN_F2_SHIFT 0U

4168

#define LPDDR4__DENALI_PI_233__PI_VREF_EN_F2_WIDTH 2U

4169

#define LPDDR4__PI_VREF_EN_F2__REG DENALI_PI_233

4170

#define LPDDR4__PI_VREF_EN_F2__FLD LPDDR4__DENALI_PI_233__PI_VREF_EN_F2

4171

4172

#define LPDDR4__DENALI_PI_233__PI_TDFI_WDQLVL_WR_F0_MASK 0x0003FF00U

4173

#define LPDDR4__DENALI_PI_233__PI_TDFI_WDQLVL_WR_F0_SHIFT 8U

4174

#define LPDDR4__DENALI_PI_233__PI_TDFI_WDQLVL_WR_F0_WIDTH 10U

4175

#define LPDDR4__PI_TDFI_WDQLVL_WR_F0__REG DENALI_PI_233

4176

#define LPDDR4__PI_TDFI_WDQLVL_WR_F0__FLD LPDDR4__DENALI_PI_233__PI_TDFI_WDQLVL_WR_F0

4177

4178

#define LPDDR4__DENALI_PI_234_READ_MASK 0x7F7F03FFU

4179

#define LPDDR4__DENALI_PI_234_WRITE_MASK 0x7F7F03FFU

4180

#define LPDDR4__DENALI_PI_234__PI_TDFI_WDQLVL_RW_F0_MASK 0x000003FFU

4181

#define LPDDR4__DENALI_PI_234__PI_TDFI_WDQLVL_RW_F0_SHIFT 0U

4182

#define LPDDR4__DENALI_PI_234__PI_TDFI_WDQLVL_RW_F0_WIDTH 10U

4183

#define LPDDR4__PI_TDFI_WDQLVL_RW_F0__REG DENALI_PI_234

4184

#define LPDDR4__PI_TDFI_WDQLVL_RW_F0__FLD LPDDR4__DENALI_PI_234__PI_TDFI_WDQLVL_RW_F0

4185

4186

#define LPDDR4__DENALI_PI_234__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_MASK 0x007F0000U

4187

#define LPDDR4__DENALI_PI_234__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_SHIFT 16U

4188

#define LPDDR4__DENALI_PI_234__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_WIDTH 7U

4189

#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F0__REG DENALI_PI_234

4190

#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F0__FLD LPDDR4__DENALI_PI_234__PI_WDQLVL_VREF_INITIAL_START_POINT_F0

4191

4192

#define LPDDR4__DENALI_PI_234__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_MASK 0x7F000000U

4193

#define LPDDR4__DENALI_PI_234__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_SHIFT 24U

4194

#define LPDDR4__DENALI_PI_234__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_WIDTH 7U

4195

#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0__REG DENALI_PI_234

4196

#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0__FLD LPDDR4__DENALI_PI_234__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0

4197

4198

#define LPDDR4__DENALI_PI_235_READ_MASK 0x1F03030FU

4199

#define LPDDR4__DENALI_PI_235_WRITE_MASK 0x1F03030FU

4200

#define LPDDR4__DENALI_PI_235__PI_WDQLVL_VREF_DELTA_F0_MASK 0x0000000FU

4201

#define LPDDR4__DENALI_PI_235__PI_WDQLVL_VREF_DELTA_F0_SHIFT 0U

4202

#define LPDDR4__DENALI_PI_235__PI_WDQLVL_VREF_DELTA_F0_WIDTH 4U

4203

#define LPDDR4__PI_WDQLVL_VREF_DELTA_F0__REG DENALI_PI_235

4204

#define LPDDR4__PI_WDQLVL_VREF_DELTA_F0__FLD LPDDR4__DENALI_PI_235__PI_WDQLVL_VREF_DELTA_F0

4205

4206

#define LPDDR4__DENALI_PI_235__PI_WDQLVL_EN_F0_MASK 0x00000300U

4207

#define LPDDR4__DENALI_PI_235__PI_WDQLVL_EN_F0_SHIFT 8U

4208

#define LPDDR4__DENALI_PI_235__PI_WDQLVL_EN_F0_WIDTH 2U

4209

#define LPDDR4__PI_WDQLVL_EN_F0__REG DENALI_PI_235

4210

#define LPDDR4__PI_WDQLVL_EN_F0__FLD LPDDR4__DENALI_PI_235__PI_WDQLVL_EN_F0

4211

4212

#define LPDDR4__DENALI_PI_235__PI_NTP_TRAIN_EN_F0_MASK 0x00030000U

4213

#define LPDDR4__DENALI_PI_235__PI_NTP_TRAIN_EN_F0_SHIFT 16U

4214

#define LPDDR4__DENALI_PI_235__PI_NTP_TRAIN_EN_F0_WIDTH 2U

4215

#define LPDDR4__PI_NTP_TRAIN_EN_F0__REG DENALI_PI_235

4216

#define LPDDR4__PI_NTP_TRAIN_EN_F0__FLD LPDDR4__DENALI_PI_235__PI_NTP_TRAIN_EN_F0

4217

4218

#define LPDDR4__DENALI_PI_235__PI_WDQLVL_CL_F0_MASK 0x1F000000U

4219

#define LPDDR4__DENALI_PI_235__PI_WDQLVL_CL_F0_SHIFT 24U

4220

#define LPDDR4__DENALI_PI_235__PI_WDQLVL_CL_F0_WIDTH 5U

4221

#define LPDDR4__PI_WDQLVL_CL_F0__REG DENALI_PI_235

4222

#define LPDDR4__PI_WDQLVL_CL_F0__FLD LPDDR4__DENALI_PI_235__PI_WDQLVL_CL_F0

4223

4224

#define LPDDR4__DENALI_PI_236_READ_MASK 0x03FFFFFFU

4225

#define LPDDR4__DENALI_PI_236_WRITE_MASK 0x03FFFFFFU

4226

#define LPDDR4__DENALI_PI_236__PI_WDQLVL_RDLAT_ADJ_F0_MASK 0x000000FFU

4227

#define LPDDR4__DENALI_PI_236__PI_WDQLVL_RDLAT_ADJ_F0_SHIFT 0U

4228

#define LPDDR4__DENALI_PI_236__PI_WDQLVL_RDLAT_ADJ_F0_WIDTH 8U

4229

#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F0__REG DENALI_PI_236

4230

#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_236__PI_WDQLVL_RDLAT_ADJ_F0

4231

4232

#define LPDDR4__DENALI_PI_236__PI_WDQLVL_WRLAT_ADJ_F0_MASK 0x0000FF00U

4233

#define LPDDR4__DENALI_PI_236__PI_WDQLVL_WRLAT_ADJ_F0_SHIFT 8U

4234

#define LPDDR4__DENALI_PI_236__PI_WDQLVL_WRLAT_ADJ_F0_WIDTH 8U

4235

#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F0__REG DENALI_PI_236

4236

#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_236__PI_WDQLVL_WRLAT_ADJ_F0

4237

4238

#define LPDDR4__DENALI_PI_236__PI_TDFI_WDQLVL_WR_F1_MASK 0x03FF0000U

4239

#define LPDDR4__DENALI_PI_236__PI_TDFI_WDQLVL_WR_F1_SHIFT 16U

4240

#define LPDDR4__DENALI_PI_236__PI_TDFI_WDQLVL_WR_F1_WIDTH 10U

4241

#define LPDDR4__PI_TDFI_WDQLVL_WR_F1__REG DENALI_PI_236

4242

#define LPDDR4__PI_TDFI_WDQLVL_WR_F1__FLD LPDDR4__DENALI_PI_236__PI_TDFI_WDQLVL_WR_F1

4243

4244

#define LPDDR4__DENALI_PI_237_READ_MASK 0x7F7F03FFU

4245

#define LPDDR4__DENALI_PI_237_WRITE_MASK 0x7F7F03FFU

4246

#define LPDDR4__DENALI_PI_237__PI_TDFI_WDQLVL_RW_F1_MASK 0x000003FFU

4247

#define LPDDR4__DENALI_PI_237__PI_TDFI_WDQLVL_RW_F1_SHIFT 0U

4248

#define LPDDR4__DENALI_PI_237__PI_TDFI_WDQLVL_RW_F1_WIDTH 10U

4249

#define LPDDR4__PI_TDFI_WDQLVL_RW_F1__REG DENALI_PI_237

4250

#define LPDDR4__PI_TDFI_WDQLVL_RW_F1__FLD LPDDR4__DENALI_PI_237__PI_TDFI_WDQLVL_RW_F1

4251

4252

#define LPDDR4__DENALI_PI_237__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_MASK 0x007F0000U

4253

#define LPDDR4__DENALI_PI_237__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_SHIFT 16U

4254

#define LPDDR4__DENALI_PI_237__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_WIDTH 7U

4255

#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F1__REG DENALI_PI_237

4256

#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F1__FLD LPDDR4__DENALI_PI_237__PI_WDQLVL_VREF_INITIAL_START_POINT_F1

4257

4258

#define LPDDR4__DENALI_PI_237__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_MASK 0x7F000000U

4259

#define LPDDR4__DENALI_PI_237__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_SHIFT 24U

4260

#define LPDDR4__DENALI_PI_237__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_WIDTH 7U

4261

#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1__REG DENALI_PI_237

4262

#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1__FLD LPDDR4__DENALI_PI_237__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1

4263

4264

#define LPDDR4__DENALI_PI_238_READ_MASK 0x1F03030FU

4265

#define LPDDR4__DENALI_PI_238_WRITE_MASK 0x1F03030FU

4266

#define LPDDR4__DENALI_PI_238__PI_WDQLVL_VREF_DELTA_F1_MASK 0x0000000FU

4267

#define LPDDR4__DENALI_PI_238__PI_WDQLVL_VREF_DELTA_F1_SHIFT 0U

4268

#define LPDDR4__DENALI_PI_238__PI_WDQLVL_VREF_DELTA_F1_WIDTH 4U

4269

#define LPDDR4__PI_WDQLVL_VREF_DELTA_F1__REG DENALI_PI_238

4270

#define LPDDR4__PI_WDQLVL_VREF_DELTA_F1__FLD LPDDR4__DENALI_PI_238__PI_WDQLVL_VREF_DELTA_F1

4271

4272

#define LPDDR4__DENALI_PI_238__PI_WDQLVL_EN_F1_MASK 0x00000300U

4273

#define LPDDR4__DENALI_PI_238__PI_WDQLVL_EN_F1_SHIFT 8U

4274

#define LPDDR4__DENALI_PI_238__PI_WDQLVL_EN_F1_WIDTH 2U

4275

#define LPDDR4__PI_WDQLVL_EN_F1__REG DENALI_PI_238

4276

#define LPDDR4__PI_WDQLVL_EN_F1__FLD LPDDR4__DENALI_PI_238__PI_WDQLVL_EN_F1

4277

4278

#define LPDDR4__DENALI_PI_238__PI_NTP_TRAIN_EN_F1_MASK 0x00030000U

4279

#define LPDDR4__DENALI_PI_238__PI_NTP_TRAIN_EN_F1_SHIFT 16U

4280

#define LPDDR4__DENALI_PI_238__PI_NTP_TRAIN_EN_F1_WIDTH 2U

4281

#define LPDDR4__PI_NTP_TRAIN_EN_F1__REG DENALI_PI_238

4282

#define LPDDR4__PI_NTP_TRAIN_EN_F1__FLD LPDDR4__DENALI_PI_238__PI_NTP_TRAIN_EN_F1

4283

4284

#define LPDDR4__DENALI_PI_238__PI_WDQLVL_CL_F1_MASK 0x1F000000U

4285

#define LPDDR4__DENALI_PI_238__PI_WDQLVL_CL_F1_SHIFT 24U

4286

#define LPDDR4__DENALI_PI_238__PI_WDQLVL_CL_F1_WIDTH 5U

4287

#define LPDDR4__PI_WDQLVL_CL_F1__REG DENALI_PI_238

4288

#define LPDDR4__PI_WDQLVL_CL_F1__FLD LPDDR4__DENALI_PI_238__PI_WDQLVL_CL_F1

4289

4290

#define LPDDR4__DENALI_PI_239_READ_MASK 0x03FFFFFFU

4291

#define LPDDR4__DENALI_PI_239_WRITE_MASK 0x03FFFFFFU

4292

#define LPDDR4__DENALI_PI_239__PI_WDQLVL_RDLAT_ADJ_F1_MASK 0x000000FFU

4293

#define LPDDR4__DENALI_PI_239__PI_WDQLVL_RDLAT_ADJ_F1_SHIFT 0U

4294

#define LPDDR4__DENALI_PI_239__PI_WDQLVL_RDLAT_ADJ_F1_WIDTH 8U

4295

#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F1__REG DENALI_PI_239

4296

#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_239__PI_WDQLVL_RDLAT_ADJ_F1

4297

4298

#define LPDDR4__DENALI_PI_239__PI_WDQLVL_WRLAT_ADJ_F1_MASK 0x0000FF00U

4299

#define LPDDR4__DENALI_PI_239__PI_WDQLVL_WRLAT_ADJ_F1_SHIFT 8U

4300

#define LPDDR4__DENALI_PI_239__PI_WDQLVL_WRLAT_ADJ_F1_WIDTH 8U

4301

#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F1__REG DENALI_PI_239

4302

#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_239__PI_WDQLVL_WRLAT_ADJ_F1

4303

4304

#define LPDDR4__DENALI_PI_239__PI_TDFI_WDQLVL_WR_F2_MASK 0x03FF0000U

4305

#define LPDDR4__DENALI_PI_239__PI_TDFI_WDQLVL_WR_F2_SHIFT 16U

4306

#define LPDDR4__DENALI_PI_239__PI_TDFI_WDQLVL_WR_F2_WIDTH 10U

4307

#define LPDDR4__PI_TDFI_WDQLVL_WR_F2__REG DENALI_PI_239

4308

#define LPDDR4__PI_TDFI_WDQLVL_WR_F2__FLD LPDDR4__DENALI_PI_239__PI_TDFI_WDQLVL_WR_F2

4309

4310

#define LPDDR4__DENALI_PI_240_READ_MASK 0x7F7F03FFU

4311

#define LPDDR4__DENALI_PI_240_WRITE_MASK 0x7F7F03FFU

4312

#define LPDDR4__DENALI_PI_240__PI_TDFI_WDQLVL_RW_F2_MASK 0x000003FFU

4313

#define LPDDR4__DENALI_PI_240__PI_TDFI_WDQLVL_RW_F2_SHIFT 0U

4314

#define LPDDR4__DENALI_PI_240__PI_TDFI_WDQLVL_RW_F2_WIDTH 10U

4315

#define LPDDR4__PI_TDFI_WDQLVL_RW_F2__REG DENALI_PI_240

4316

#define LPDDR4__PI_TDFI_WDQLVL_RW_F2__FLD LPDDR4__DENALI_PI_240__PI_TDFI_WDQLVL_RW_F2

4317

4318

#define LPDDR4__DENALI_PI_240__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_MASK 0x007F0000U

4319

#define LPDDR4__DENALI_PI_240__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_SHIFT 16U

4320

#define LPDDR4__DENALI_PI_240__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_WIDTH 7U

4321

#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F2__REG DENALI_PI_240

4322

#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F2__FLD LPDDR4__DENALI_PI_240__PI_WDQLVL_VREF_INITIAL_START_POINT_F2

4323

4324

#define LPDDR4__DENALI_PI_240__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_MASK 0x7F000000U

4325

#define LPDDR4__DENALI_PI_240__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_SHIFT 24U

4326

#define LPDDR4__DENALI_PI_240__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_WIDTH 7U

4327

#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2__REG DENALI_PI_240

4328

#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2__FLD LPDDR4__DENALI_PI_240__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2

4329

4330

#define LPDDR4__DENALI_PI_241_READ_MASK 0x1F03030FU

4331

#define LPDDR4__DENALI_PI_241_WRITE_MASK 0x1F03030FU

4332

#define LPDDR4__DENALI_PI_241__PI_WDQLVL_VREF_DELTA_F2_MASK 0x0000000FU

4333

#define LPDDR4__DENALI_PI_241__PI_WDQLVL_VREF_DELTA_F2_SHIFT 0U

4334

#define LPDDR4__DENALI_PI_241__PI_WDQLVL_VREF_DELTA_F2_WIDTH 4U

4335

#define LPDDR4__PI_WDQLVL_VREF_DELTA_F2__REG DENALI_PI_241

4336

#define LPDDR4__PI_WDQLVL_VREF_DELTA_F2__FLD LPDDR4__DENALI_PI_241__PI_WDQLVL_VREF_DELTA_F2

4337

4338

#define LPDDR4__DENALI_PI_241__PI_WDQLVL_EN_F2_MASK 0x00000300U

4339

#define LPDDR4__DENALI_PI_241__PI_WDQLVL_EN_F2_SHIFT 8U

4340

#define LPDDR4__DENALI_PI_241__PI_WDQLVL_EN_F2_WIDTH 2U

4341

#define LPDDR4__PI_WDQLVL_EN_F2__REG DENALI_PI_241

4342

#define LPDDR4__PI_WDQLVL_EN_F2__FLD LPDDR4__DENALI_PI_241__PI_WDQLVL_EN_F2

4343

4344

#define LPDDR4__DENALI_PI_241__PI_NTP_TRAIN_EN_F2_MASK 0x00030000U

4345

#define LPDDR4__DENALI_PI_241__PI_NTP_TRAIN_EN_F2_SHIFT 16U

4346

#define LPDDR4__DENALI_PI_241__PI_NTP_TRAIN_EN_F2_WIDTH 2U

4347

#define LPDDR4__PI_NTP_TRAIN_EN_F2__REG DENALI_PI_241

4348

#define LPDDR4__PI_NTP_TRAIN_EN_F2__FLD LPDDR4__DENALI_PI_241__PI_NTP_TRAIN_EN_F2

4349

4350

#define LPDDR4__DENALI_PI_241__PI_WDQLVL_CL_F2_MASK 0x1F000000U

4351

#define LPDDR4__DENALI_PI_241__PI_WDQLVL_CL_F2_SHIFT 24U

4352

#define LPDDR4__DENALI_PI_241__PI_WDQLVL_CL_F2_WIDTH 5U

4353

#define LPDDR4__PI_WDQLVL_CL_F2__REG DENALI_PI_241

4354

#define LPDDR4__PI_WDQLVL_CL_F2__FLD LPDDR4__DENALI_PI_241__PI_WDQLVL_CL_F2

4355

4356

#define LPDDR4__DENALI_PI_242_READ_MASK 0x0303FFFFU

4357

#define LPDDR4__DENALI_PI_242_WRITE_MASK 0x0303FFFFU

4358

#define LPDDR4__DENALI_PI_242__PI_WDQLVL_RDLAT_ADJ_F2_MASK 0x000000FFU

4359

#define LPDDR4__DENALI_PI_242__PI_WDQLVL_RDLAT_ADJ_F2_SHIFT 0U

4360

#define LPDDR4__DENALI_PI_242__PI_WDQLVL_RDLAT_ADJ_F2_WIDTH 8U

4361

#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F2__REG DENALI_PI_242

4362

#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_242__PI_WDQLVL_RDLAT_ADJ_F2

4363

4364

#define LPDDR4__DENALI_PI_242__PI_WDQLVL_WRLAT_ADJ_F2_MASK 0x0000FF00U

4365

#define LPDDR4__DENALI_PI_242__PI_WDQLVL_WRLAT_ADJ_F2_SHIFT 8U

4366

#define LPDDR4__DENALI_PI_242__PI_WDQLVL_WRLAT_ADJ_F2_WIDTH 8U

4367

#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F2__REG DENALI_PI_242

4368

#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_242__PI_WDQLVL_WRLAT_ADJ_F2

4369

4370

#define LPDDR4__DENALI_PI_242__PI_RD_DBI_LEVEL_EN_F0_MASK 0x00030000U

4371

#define LPDDR4__DENALI_PI_242__PI_RD_DBI_LEVEL_EN_F0_SHIFT 16U

4372

#define LPDDR4__DENALI_PI_242__PI_RD_DBI_LEVEL_EN_F0_WIDTH 2U

4373

#define LPDDR4__PI_RD_DBI_LEVEL_EN_F0__REG DENALI_PI_242

4374

#define LPDDR4__PI_RD_DBI_LEVEL_EN_F0__FLD LPDDR4__DENALI_PI_242__PI_RD_DBI_LEVEL_EN_F0

4375

4376

#define LPDDR4__DENALI_PI_242__PI_RD_DBI_LEVEL_EN_F1_MASK 0x03000000U

4377

#define LPDDR4__DENALI_PI_242__PI_RD_DBI_LEVEL_EN_F1_SHIFT 24U

4378

#define LPDDR4__DENALI_PI_242__PI_RD_DBI_LEVEL_EN_F1_WIDTH 2U

4379

#define LPDDR4__PI_RD_DBI_LEVEL_EN_F1__REG DENALI_PI_242

4380

#define LPDDR4__PI_RD_DBI_LEVEL_EN_F1__FLD LPDDR4__DENALI_PI_242__PI_RD_DBI_LEVEL_EN_F1

4381

4382

#define LPDDR4__DENALI_PI_243_READ_MASK 0xFFFFFF03U

4383

#define LPDDR4__DENALI_PI_243_WRITE_MASK 0xFFFFFF03U

4384

#define LPDDR4__DENALI_PI_243__PI_RD_DBI_LEVEL_EN_F2_MASK 0x00000003U

4385

#define LPDDR4__DENALI_PI_243__PI_RD_DBI_LEVEL_EN_F2_SHIFT 0U

4386

#define LPDDR4__DENALI_PI_243__PI_RD_DBI_LEVEL_EN_F2_WIDTH 2U

4387

#define LPDDR4__PI_RD_DBI_LEVEL_EN_F2__REG DENALI_PI_243

4388

#define LPDDR4__PI_RD_DBI_LEVEL_EN_F2__FLD LPDDR4__DENALI_PI_243__PI_RD_DBI_LEVEL_EN_F2

4389

4390

#define LPDDR4__DENALI_PI_243__PI_TRTP_F0_MASK 0x0000FF00U

4391

#define LPDDR4__DENALI_PI_243__PI_TRTP_F0_SHIFT 8U

4392

#define LPDDR4__DENALI_PI_243__PI_TRTP_F0_WIDTH 8U

4393

#define LPDDR4__PI_TRTP_F0__REG DENALI_PI_243

4394

#define LPDDR4__PI_TRTP_F0__FLD LPDDR4__DENALI_PI_243__PI_TRTP_F0

4395

4396

#define LPDDR4__DENALI_PI_243__PI_TRP_F0_MASK 0x00FF0000U

4397

#define LPDDR4__DENALI_PI_243__PI_TRP_F0_SHIFT 16U

4398

#define LPDDR4__DENALI_PI_243__PI_TRP_F0_WIDTH 8U

4399

#define LPDDR4__PI_TRP_F0__REG DENALI_PI_243

4400

#define LPDDR4__PI_TRP_F0__FLD LPDDR4__DENALI_PI_243__PI_TRP_F0

4401

4402

#define LPDDR4__DENALI_PI_243__PI_TRCD_F0_MASK 0xFF000000U

4403

#define LPDDR4__DENALI_PI_243__PI_TRCD_F0_SHIFT 24U

4404

#define LPDDR4__DENALI_PI_243__PI_TRCD_F0_WIDTH 8U

4405

#define LPDDR4__PI_TRCD_F0__REG DENALI_PI_243

4406

#define LPDDR4__PI_TRCD_F0__FLD LPDDR4__DENALI_PI_243__PI_TRCD_F0

4407

4408

#define LPDDR4__DENALI_PI_244_READ_MASK 0x00FF3F1FU

4409

#define LPDDR4__DENALI_PI_244_WRITE_MASK 0x00FF3F1FU

4410

#define LPDDR4__DENALI_PI_244__PI_TCCD_L_F0_MASK 0x0000001FU

4411

#define LPDDR4__DENALI_PI_244__PI_TCCD_L_F0_SHIFT 0U

4412

#define LPDDR4__DENALI_PI_244__PI_TCCD_L_F0_WIDTH 5U

4413

#define LPDDR4__PI_TCCD_L_F0__REG DENALI_PI_244

4414

#define LPDDR4__PI_TCCD_L_F0__FLD LPDDR4__DENALI_PI_244__PI_TCCD_L_F0

4415

4416

#define LPDDR4__DENALI_PI_244__PI_TWTR_F0_MASK 0x00003F00U

4417

#define LPDDR4__DENALI_PI_244__PI_TWTR_F0_SHIFT 8U

4418

#define LPDDR4__DENALI_PI_244__PI_TWTR_F0_WIDTH 6U

4419

#define LPDDR4__PI_TWTR_F0__REG DENALI_PI_244

4420

#define LPDDR4__PI_TWTR_F0__FLD LPDDR4__DENALI_PI_244__PI_TWTR_F0

4421

4422

#define LPDDR4__DENALI_PI_244__PI_TWR_F0_MASK 0x00FF0000U

4423

#define LPDDR4__DENALI_PI_244__PI_TWR_F0_SHIFT 16U

4424

#define LPDDR4__DENALI_PI_244__PI_TWR_F0_WIDTH 8U

4425

#define LPDDR4__PI_TWR_F0__REG DENALI_PI_244

4426

#define LPDDR4__PI_TWR_F0__FLD LPDDR4__DENALI_PI_244__PI_TWR_F0

4427

4428

#define LPDDR4__DENALI_PI_245_READ_MASK 0x000FFFFFU

4429

#define LPDDR4__DENALI_PI_245_WRITE_MASK 0x000FFFFFU

4430

#define LPDDR4__DENALI_PI_245__PI_TRAS_MAX_F0_MASK 0x000FFFFFU

4431

#define LPDDR4__DENALI_PI_245__PI_TRAS_MAX_F0_SHIFT 0U

4432

#define LPDDR4__DENALI_PI_245__PI_TRAS_MAX_F0_WIDTH 20U

4433

#define LPDDR4__PI_TRAS_MAX_F0__REG DENALI_PI_245

4434

#define LPDDR4__PI_TRAS_MAX_F0__FLD LPDDR4__DENALI_PI_245__PI_TRAS_MAX_F0

4435

4436

#define LPDDR4__DENALI_PI_246_READ_MASK 0x3F0F01FFU

4437

#define LPDDR4__DENALI_PI_246_WRITE_MASK 0x3F0F01FFU

4438

#define LPDDR4__DENALI_PI_246__PI_TRAS_MIN_F0_MASK 0x000001FFU

4439

#define LPDDR4__DENALI_PI_246__PI_TRAS_MIN_F0_SHIFT 0U

4440

#define LPDDR4__DENALI_PI_246__PI_TRAS_MIN_F0_WIDTH 9U

4441

#define LPDDR4__PI_TRAS_MIN_F0__REG DENALI_PI_246

4442

#define LPDDR4__PI_TRAS_MIN_F0__FLD LPDDR4__DENALI_PI_246__PI_TRAS_MIN_F0

4443

4444

#define LPDDR4__DENALI_PI_246__PI_TDQSCK_MAX_F0_MASK 0x000F0000U

4445

#define LPDDR4__DENALI_PI_246__PI_TDQSCK_MAX_F0_SHIFT 16U

4446

#define LPDDR4__DENALI_PI_246__PI_TDQSCK_MAX_F0_WIDTH 4U

4447

#define LPDDR4__PI_TDQSCK_MAX_F0__REG DENALI_PI_246

4448

#define LPDDR4__PI_TDQSCK_MAX_F0__FLD LPDDR4__DENALI_PI_246__PI_TDQSCK_MAX_F0

4449

4450

#define LPDDR4__DENALI_PI_246__PI_TCCDMW_F0_MASK 0x3F000000U

4451

#define LPDDR4__DENALI_PI_246__PI_TCCDMW_F0_SHIFT 24U

4452

#define LPDDR4__DENALI_PI_246__PI_TCCDMW_F0_WIDTH 6U

4453

#define LPDDR4__PI_TCCDMW_F0__REG DENALI_PI_246

4454

#define LPDDR4__PI_TCCDMW_F0__FLD LPDDR4__DENALI_PI_246__PI_TCCDMW_F0

4455

4456

#define LPDDR4__DENALI_PI_247_READ_MASK 0xFFFFFFFFU

4457

#define LPDDR4__DENALI_PI_247_WRITE_MASK 0xFFFFFFFFU

4458

#define LPDDR4__DENALI_PI_247__PI_TSR_F0_MASK 0x000000FFU

4459

#define LPDDR4__DENALI_PI_247__PI_TSR_F0_SHIFT 0U

4460

#define LPDDR4__DENALI_PI_247__PI_TSR_F0_WIDTH 8U

4461

#define LPDDR4__PI_TSR_F0__REG DENALI_PI_247

4462

#define LPDDR4__PI_TSR_F0__FLD LPDDR4__DENALI_PI_247__PI_TSR_F0

4463

4464

#define LPDDR4__DENALI_PI_247__PI_TMRD_F0_MASK 0x0000FF00U

4465

#define LPDDR4__DENALI_PI_247__PI_TMRD_F0_SHIFT 8U

4466

#define LPDDR4__DENALI_PI_247__PI_TMRD_F0_WIDTH 8U

4467

#define LPDDR4__PI_TMRD_F0__REG DENALI_PI_247

4468

#define LPDDR4__PI_TMRD_F0__FLD LPDDR4__DENALI_PI_247__PI_TMRD_F0

4469

4470

#define LPDDR4__DENALI_PI_247__PI_TMRW_F0_MASK 0x00FF0000U

4471

#define LPDDR4__DENALI_PI_247__PI_TMRW_F0_SHIFT 16U

4472

#define LPDDR4__DENALI_PI_247__PI_TMRW_F0_WIDTH 8U

4473

#define LPDDR4__PI_TMRW_F0__REG DENALI_PI_247

4474

#define LPDDR4__PI_TMRW_F0__FLD LPDDR4__DENALI_PI_247__PI_TMRW_F0

4475

4476

#define LPDDR4__DENALI_PI_247__PI_TMOD_F0_MASK 0xFF000000U

4477

#define LPDDR4__DENALI_PI_247__PI_TMOD_F0_SHIFT 24U

4478

#define LPDDR4__DENALI_PI_247__PI_TMOD_F0_WIDTH 8U

4479

#define LPDDR4__PI_TMOD_F0__REG DENALI_PI_247

4480

#define LPDDR4__PI_TMOD_F0__FLD LPDDR4__DENALI_PI_247__PI_TMOD_F0

4481

4482

#define LPDDR4__DENALI_PI_248_READ_MASK 0xFFFFFFFFU

4483

#define LPDDR4__DENALI_PI_248_WRITE_MASK 0xFFFFFFFFU

4484

#define LPDDR4__DENALI_PI_248__PI_TMOD_PAR_F0_MASK 0x000000FFU

4485

#define LPDDR4__DENALI_PI_248__PI_TMOD_PAR_F0_SHIFT 0U

4486

#define LPDDR4__DENALI_PI_248__PI_TMOD_PAR_F0_WIDTH 8U

4487

#define LPDDR4__PI_TMOD_PAR_F0__REG DENALI_PI_248

4488

#define LPDDR4__PI_TMOD_PAR_F0__FLD LPDDR4__DENALI_PI_248__PI_TMOD_PAR_F0

4489

4490

#define LPDDR4__DENALI_PI_248__PI_TMRD_PAR_F0_MASK 0x0000FF00U

4491

#define LPDDR4__DENALI_PI_248__PI_TMRD_PAR_F0_SHIFT 8U

4492

#define LPDDR4__DENALI_PI_248__PI_TMRD_PAR_F0_WIDTH 8U

4493

#define LPDDR4__PI_TMRD_PAR_F0__REG DENALI_PI_248

4494

#define LPDDR4__PI_TMRD_PAR_F0__FLD LPDDR4__DENALI_PI_248__PI_TMRD_PAR_F0

4495

4496

#define LPDDR4__DENALI_PI_248__PI_TRTP_F1_MASK 0x00FF0000U

4497

#define LPDDR4__DENALI_PI_248__PI_TRTP_F1_SHIFT 16U

4498

#define LPDDR4__DENALI_PI_248__PI_TRTP_F1_WIDTH 8U

4499

#define LPDDR4__PI_TRTP_F1__REG DENALI_PI_248

4500

#define LPDDR4__PI_TRTP_F1__FLD LPDDR4__DENALI_PI_248__PI_TRTP_F1

4501

4502

#define LPDDR4__DENALI_PI_248__PI_TRP_F1_MASK 0xFF000000U

4503

#define LPDDR4__DENALI_PI_248__PI_TRP_F1_SHIFT 24U

4504

#define LPDDR4__DENALI_PI_248__PI_TRP_F1_WIDTH 8U

4505

#define LPDDR4__PI_TRP_F1__REG DENALI_PI_248

4506

#define LPDDR4__PI_TRP_F1__FLD LPDDR4__DENALI_PI_248__PI_TRP_F1

4507

4508

#define LPDDR4__DENALI_PI_249_READ_MASK 0xFF3F1FFFU

4509

#define LPDDR4__DENALI_PI_249_WRITE_MASK 0xFF3F1FFFU

4510

#define LPDDR4__DENALI_PI_249__PI_TRCD_F1_MASK 0x000000FFU

4511

#define LPDDR4__DENALI_PI_249__PI_TRCD_F1_SHIFT 0U

4512

#define LPDDR4__DENALI_PI_249__PI_TRCD_F1_WIDTH 8U

4513

#define LPDDR4__PI_TRCD_F1__REG DENALI_PI_249

4514

#define LPDDR4__PI_TRCD_F1__FLD LPDDR4__DENALI_PI_249__PI_TRCD_F1

4515

4516

#define LPDDR4__DENALI_PI_249__PI_TCCD_L_F1_MASK 0x00001F00U

4517

#define LPDDR4__DENALI_PI_249__PI_TCCD_L_F1_SHIFT 8U

4518

#define LPDDR4__DENALI_PI_249__PI_TCCD_L_F1_WIDTH 5U

4519

#define LPDDR4__PI_TCCD_L_F1__REG DENALI_PI_249

4520

#define LPDDR4__PI_TCCD_L_F1__FLD LPDDR4__DENALI_PI_249__PI_TCCD_L_F1

4521

4522

#define LPDDR4__DENALI_PI_249__PI_TWTR_F1_MASK 0x003F0000U

4523

#define LPDDR4__DENALI_PI_249__PI_TWTR_F1_SHIFT 16U

4524

#define LPDDR4__DENALI_PI_249__PI_TWTR_F1_WIDTH 6U

4525

#define LPDDR4__PI_TWTR_F1__REG DENALI_PI_249

4526

#define LPDDR4__PI_TWTR_F1__FLD LPDDR4__DENALI_PI_249__PI_TWTR_F1

4527

4528

#define LPDDR4__DENALI_PI_249__PI_TWR_F1_MASK 0xFF000000U

4529

#define LPDDR4__DENALI_PI_249__PI_TWR_F1_SHIFT 24U

4530

#define LPDDR4__DENALI_PI_249__PI_TWR_F1_WIDTH 8U

4531

#define LPDDR4__PI_TWR_F1__REG DENALI_PI_249

4532

#define LPDDR4__PI_TWR_F1__FLD LPDDR4__DENALI_PI_249__PI_TWR_F1

4533

4534

#define LPDDR4__DENALI_PI_250_READ_MASK 0x000FFFFFU

4535

#define LPDDR4__DENALI_PI_250_WRITE_MASK 0x000FFFFFU

4536

#define LPDDR4__DENALI_PI_250__PI_TRAS_MAX_F1_MASK 0x000FFFFFU

4537

#define LPDDR4__DENALI_PI_250__PI_TRAS_MAX_F1_SHIFT 0U

4538

#define LPDDR4__DENALI_PI_250__PI_TRAS_MAX_F1_WIDTH 20U

4539

#define LPDDR4__PI_TRAS_MAX_F1__REG DENALI_PI_250

4540

#define LPDDR4__PI_TRAS_MAX_F1__FLD LPDDR4__DENALI_PI_250__PI_TRAS_MAX_F1

4541

4542

#define LPDDR4__DENALI_PI_251_READ_MASK 0x3F0F01FFU

4543

#define LPDDR4__DENALI_PI_251_WRITE_MASK 0x3F0F01FFU

4544

#define LPDDR4__DENALI_PI_251__PI_TRAS_MIN_F1_MASK 0x000001FFU

4545

#define LPDDR4__DENALI_PI_251__PI_TRAS_MIN_F1_SHIFT 0U

4546

#define LPDDR4__DENALI_PI_251__PI_TRAS_MIN_F1_WIDTH 9U

4547

#define LPDDR4__PI_TRAS_MIN_F1__REG DENALI_PI_251

4548

#define LPDDR4__PI_TRAS_MIN_F1__FLD LPDDR4__DENALI_PI_251__PI_TRAS_MIN_F1

4549

4550

#define LPDDR4__DENALI_PI_251__PI_TDQSCK_MAX_F1_MASK 0x000F0000U

4551

#define LPDDR4__DENALI_PI_251__PI_TDQSCK_MAX_F1_SHIFT 16U

4552

#define LPDDR4__DENALI_PI_251__PI_TDQSCK_MAX_F1_WIDTH 4U

4553

#define LPDDR4__PI_TDQSCK_MAX_F1__REG DENALI_PI_251

4554

#define LPDDR4__PI_TDQSCK_MAX_F1__FLD LPDDR4__DENALI_PI_251__PI_TDQSCK_MAX_F1

4555

4556

#define LPDDR4__DENALI_PI_251__PI_TCCDMW_F1_MASK 0x3F000000U

4557

#define LPDDR4__DENALI_PI_251__PI_TCCDMW_F1_SHIFT 24U

4558

#define LPDDR4__DENALI_PI_251__PI_TCCDMW_F1_WIDTH 6U

4559

#define LPDDR4__PI_TCCDMW_F1__REG DENALI_PI_251

4560

#define LPDDR4__PI_TCCDMW_F1__FLD LPDDR4__DENALI_PI_251__PI_TCCDMW_F1

4561

4562

#define LPDDR4__DENALI_PI_252_READ_MASK 0xFFFFFFFFU

4563

#define LPDDR4__DENALI_PI_252_WRITE_MASK 0xFFFFFFFFU

4564

#define LPDDR4__DENALI_PI_252__PI_TSR_F1_MASK 0x000000FFU

4565

#define LPDDR4__DENALI_PI_252__PI_TSR_F1_SHIFT 0U

4566

#define LPDDR4__DENALI_PI_252__PI_TSR_F1_WIDTH 8U

4567

#define LPDDR4__PI_TSR_F1__REG DENALI_PI_252

4568

#define LPDDR4__PI_TSR_F1__FLD LPDDR4__DENALI_PI_252__PI_TSR_F1

4569

4570

#define LPDDR4__DENALI_PI_252__PI_TMRD_F1_MASK 0x0000FF00U

4571

#define LPDDR4__DENALI_PI_252__PI_TMRD_F1_SHIFT 8U

4572

#define LPDDR4__DENALI_PI_252__PI_TMRD_F1_WIDTH 8U

4573

#define LPDDR4__PI_TMRD_F1__REG DENALI_PI_252

4574

#define LPDDR4__PI_TMRD_F1__FLD LPDDR4__DENALI_PI_252__PI_TMRD_F1

4575

4576

#define LPDDR4__DENALI_PI_252__PI_TMRW_F1_MASK 0x00FF0000U

4577

#define LPDDR4__DENALI_PI_252__PI_TMRW_F1_SHIFT 16U

4578

#define LPDDR4__DENALI_PI_252__PI_TMRW_F1_WIDTH 8U

4579

#define LPDDR4__PI_TMRW_F1__REG DENALI_PI_252

4580

#define LPDDR4__PI_TMRW_F1__FLD LPDDR4__DENALI_PI_252__PI_TMRW_F1

4581

4582

#define LPDDR4__DENALI_PI_252__PI_TMOD_F1_MASK 0xFF000000U

4583

#define LPDDR4__DENALI_PI_252__PI_TMOD_F1_SHIFT 24U

4584

#define LPDDR4__DENALI_PI_252__PI_TMOD_F1_WIDTH 8U

4585

#define LPDDR4__PI_TMOD_F1__REG DENALI_PI_252

4586

#define LPDDR4__PI_TMOD_F1__FLD LPDDR4__DENALI_PI_252__PI_TMOD_F1

4587

4588

#define LPDDR4__DENALI_PI_253_READ_MASK 0xFFFFFFFFU

4589

#define LPDDR4__DENALI_PI_253_WRITE_MASK 0xFFFFFFFFU

4590

#define LPDDR4__DENALI_PI_253__PI_TMOD_PAR_F1_MASK 0x000000FFU

4591

#define LPDDR4__DENALI_PI_253__PI_TMOD_PAR_F1_SHIFT 0U

4592

#define LPDDR4__DENALI_PI_253__PI_TMOD_PAR_F1_WIDTH 8U

4593

#define LPDDR4__PI_TMOD_PAR_F1__REG DENALI_PI_253

4594

#define LPDDR4__PI_TMOD_PAR_F1__FLD LPDDR4__DENALI_PI_253__PI_TMOD_PAR_F1

4595

4596

#define LPDDR4__DENALI_PI_253__PI_TMRD_PAR_F1_MASK 0x0000FF00U

4597

#define LPDDR4__DENALI_PI_253__PI_TMRD_PAR_F1_SHIFT 8U

4598

#define LPDDR4__DENALI_PI_253__PI_TMRD_PAR_F1_WIDTH 8U

4599

#define LPDDR4__PI_TMRD_PAR_F1__REG DENALI_PI_253

4600

#define LPDDR4__PI_TMRD_PAR_F1__FLD LPDDR4__DENALI_PI_253__PI_TMRD_PAR_F1

4601

4602

#define LPDDR4__DENALI_PI_253__PI_TRTP_F2_MASK 0x00FF0000U

4603

#define LPDDR4__DENALI_PI_253__PI_TRTP_F2_SHIFT 16U

4604

#define LPDDR4__DENALI_PI_253__PI_TRTP_F2_WIDTH 8U

4605

#define LPDDR4__PI_TRTP_F2__REG DENALI_PI_253

4606

#define LPDDR4__PI_TRTP_F2__FLD LPDDR4__DENALI_PI_253__PI_TRTP_F2

4607

4608

#define LPDDR4__DENALI_PI_253__PI_TRP_F2_MASK 0xFF000000U

4609

#define LPDDR4__DENALI_PI_253__PI_TRP_F2_SHIFT 24U

4610

#define LPDDR4__DENALI_PI_253__PI_TRP_F2_WIDTH 8U

4611

#define LPDDR4__PI_TRP_F2__REG DENALI_PI_253

4612

#define LPDDR4__PI_TRP_F2__FLD LPDDR4__DENALI_PI_253__PI_TRP_F2

4613

4614

#define LPDDR4__DENALI_PI_254_READ_MASK 0xFF3F1FFFU

4615

#define LPDDR4__DENALI_PI_254_WRITE_MASK 0xFF3F1FFFU

4616

#define LPDDR4__DENALI_PI_254__PI_TRCD_F2_MASK 0x000000FFU

4617

#define LPDDR4__DENALI_PI_254__PI_TRCD_F2_SHIFT 0U

4618

#define LPDDR4__DENALI_PI_254__PI_TRCD_F2_WIDTH 8U

4619

#define LPDDR4__PI_TRCD_F2__REG DENALI_PI_254

4620

#define LPDDR4__PI_TRCD_F2__FLD LPDDR4__DENALI_PI_254__PI_TRCD_F2

4621

4622

#define LPDDR4__DENALI_PI_254__PI_TCCD_L_F2_MASK 0x00001F00U

4623

#define LPDDR4__DENALI_PI_254__PI_TCCD_L_F2_SHIFT 8U

4624

#define LPDDR4__DENALI_PI_254__PI_TCCD_L_F2_WIDTH 5U

4625

#define LPDDR4__PI_TCCD_L_F2__REG DENALI_PI_254

4626

#define LPDDR4__PI_TCCD_L_F2__FLD LPDDR4__DENALI_PI_254__PI_TCCD_L_F2

4627

4628

#define LPDDR4__DENALI_PI_254__PI_TWTR_F2_MASK 0x003F0000U

4629

#define LPDDR4__DENALI_PI_254__PI_TWTR_F2_SHIFT 16U

4630

#define LPDDR4__DENALI_PI_254__PI_TWTR_F2_WIDTH 6U

4631

#define LPDDR4__PI_TWTR_F2__REG DENALI_PI_254

4632

#define LPDDR4__PI_TWTR_F2__FLD LPDDR4__DENALI_PI_254__PI_TWTR_F2

4633

4634

#define LPDDR4__DENALI_PI_254__PI_TWR_F2_MASK 0xFF000000U

4635

#define LPDDR4__DENALI_PI_254__PI_TWR_F2_SHIFT 24U

4636

#define LPDDR4__DENALI_PI_254__PI_TWR_F2_WIDTH 8U

4637

#define LPDDR4__PI_TWR_F2__REG DENALI_PI_254

4638

#define LPDDR4__PI_TWR_F2__FLD LPDDR4__DENALI_PI_254__PI_TWR_F2

4639

4640

#define LPDDR4__DENALI_PI_255_READ_MASK 0x000FFFFFU

4641

#define LPDDR4__DENALI_PI_255_WRITE_MASK 0x000FFFFFU

4642

#define LPDDR4__DENALI_PI_255__PI_TRAS_MAX_F2_MASK 0x000FFFFFU

4643

#define LPDDR4__DENALI_PI_255__PI_TRAS_MAX_F2_SHIFT 0U

4644

#define LPDDR4__DENALI_PI_255__PI_TRAS_MAX_F2_WIDTH 20U

4645

#define LPDDR4__PI_TRAS_MAX_F2__REG DENALI_PI_255

4646

#define LPDDR4__PI_TRAS_MAX_F2__FLD LPDDR4__DENALI_PI_255__PI_TRAS_MAX_F2

4647

4648

#define LPDDR4__DENALI_PI_256_READ_MASK 0x3F0F01FFU

4649

#define LPDDR4__DENALI_PI_256_WRITE_MASK 0x3F0F01FFU

4650

#define LPDDR4__DENALI_PI_256__PI_TRAS_MIN_F2_MASK 0x000001FFU

4651

#define LPDDR4__DENALI_PI_256__PI_TRAS_MIN_F2_SHIFT 0U

4652

#define LPDDR4__DENALI_PI_256__PI_TRAS_MIN_F2_WIDTH 9U

4653

#define LPDDR4__PI_TRAS_MIN_F2__REG DENALI_PI_256

4654

#define LPDDR4__PI_TRAS_MIN_F2__FLD LPDDR4__DENALI_PI_256__PI_TRAS_MIN_F2

4655

4656

#define LPDDR4__DENALI_PI_256__PI_TDQSCK_MAX_F2_MASK 0x000F0000U

4657

#define LPDDR4__DENALI_PI_256__PI_TDQSCK_MAX_F2_SHIFT 16U

4658

#define LPDDR4__DENALI_PI_256__PI_TDQSCK_MAX_F2_WIDTH 4U

4659

#define LPDDR4__PI_TDQSCK_MAX_F2__REG DENALI_PI_256

4660

#define LPDDR4__PI_TDQSCK_MAX_F2__FLD LPDDR4__DENALI_PI_256__PI_TDQSCK_MAX_F2

4661

4662

#define LPDDR4__DENALI_PI_256__PI_TCCDMW_F2_MASK 0x3F000000U

4663

#define LPDDR4__DENALI_PI_256__PI_TCCDMW_F2_SHIFT 24U

4664

#define LPDDR4__DENALI_PI_256__PI_TCCDMW_F2_WIDTH 6U

4665

#define LPDDR4__PI_TCCDMW_F2__REG DENALI_PI_256

4666

#define LPDDR4__PI_TCCDMW_F2__FLD LPDDR4__DENALI_PI_256__PI_TCCDMW_F2

4667

4668

#define LPDDR4__DENALI_PI_257_READ_MASK 0xFFFFFFFFU

4669

#define LPDDR4__DENALI_PI_257_WRITE_MASK 0xFFFFFFFFU

4670

#define LPDDR4__DENALI_PI_257__PI_TSR_F2_MASK 0x000000FFU

4671

#define LPDDR4__DENALI_PI_257__PI_TSR_F2_SHIFT 0U

4672

#define LPDDR4__DENALI_PI_257__PI_TSR_F2_WIDTH 8U

4673

#define LPDDR4__PI_TSR_F2__REG DENALI_PI_257

4674

#define LPDDR4__PI_TSR_F2__FLD LPDDR4__DENALI_PI_257__PI_TSR_F2

4675

4676

#define LPDDR4__DENALI_PI_257__PI_TMRD_F2_MASK 0x0000FF00U

4677

#define LPDDR4__DENALI_PI_257__PI_TMRD_F2_SHIFT 8U

4678

#define LPDDR4__DENALI_PI_257__PI_TMRD_F2_WIDTH 8U

4679

#define LPDDR4__PI_TMRD_F2__REG DENALI_PI_257

4680

#define LPDDR4__PI_TMRD_F2__FLD LPDDR4__DENALI_PI_257__PI_TMRD_F2

4681

4682

#define LPDDR4__DENALI_PI_257__PI_TMRW_F2_MASK 0x00FF0000U

4683

#define LPDDR4__DENALI_PI_257__PI_TMRW_F2_SHIFT 16U

4684

#define LPDDR4__DENALI_PI_257__PI_TMRW_F2_WIDTH 8U

4685

#define LPDDR4__PI_TMRW_F2__REG DENALI_PI_257

4686

#define LPDDR4__PI_TMRW_F2__FLD LPDDR4__DENALI_PI_257__PI_TMRW_F2

4687

4688

#define LPDDR4__DENALI_PI_257__PI_TMOD_F2_MASK 0xFF000000U

4689

#define LPDDR4__DENALI_PI_257__PI_TMOD_F2_SHIFT 24U

4690

#define LPDDR4__DENALI_PI_257__PI_TMOD_F2_WIDTH 8U

4691

#define LPDDR4__PI_TMOD_F2__REG DENALI_PI_257

4692

#define LPDDR4__PI_TMOD_F2__FLD LPDDR4__DENALI_PI_257__PI_TMOD_F2

4693

4694

#define LPDDR4__DENALI_PI_258_READ_MASK 0x0000FFFFU

4695

#define LPDDR4__DENALI_PI_258_WRITE_MASK 0x0000FFFFU

4696

#define LPDDR4__DENALI_PI_258__PI_TMOD_PAR_F2_MASK 0x000000FFU

4697

#define LPDDR4__DENALI_PI_258__PI_TMOD_PAR_F2_SHIFT 0U

4698

#define LPDDR4__DENALI_PI_258__PI_TMOD_PAR_F2_WIDTH 8U

4699

#define LPDDR4__PI_TMOD_PAR_F2__REG DENALI_PI_258

4700

#define LPDDR4__PI_TMOD_PAR_F2__FLD LPDDR4__DENALI_PI_258__PI_TMOD_PAR_F2

4701

4702

#define LPDDR4__DENALI_PI_258__PI_TMRD_PAR_F2_MASK 0x0000FF00U

4703

#define LPDDR4__DENALI_PI_258__PI_TMRD_PAR_F2_SHIFT 8U

4704

#define LPDDR4__DENALI_PI_258__PI_TMRD_PAR_F2_WIDTH 8U

4705

#define LPDDR4__PI_TMRD_PAR_F2__REG DENALI_PI_258

4706

#define LPDDR4__PI_TMRD_PAR_F2__FLD LPDDR4__DENALI_PI_258__PI_TMRD_PAR_F2

4707

4708

#define LPDDR4__DENALI_PI_259_READ_MASK 0x001FFFFFU

4709

#define LPDDR4__DENALI_PI_259_WRITE_MASK 0x001FFFFFU

4710

#define LPDDR4__DENALI_PI_259__PI_TDFI_CTRLUPD_MAX_F0_MASK 0x001FFFFFU

4711

#define LPDDR4__DENALI_PI_259__PI_TDFI_CTRLUPD_MAX_F0_SHIFT 0U

4712

#define LPDDR4__DENALI_PI_259__PI_TDFI_CTRLUPD_MAX_F0_WIDTH 21U

4713

#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F0__REG DENALI_PI_259

4714

#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F0__FLD LPDDR4__DENALI_PI_259__PI_TDFI_CTRLUPD_MAX_F0

4715

4716

#define LPDDR4__DENALI_PI_260_READ_MASK 0xFFFFFFFFU

4717

#define LPDDR4__DENALI_PI_260_WRITE_MASK 0xFFFFFFFFU

4718

#define LPDDR4__DENALI_PI_260__PI_TDFI_CTRLUPD_INTERVAL_F0_MASK 0xFFFFFFFFU

4719

#define LPDDR4__DENALI_PI_260__PI_TDFI_CTRLUPD_INTERVAL_F0_SHIFT 0U

4720

#define LPDDR4__DENALI_PI_260__PI_TDFI_CTRLUPD_INTERVAL_F0_WIDTH 32U

4721

#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F0__REG DENALI_PI_260

4722

#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F0__FLD LPDDR4__DENALI_PI_260__PI_TDFI_CTRLUPD_INTERVAL_F0

4723

4724

#define LPDDR4__DENALI_PI_261_READ_MASK 0x001FFFFFU

4725

#define LPDDR4__DENALI_PI_261_WRITE_MASK 0x001FFFFFU

4726

#define LPDDR4__DENALI_PI_261__PI_TDFI_CTRLUPD_MAX_F1_MASK 0x001FFFFFU

4727

#define LPDDR4__DENALI_PI_261__PI_TDFI_CTRLUPD_MAX_F1_SHIFT 0U

4728

#define LPDDR4__DENALI_PI_261__PI_TDFI_CTRLUPD_MAX_F1_WIDTH 21U

4729

#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F1__REG DENALI_PI_261

4730

#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F1__FLD LPDDR4__DENALI_PI_261__PI_TDFI_CTRLUPD_MAX_F1

4731

4732

#define LPDDR4__DENALI_PI_262_READ_MASK 0xFFFFFFFFU

4733

#define LPDDR4__DENALI_PI_262_WRITE_MASK 0xFFFFFFFFU

4734

#define LPDDR4__DENALI_PI_262__PI_TDFI_CTRLUPD_INTERVAL_F1_MASK 0xFFFFFFFFU

4735

#define LPDDR4__DENALI_PI_262__PI_TDFI_CTRLUPD_INTERVAL_F1_SHIFT 0U

4736

#define LPDDR4__DENALI_PI_262__PI_TDFI_CTRLUPD_INTERVAL_F1_WIDTH 32U

4737

#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F1__REG DENALI_PI_262

4738

#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F1__FLD LPDDR4__DENALI_PI_262__PI_TDFI_CTRLUPD_INTERVAL_F1

4739

4740

#define LPDDR4__DENALI_PI_263_READ_MASK 0x001FFFFFU

4741

#define LPDDR4__DENALI_PI_263_WRITE_MASK 0x001FFFFFU

4742

#define LPDDR4__DENALI_PI_263__PI_TDFI_CTRLUPD_MAX_F2_MASK 0x001FFFFFU

4743

#define LPDDR4__DENALI_PI_263__PI_TDFI_CTRLUPD_MAX_F2_SHIFT 0U

4744

#define LPDDR4__DENALI_PI_263__PI_TDFI_CTRLUPD_MAX_F2_WIDTH 21U

4745

#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F2__REG DENALI_PI_263

4746

#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F2__FLD LPDDR4__DENALI_PI_263__PI_TDFI_CTRLUPD_MAX_F2

4747

4748

#define LPDDR4__DENALI_PI_264_READ_MASK 0xFFFFFFFFU

4749

#define LPDDR4__DENALI_PI_264_WRITE_MASK 0xFFFFFFFFU

4750

#define LPDDR4__DENALI_PI_264__PI_TDFI_CTRLUPD_INTERVAL_F2_MASK 0xFFFFFFFFU

4751

#define LPDDR4__DENALI_PI_264__PI_TDFI_CTRLUPD_INTERVAL_F2_SHIFT 0U

4752

#define LPDDR4__DENALI_PI_264__PI_TDFI_CTRLUPD_INTERVAL_F2_WIDTH 32U

4753

#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F2__REG DENALI_PI_264

4754

#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F2__FLD LPDDR4__DENALI_PI_264__PI_TDFI_CTRLUPD_INTERVAL_F2

4755

4756

#define LPDDR4__DENALI_PI_265_READ_MASK 0xFFFFFFFFU

4757

#define LPDDR4__DENALI_PI_265_WRITE_MASK 0xFFFFFFFFU

4758

#define LPDDR4__DENALI_PI_265__PI_TXSR_F0_MASK 0x0000FFFFU

4759

#define LPDDR4__DENALI_PI_265__PI_TXSR_F0_SHIFT 0U

4760

#define LPDDR4__DENALI_PI_265__PI_TXSR_F0_WIDTH 16U

4761

#define LPDDR4__PI_TXSR_F0__REG DENALI_PI_265

4762

#define LPDDR4__PI_TXSR_F0__FLD LPDDR4__DENALI_PI_265__PI_TXSR_F0

4763

4764

#define LPDDR4__DENALI_PI_265__PI_TXSR_F1_MASK 0xFFFF0000U

4765

#define LPDDR4__DENALI_PI_265__PI_TXSR_F1_SHIFT 16U

4766

#define LPDDR4__DENALI_PI_265__PI_TXSR_F1_WIDTH 16U

4767

#define LPDDR4__PI_TXSR_F1__REG DENALI_PI_265

4768

#define LPDDR4__PI_TXSR_F1__FLD LPDDR4__DENALI_PI_265__PI_TXSR_F1

4769

4770

#define LPDDR4__DENALI_PI_266_READ_MASK 0x3F3FFFFFU

4771

#define LPDDR4__DENALI_PI_266_WRITE_MASK 0x3F3FFFFFU

4772

#define LPDDR4__DENALI_PI_266__PI_TXSR_F2_MASK 0x0000FFFFU

4773

#define LPDDR4__DENALI_PI_266__PI_TXSR_F2_SHIFT 0U

4774

#define LPDDR4__DENALI_PI_266__PI_TXSR_F2_WIDTH 16U

4775

#define LPDDR4__PI_TXSR_F2__REG DENALI_PI_266

4776

#define LPDDR4__PI_TXSR_F2__FLD LPDDR4__DENALI_PI_266__PI_TXSR_F2

4777

4778

#define LPDDR4__DENALI_PI_266__PI_TEXCKE_F0_MASK 0x003F0000U

4779

#define LPDDR4__DENALI_PI_266__PI_TEXCKE_F0_SHIFT 16U

4780

#define LPDDR4__DENALI_PI_266__PI_TEXCKE_F0_WIDTH 6U

4781

#define LPDDR4__PI_TEXCKE_F0__REG DENALI_PI_266

4782

#define LPDDR4__PI_TEXCKE_F0__FLD LPDDR4__DENALI_PI_266__PI_TEXCKE_F0

4783

4784

#define LPDDR4__DENALI_PI_266__PI_TEXCKE_F1_MASK 0x3F000000U

4785

#define LPDDR4__DENALI_PI_266__PI_TEXCKE_F1_SHIFT 24U

4786

#define LPDDR4__DENALI_PI_266__PI_TEXCKE_F1_WIDTH 6U

4787

#define LPDDR4__PI_TEXCKE_F1__REG DENALI_PI_266

4788

#define LPDDR4__PI_TEXCKE_F1__FLD LPDDR4__DENALI_PI_266__PI_TEXCKE_F1

4789

4790

#define LPDDR4__DENALI_PI_267_READ_MASK 0x00FFFF3FU

4791

#define LPDDR4__DENALI_PI_267_WRITE_MASK 0x00FFFF3FU

4792

#define LPDDR4__DENALI_PI_267__PI_TEXCKE_F2_MASK 0x0000003FU

4793

#define LPDDR4__DENALI_PI_267__PI_TEXCKE_F2_SHIFT 0U

4794

#define LPDDR4__DENALI_PI_267__PI_TEXCKE_F2_WIDTH 6U

4795

#define LPDDR4__PI_TEXCKE_F2__REG DENALI_PI_267

4796

#define LPDDR4__PI_TEXCKE_F2__FLD LPDDR4__DENALI_PI_267__PI_TEXCKE_F2

4797

4798

#define LPDDR4__DENALI_PI_267__PI_TDLL_F0_MASK 0x00FFFF00U

4799

#define LPDDR4__DENALI_PI_267__PI_TDLL_F0_SHIFT 8U

4800

#define LPDDR4__DENALI_PI_267__PI_TDLL_F0_WIDTH 16U

4801

#define LPDDR4__PI_TDLL_F0__REG DENALI_PI_267

4802

#define LPDDR4__PI_TDLL_F0__FLD LPDDR4__DENALI_PI_267__PI_TDLL_F0

4803

4804

#define LPDDR4__DENALI_PI_268_READ_MASK 0xFFFFFFFFU

4805

#define LPDDR4__DENALI_PI_268_WRITE_MASK 0xFFFFFFFFU

4806

#define LPDDR4__DENALI_PI_268__PI_TDLL_F1_MASK 0x0000FFFFU

4807

#define LPDDR4__DENALI_PI_268__PI_TDLL_F1_SHIFT 0U

4808

#define LPDDR4__DENALI_PI_268__PI_TDLL_F1_WIDTH 16U

4809

#define LPDDR4__PI_TDLL_F1__REG DENALI_PI_268

4810

#define LPDDR4__PI_TDLL_F1__FLD LPDDR4__DENALI_PI_268__PI_TDLL_F1

4811

4812

#define LPDDR4__DENALI_PI_268__PI_TDLL_F2_MASK 0xFFFF0000U

4813

#define LPDDR4__DENALI_PI_268__PI_TDLL_F2_SHIFT 16U

4814

#define LPDDR4__DENALI_PI_268__PI_TDLL_F2_WIDTH 16U

4815

#define LPDDR4__PI_TDLL_F2__REG DENALI_PI_268

4816

#define LPDDR4__PI_TDLL_F2__FLD LPDDR4__DENALI_PI_268__PI_TDLL_F2

4817

4818

#define LPDDR4__DENALI_PI_269_READ_MASK 0xFFFFFFFFU

4819

#define LPDDR4__DENALI_PI_269_WRITE_MASK 0xFFFFFFFFU

4820

#define LPDDR4__DENALI_PI_269__PI_TCKSRX_F0_MASK 0x000000FFU

4821

#define LPDDR4__DENALI_PI_269__PI_TCKSRX_F0_SHIFT 0U

4822

#define LPDDR4__DENALI_PI_269__PI_TCKSRX_F0_WIDTH 8U

4823

#define LPDDR4__PI_TCKSRX_F0__REG DENALI_PI_269

4824

#define LPDDR4__PI_TCKSRX_F0__FLD LPDDR4__DENALI_PI_269__PI_TCKSRX_F0

4825

4826

#define LPDDR4__DENALI_PI_269__PI_TCKSRE_F0_MASK 0x0000FF00U

4827

#define LPDDR4__DENALI_PI_269__PI_TCKSRE_F0_SHIFT 8U

4828

#define LPDDR4__DENALI_PI_269__PI_TCKSRE_F0_WIDTH 8U

4829

#define LPDDR4__PI_TCKSRE_F0__REG DENALI_PI_269

4830

#define LPDDR4__PI_TCKSRE_F0__FLD LPDDR4__DENALI_PI_269__PI_TCKSRE_F0

4831

4832

#define LPDDR4__DENALI_PI_269__PI_TCKSRX_F1_MASK 0x00FF0000U

4833

#define LPDDR4__DENALI_PI_269__PI_TCKSRX_F1_SHIFT 16U

4834

#define LPDDR4__DENALI_PI_269__PI_TCKSRX_F1_WIDTH 8U

4835

#define LPDDR4__PI_TCKSRX_F1__REG DENALI_PI_269

4836

#define LPDDR4__PI_TCKSRX_F1__FLD LPDDR4__DENALI_PI_269__PI_TCKSRX_F1

4837

4838

#define LPDDR4__DENALI_PI_269__PI_TCKSRE_F1_MASK 0xFF000000U

4839

#define LPDDR4__DENALI_PI_269__PI_TCKSRE_F1_SHIFT 24U

4840

#define LPDDR4__DENALI_PI_269__PI_TCKSRE_F1_WIDTH 8U

4841

#define LPDDR4__PI_TCKSRE_F1__REG DENALI_PI_269

4842

#define LPDDR4__PI_TCKSRE_F1__FLD LPDDR4__DENALI_PI_269__PI_TCKSRE_F1

4843

4844

#define LPDDR4__DENALI_PI_270_READ_MASK 0x0000FFFFU

4845

#define LPDDR4__DENALI_PI_270_WRITE_MASK 0x0000FFFFU

4846

#define LPDDR4__DENALI_PI_270__PI_TCKSRX_F2_MASK 0x000000FFU

4847

#define LPDDR4__DENALI_PI_270__PI_TCKSRX_F2_SHIFT 0U

4848

#define LPDDR4__DENALI_PI_270__PI_TCKSRX_F2_WIDTH 8U

4849

#define LPDDR4__PI_TCKSRX_F2__REG DENALI_PI_270

4850

#define LPDDR4__PI_TCKSRX_F2__FLD LPDDR4__DENALI_PI_270__PI_TCKSRX_F2

4851

4852

#define LPDDR4__DENALI_PI_270__PI_TCKSRE_F2_MASK 0x0000FF00U

4853

#define LPDDR4__DENALI_PI_270__PI_TCKSRE_F2_SHIFT 8U

4854

#define LPDDR4__DENALI_PI_270__PI_TCKSRE_F2_WIDTH 8U

4855

#define LPDDR4__PI_TCKSRE_F2__REG DENALI_PI_270

4856

#define LPDDR4__PI_TCKSRE_F2__FLD LPDDR4__DENALI_PI_270__PI_TCKSRE_F2

4857

4858

#define LPDDR4__DENALI_PI_271_READ_MASK 0x00FFFFFFU

4859

#define LPDDR4__DENALI_PI_271_WRITE_MASK 0x00FFFFFFU

4860

#define LPDDR4__DENALI_PI_271__PI_TINIT_F0_MASK 0x00FFFFFFU

4861

#define LPDDR4__DENALI_PI_271__PI_TINIT_F0_SHIFT 0U

4862

#define LPDDR4__DENALI_PI_271__PI_TINIT_F0_WIDTH 24U

4863

#define LPDDR4__PI_TINIT_F0__REG DENALI_PI_271

4864

#define LPDDR4__PI_TINIT_F0__FLD LPDDR4__DENALI_PI_271__PI_TINIT_F0

4865

4866

#define LPDDR4__DENALI_PI_272_READ_MASK 0x00FFFFFFU

4867

#define LPDDR4__DENALI_PI_272_WRITE_MASK 0x00FFFFFFU

4868

#define LPDDR4__DENALI_PI_272__PI_TINIT3_F0_MASK 0x00FFFFFFU

4869

#define LPDDR4__DENALI_PI_272__PI_TINIT3_F0_SHIFT 0U

4870

#define LPDDR4__DENALI_PI_272__PI_TINIT3_F0_WIDTH 24U

4871

#define LPDDR4__PI_TINIT3_F0__REG DENALI_PI_272

4872

#define LPDDR4__PI_TINIT3_F0__FLD LPDDR4__DENALI_PI_272__PI_TINIT3_F0

4873

4874

#define LPDDR4__DENALI_PI_273_READ_MASK 0x00FFFFFFU

4875

#define LPDDR4__DENALI_PI_273_WRITE_MASK 0x00FFFFFFU

4876

#define LPDDR4__DENALI_PI_273__PI_TINIT4_F0_MASK 0x00FFFFFFU

4877

#define LPDDR4__DENALI_PI_273__PI_TINIT4_F0_SHIFT 0U

4878

#define LPDDR4__DENALI_PI_273__PI_TINIT4_F0_WIDTH 24U

4879

#define LPDDR4__PI_TINIT4_F0__REG DENALI_PI_273

4880

#define LPDDR4__PI_TINIT4_F0__FLD LPDDR4__DENALI_PI_273__PI_TINIT4_F0

4881

4882

#define LPDDR4__DENALI_PI_274_READ_MASK 0x00FFFFFFU

4883

#define LPDDR4__DENALI_PI_274_WRITE_MASK 0x00FFFFFFU

4884

#define LPDDR4__DENALI_PI_274__PI_TINIT5_F0_MASK 0x00FFFFFFU

4885

#define LPDDR4__DENALI_PI_274__PI_TINIT5_F0_SHIFT 0U

4886

#define LPDDR4__DENALI_PI_274__PI_TINIT5_F0_WIDTH 24U

4887

#define LPDDR4__PI_TINIT5_F0__REG DENALI_PI_274

4888

#define LPDDR4__PI_TINIT5_F0__FLD LPDDR4__DENALI_PI_274__PI_TINIT5_F0

4889

4890

#define LPDDR4__DENALI_PI_275_READ_MASK 0x0000FFFFU

4891

#define LPDDR4__DENALI_PI_275_WRITE_MASK 0x0000FFFFU

4892

#define LPDDR4__DENALI_PI_275__PI_TXSNR_F0_MASK 0x0000FFFFU

4893

#define LPDDR4__DENALI_PI_275__PI_TXSNR_F0_SHIFT 0U

4894

#define LPDDR4__DENALI_PI_275__PI_TXSNR_F0_WIDTH 16U

4895

#define LPDDR4__PI_TXSNR_F0__REG DENALI_PI_275

4896

#define LPDDR4__PI_TXSNR_F0__FLD LPDDR4__DENALI_PI_275__PI_TXSNR_F0

4897

4898

#define LPDDR4__DENALI_PI_276_READ_MASK 0x00FFFFFFU

4899

#define LPDDR4__DENALI_PI_276_WRITE_MASK 0x00FFFFFFU

4900

#define LPDDR4__DENALI_PI_276__PI_TINIT_F1_MASK 0x00FFFFFFU

4901

#define LPDDR4__DENALI_PI_276__PI_TINIT_F1_SHIFT 0U

4902

#define LPDDR4__DENALI_PI_276__PI_TINIT_F1_WIDTH 24U

4903

#define LPDDR4__PI_TINIT_F1__REG DENALI_PI_276

4904

#define LPDDR4__PI_TINIT_F1__FLD LPDDR4__DENALI_PI_276__PI_TINIT_F1

4905

4906

#define LPDDR4__DENALI_PI_277_READ_MASK 0x00FFFFFFU

4907

#define LPDDR4__DENALI_PI_277_WRITE_MASK 0x00FFFFFFU

4908

#define LPDDR4__DENALI_PI_277__PI_TINIT3_F1_MASK 0x00FFFFFFU

4909

#define LPDDR4__DENALI_PI_277__PI_TINIT3_F1_SHIFT 0U

4910

#define LPDDR4__DENALI_PI_277__PI_TINIT3_F1_WIDTH 24U

4911

#define LPDDR4__PI_TINIT3_F1__REG DENALI_PI_277

4912

#define LPDDR4__PI_TINIT3_F1__FLD LPDDR4__DENALI_PI_277__PI_TINIT3_F1

4913

4914

#define LPDDR4__DENALI_PI_278_READ_MASK 0x00FFFFFFU

4915

#define LPDDR4__DENALI_PI_278_WRITE_MASK 0x00FFFFFFU

4916

#define LPDDR4__DENALI_PI_278__PI_TINIT4_F1_MASK 0x00FFFFFFU

4917

#define LPDDR4__DENALI_PI_278__PI_TINIT4_F1_SHIFT 0U

4918

#define LPDDR4__DENALI_PI_278__PI_TINIT4_F1_WIDTH 24U

4919

#define LPDDR4__PI_TINIT4_F1__REG DENALI_PI_278

4920

#define LPDDR4__PI_TINIT4_F1__FLD LPDDR4__DENALI_PI_278__PI_TINIT4_F1

4921

4922

#define LPDDR4__DENALI_PI_279_READ_MASK 0x00FFFFFFU

4923

#define LPDDR4__DENALI_PI_279_WRITE_MASK 0x00FFFFFFU

4924

#define LPDDR4__DENALI_PI_279__PI_TINIT5_F1_MASK 0x00FFFFFFU

4925

#define LPDDR4__DENALI_PI_279__PI_TINIT5_F1_SHIFT 0U

4926

#define LPDDR4__DENALI_PI_279__PI_TINIT5_F1_WIDTH 24U

4927

#define LPDDR4__PI_TINIT5_F1__REG DENALI_PI_279

4928

#define LPDDR4__PI_TINIT5_F1__FLD LPDDR4__DENALI_PI_279__PI_TINIT5_F1

4929

4930

#define LPDDR4__DENALI_PI_280_READ_MASK 0x0000FFFFU

4931

#define LPDDR4__DENALI_PI_280_WRITE_MASK 0x0000FFFFU

4932

#define LPDDR4__DENALI_PI_280__PI_TXSNR_F1_MASK 0x0000FFFFU

4933

#define LPDDR4__DENALI_PI_280__PI_TXSNR_F1_SHIFT 0U

4934

#define LPDDR4__DENALI_PI_280__PI_TXSNR_F1_WIDTH 16U

4935

#define LPDDR4__PI_TXSNR_F1__REG DENALI_PI_280

4936

#define LPDDR4__PI_TXSNR_F1__FLD LPDDR4__DENALI_PI_280__PI_TXSNR_F1

4937

4938

#define LPDDR4__DENALI_PI_281_READ_MASK 0x00FFFFFFU

4939

#define LPDDR4__DENALI_PI_281_WRITE_MASK 0x00FFFFFFU

4940

#define LPDDR4__DENALI_PI_281__PI_TINIT_F2_MASK 0x00FFFFFFU

4941

#define LPDDR4__DENALI_PI_281__PI_TINIT_F2_SHIFT 0U

4942

#define LPDDR4__DENALI_PI_281__PI_TINIT_F2_WIDTH 24U

4943

#define LPDDR4__PI_TINIT_F2__REG DENALI_PI_281

4944

#define LPDDR4__PI_TINIT_F2__FLD LPDDR4__DENALI_PI_281__PI_TINIT_F2

4945

4946

#define LPDDR4__DENALI_PI_282_READ_MASK 0x00FFFFFFU

4947

#define LPDDR4__DENALI_PI_282_WRITE_MASK 0x00FFFFFFU

4948

#define LPDDR4__DENALI_PI_282__PI_TINIT3_F2_MASK 0x00FFFFFFU

4949

#define LPDDR4__DENALI_PI_282__PI_TINIT3_F2_SHIFT 0U

4950

#define LPDDR4__DENALI_PI_282__PI_TINIT3_F2_WIDTH 24U

4951

#define LPDDR4__PI_TINIT3_F2__REG DENALI_PI_282

4952

#define LPDDR4__PI_TINIT3_F2__FLD LPDDR4__DENALI_PI_282__PI_TINIT3_F2

4953

4954

#define LPDDR4__DENALI_PI_283_READ_MASK 0x00FFFFFFU

4955

#define LPDDR4__DENALI_PI_283_WRITE_MASK 0x00FFFFFFU

4956

#define LPDDR4__DENALI_PI_283__PI_TINIT4_F2_MASK 0x00FFFFFFU

4957

#define LPDDR4__DENALI_PI_283__PI_TINIT4_F2_SHIFT 0U

4958

#define LPDDR4__DENALI_PI_283__PI_TINIT4_F2_WIDTH 24U

4959

#define LPDDR4__PI_TINIT4_F2__REG DENALI_PI_283

4960

#define LPDDR4__PI_TINIT4_F2__FLD LPDDR4__DENALI_PI_283__PI_TINIT4_F2

4961

4962

#define LPDDR4__DENALI_PI_284_READ_MASK 0x00FFFFFFU

4963

#define LPDDR4__DENALI_PI_284_WRITE_MASK 0x00FFFFFFU

4964

#define LPDDR4__DENALI_PI_284__PI_TINIT5_F2_MASK 0x00FFFFFFU

4965

#define LPDDR4__DENALI_PI_284__PI_TINIT5_F2_SHIFT 0U

4966

#define LPDDR4__DENALI_PI_284__PI_TINIT5_F2_WIDTH 24U

4967

#define LPDDR4__PI_TINIT5_F2__REG DENALI_PI_284

4968

#define LPDDR4__PI_TINIT5_F2__FLD LPDDR4__DENALI_PI_284__PI_TINIT5_F2

4969

4970

#define LPDDR4__DENALI_PI_285_READ_MASK 0x0FFFFFFFU

4971

#define LPDDR4__DENALI_PI_285_WRITE_MASK 0x0FFFFFFFU

4972

#define LPDDR4__DENALI_PI_285__PI_TXSNR_F2_MASK 0x0000FFFFU

4973

#define LPDDR4__DENALI_PI_285__PI_TXSNR_F2_SHIFT 0U

4974

#define LPDDR4__DENALI_PI_285__PI_TXSNR_F2_WIDTH 16U

4975

#define LPDDR4__PI_TXSNR_F2__REG DENALI_PI_285

4976

#define LPDDR4__PI_TXSNR_F2__FLD LPDDR4__DENALI_PI_285__PI_TXSNR_F2

4977

4978

#define LPDDR4__DENALI_PI_285__PI_RESERVED54_MASK 0x0FFF0000U

4979

#define LPDDR4__DENALI_PI_285__PI_RESERVED54_SHIFT 16U

4980

#define LPDDR4__DENALI_PI_285__PI_RESERVED54_WIDTH 12U

4981

#define LPDDR4__PI_RESERVED54__REG DENALI_PI_285

4982

#define LPDDR4__PI_RESERVED54__FLD LPDDR4__DENALI_PI_285__PI_RESERVED54

4983

4984

#define LPDDR4__DENALI_PI_286_READ_MASK 0x0FFF0FFFU

4985

#define LPDDR4__DENALI_PI_286_WRITE_MASK 0x0FFF0FFFU

4986

#define LPDDR4__DENALI_PI_286__PI_RESERVED55_MASK 0x00000FFFU

4987

#define LPDDR4__DENALI_PI_286__PI_RESERVED55_SHIFT 0U

4988

#define LPDDR4__DENALI_PI_286__PI_RESERVED55_WIDTH 12U

4989

#define LPDDR4__PI_RESERVED55__REG DENALI_PI_286

4990

#define LPDDR4__PI_RESERVED55__FLD LPDDR4__DENALI_PI_286__PI_RESERVED55

4991

4992

#define LPDDR4__DENALI_PI_286__PI_TZQCAL_F0_MASK 0x0FFF0000U

4993

#define LPDDR4__DENALI_PI_286__PI_TZQCAL_F0_SHIFT 16U

4994

#define LPDDR4__DENALI_PI_286__PI_TZQCAL_F0_WIDTH 12U

4995

#define LPDDR4__PI_TZQCAL_F0__REG DENALI_PI_286

4996

#define LPDDR4__PI_TZQCAL_F0__FLD LPDDR4__DENALI_PI_286__PI_TZQCAL_F0

4997

4998

#define LPDDR4__DENALI_PI_287_READ_MASK 0x000FFF7FU

4999

#define LPDDR4__DENALI_PI_287_WRITE_MASK 0x000FFF7FU

5000

#define LPDDR4__DENALI_PI_287__PI_TZQLAT_F0_MASK 0x0000007FU

5001

#define LPDDR4__DENALI_PI_287__PI_TZQLAT_F0_SHIFT 0U

5002

#define LPDDR4__DENALI_PI_287__PI_TZQLAT_F0_WIDTH 7U

5003

#define LPDDR4__PI_TZQLAT_F0__REG DENALI_PI_287

5004

#define LPDDR4__PI_TZQLAT_F0__FLD LPDDR4__DENALI_PI_287__PI_TZQLAT_F0

5005

5006

#define LPDDR4__DENALI_PI_287__PI_RESERVED56_MASK 0x000FFF00U

5007

#define LPDDR4__DENALI_PI_287__PI_RESERVED56_SHIFT 8U

5008

#define LPDDR4__DENALI_PI_287__PI_RESERVED56_WIDTH 12U

5009

#define LPDDR4__PI_RESERVED56__REG DENALI_PI_287

5010

#define LPDDR4__PI_RESERVED56__FLD LPDDR4__DENALI_PI_287__PI_RESERVED56

5011

5012

#define LPDDR4__DENALI_PI_288_READ_MASK 0x0FFF0FFFU

5013

#define LPDDR4__DENALI_PI_288_WRITE_MASK 0x0FFF0FFFU

5014

#define LPDDR4__DENALI_PI_288__PI_RESERVED57_MASK 0x00000FFFU

5015

#define LPDDR4__DENALI_PI_288__PI_RESERVED57_SHIFT 0U

5016

#define LPDDR4__DENALI_PI_288__PI_RESERVED57_WIDTH 12U

5017

#define LPDDR4__PI_RESERVED57__REG DENALI_PI_288

5018

#define LPDDR4__PI_RESERVED57__FLD LPDDR4__DENALI_PI_288__PI_RESERVED57

5019

5020

#define LPDDR4__DENALI_PI_288__PI_TZQCAL_F1_MASK 0x0FFF0000U

5021

#define LPDDR4__DENALI_PI_288__PI_TZQCAL_F1_SHIFT 16U

5022

#define LPDDR4__DENALI_PI_288__PI_TZQCAL_F1_WIDTH 12U

5023

#define LPDDR4__PI_TZQCAL_F1__REG DENALI_PI_288

5024

#define LPDDR4__PI_TZQCAL_F1__FLD LPDDR4__DENALI_PI_288__PI_TZQCAL_F1

5025

5026

#define LPDDR4__DENALI_PI_289_READ_MASK 0x000FFF7FU

5027

#define LPDDR4__DENALI_PI_289_WRITE_MASK 0x000FFF7FU

5028

#define LPDDR4__DENALI_PI_289__PI_TZQLAT_F1_MASK 0x0000007FU

5029

#define LPDDR4__DENALI_PI_289__PI_TZQLAT_F1_SHIFT 0U

5030

#define LPDDR4__DENALI_PI_289__PI_TZQLAT_F1_WIDTH 7U

5031

#define LPDDR4__PI_TZQLAT_F1__REG DENALI_PI_289

5032

#define LPDDR4__PI_TZQLAT_F1__FLD LPDDR4__DENALI_PI_289__PI_TZQLAT_F1

5033

5034

#define LPDDR4__DENALI_PI_289__PI_RESERVED58_MASK 0x000FFF00U

5035

#define LPDDR4__DENALI_PI_289__PI_RESERVED58_SHIFT 8U

5036

#define LPDDR4__DENALI_PI_289__PI_RESERVED58_WIDTH 12U

5037

#define LPDDR4__PI_RESERVED58__REG DENALI_PI_289

5038

#define LPDDR4__PI_RESERVED58__FLD LPDDR4__DENALI_PI_289__PI_RESERVED58

5039

5040

#define LPDDR4__DENALI_PI_290_READ_MASK 0x0FFF0FFFU

5041

#define LPDDR4__DENALI_PI_290_WRITE_MASK 0x0FFF0FFFU

5042

#define LPDDR4__DENALI_PI_290__PI_RESERVED59_MASK 0x00000FFFU

5043

#define LPDDR4__DENALI_PI_290__PI_RESERVED59_SHIFT 0U

5044

#define LPDDR4__DENALI_PI_290__PI_RESERVED59_WIDTH 12U

5045

#define LPDDR4__PI_RESERVED59__REG DENALI_PI_290

5046

#define LPDDR4__PI_RESERVED59__FLD LPDDR4__DENALI_PI_290__PI_RESERVED59

5047

5048

#define LPDDR4__DENALI_PI_290__PI_TZQCAL_F2_MASK 0x0FFF0000U

5049

#define LPDDR4__DENALI_PI_290__PI_TZQCAL_F2_SHIFT 16U

5050

#define LPDDR4__DENALI_PI_290__PI_TZQCAL_F2_WIDTH 12U

5051

#define LPDDR4__PI_TZQCAL_F2__REG DENALI_PI_290

5052

#define LPDDR4__PI_TZQCAL_F2__FLD LPDDR4__DENALI_PI_290__PI_TZQCAL_F2

5053

5054

#define LPDDR4__DENALI_PI_291_READ_MASK 0x000FFF7FU

5055

#define LPDDR4__DENALI_PI_291_WRITE_MASK 0x000FFF7FU

5056

#define LPDDR4__DENALI_PI_291__PI_TZQLAT_F2_MASK 0x0000007FU

5057

#define LPDDR4__DENALI_PI_291__PI_TZQLAT_F2_SHIFT 0U

5058

#define LPDDR4__DENALI_PI_291__PI_TZQLAT_F2_WIDTH 7U

5059

#define LPDDR4__PI_TZQLAT_F2__REG DENALI_PI_291

5060

#define LPDDR4__PI_TZQLAT_F2__FLD LPDDR4__DENALI_PI_291__PI_TZQLAT_F2

5061

5062

#define LPDDR4__DENALI_PI_291__PI_RESERVED60_MASK 0x000FFF00U

5063

#define LPDDR4__DENALI_PI_291__PI_RESERVED60_SHIFT 8U

5064

#define LPDDR4__DENALI_PI_291__PI_RESERVED60_WIDTH 12U

5065

#define LPDDR4__PI_RESERVED60__REG DENALI_PI_291

5066

#define LPDDR4__PI_RESERVED60__FLD LPDDR4__DENALI_PI_291__PI_RESERVED60

5067

5068

#define LPDDR4__DENALI_PI_292_READ_MASK 0x0FFF0FFFU

5069

#define LPDDR4__DENALI_PI_292_WRITE_MASK 0x0FFF0FFFU

5070

#define LPDDR4__DENALI_PI_292__PI_RESERVED61_MASK 0x00000FFFU

5071

#define LPDDR4__DENALI_PI_292__PI_RESERVED61_SHIFT 0U

5072

#define LPDDR4__DENALI_PI_292__PI_RESERVED61_WIDTH 12U

5073

#define LPDDR4__PI_RESERVED61__REG DENALI_PI_292

5074

#define LPDDR4__PI_RESERVED61__FLD LPDDR4__DENALI_PI_292__PI_RESERVED61

5075

5076

#define LPDDR4__DENALI_PI_292__PI_RESERVED62_MASK 0x0FFF0000U

5077

#define LPDDR4__DENALI_PI_292__PI_RESERVED62_SHIFT 16U

5078

#define LPDDR4__DENALI_PI_292__PI_RESERVED62_WIDTH 12U

5079

#define LPDDR4__PI_RESERVED62__REG DENALI_PI_292

5080

#define LPDDR4__PI_RESERVED62__FLD LPDDR4__DENALI_PI_292__PI_RESERVED62

5081

5082

#define LPDDR4__DENALI_PI_293_READ_MASK 0x030F0F0FU

5083

#define LPDDR4__DENALI_PI_293_WRITE_MASK 0x030F0F0FU

5084

#define LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F0_MASK 0x0000000FU

5085

#define LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F0_SHIFT 0U

5086

#define LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F0_WIDTH 4U

5087

#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F0__REG DENALI_PI_293

5088

#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F0__FLD LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F0

5089

5090

#define LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F1_MASK 0x00000F00U

5091

#define LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F1_SHIFT 8U

5092

#define LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F1_WIDTH 4U

5093

#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F1__REG DENALI_PI_293

5094

#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F1__FLD LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F1

5095

5096

#define LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F2_MASK 0x000F0000U

5097

#define LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F2_SHIFT 16U

5098

#define LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F2_WIDTH 4U

5099

#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F2__REG DENALI_PI_293

5100

#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F2__FLD LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F2

5101

5102

#define LPDDR4__DENALI_PI_293__PI_PREAMBLE_SUPPORT_F0_MASK 0x03000000U

5103

#define LPDDR4__DENALI_PI_293__PI_PREAMBLE_SUPPORT_F0_SHIFT 24U

5104

#define LPDDR4__DENALI_PI_293__PI_PREAMBLE_SUPPORT_F0_WIDTH 2U

5105

#define LPDDR4__PI_PREAMBLE_SUPPORT_F0__REG DENALI_PI_293

5106

#define LPDDR4__PI_PREAMBLE_SUPPORT_F0__FLD LPDDR4__DENALI_PI_293__PI_PREAMBLE_SUPPORT_F0

5107

5108

#define LPDDR4__DENALI_PI_294_READ_MASK 0x07070303U

5109

#define LPDDR4__DENALI_PI_294_WRITE_MASK 0x07070303U

5110

#define LPDDR4__DENALI_PI_294__PI_PREAMBLE_SUPPORT_F1_MASK 0x00000003U

5111

#define LPDDR4__DENALI_PI_294__PI_PREAMBLE_SUPPORT_F1_SHIFT 0U

5112

#define LPDDR4__DENALI_PI_294__PI_PREAMBLE_SUPPORT_F1_WIDTH 2U

5113

#define LPDDR4__PI_PREAMBLE_SUPPORT_F1__REG DENALI_PI_294

5114

#define LPDDR4__PI_PREAMBLE_SUPPORT_F1__FLD LPDDR4__DENALI_PI_294__PI_PREAMBLE_SUPPORT_F1

5115

5116

#define LPDDR4__DENALI_PI_294__PI_PREAMBLE_SUPPORT_F2_MASK 0x00000300U

5117

#define LPDDR4__DENALI_PI_294__PI_PREAMBLE_SUPPORT_F2_SHIFT 8U

5118

#define LPDDR4__DENALI_PI_294__PI_PREAMBLE_SUPPORT_F2_WIDTH 2U

5119

#define LPDDR4__PI_PREAMBLE_SUPPORT_F2__REG DENALI_PI_294

5120

#define LPDDR4__PI_PREAMBLE_SUPPORT_F2__FLD LPDDR4__DENALI_PI_294__PI_PREAMBLE_SUPPORT_F2

5121

5122

#define LPDDR4__DENALI_PI_294__PI_MEMDATA_RATIO_0_MASK 0x00070000U

5123

#define LPDDR4__DENALI_PI_294__PI_MEMDATA_RATIO_0_SHIFT 16U

5124

#define LPDDR4__DENALI_PI_294__PI_MEMDATA_RATIO_0_WIDTH 3U

5125

#define LPDDR4__PI_MEMDATA_RATIO_0__REG DENALI_PI_294

5126

#define LPDDR4__PI_MEMDATA_RATIO_0__FLD LPDDR4__DENALI_PI_294__PI_MEMDATA_RATIO_0

5127

5128

#define LPDDR4__DENALI_PI_294__PI_MEMDATA_RATIO_1_MASK 0x07000000U

5129

#define LPDDR4__DENALI_PI_294__PI_MEMDATA_RATIO_1_SHIFT 24U

5130

#define LPDDR4__DENALI_PI_294__PI_MEMDATA_RATIO_1_WIDTH 3U

5131

#define LPDDR4__PI_MEMDATA_RATIO_1__REG DENALI_PI_294

5132

#define LPDDR4__PI_MEMDATA_RATIO_1__FLD LPDDR4__DENALI_PI_294__PI_MEMDATA_RATIO_1

5133

5134

#define LPDDR4__DENALI_PI_295_READ_MASK 0x0F0F0707U

5135

#define LPDDR4__DENALI_PI_295_WRITE_MASK 0x0F0F0707U

5136

#define LPDDR4__DENALI_PI_295__PI_MEMDATA_RATIO_2_MASK 0x00000007U

5137

#define LPDDR4__DENALI_PI_295__PI_MEMDATA_RATIO_2_SHIFT 0U

5138

#define LPDDR4__DENALI_PI_295__PI_MEMDATA_RATIO_2_WIDTH 3U

5139

#define LPDDR4__PI_MEMDATA_RATIO_2__REG DENALI_PI_295

5140

#define LPDDR4__PI_MEMDATA_RATIO_2__FLD LPDDR4__DENALI_PI_295__PI_MEMDATA_RATIO_2

5141

5142

#define LPDDR4__DENALI_PI_295__PI_MEMDATA_RATIO_3_MASK 0x00000700U

5143

#define LPDDR4__DENALI_PI_295__PI_MEMDATA_RATIO_3_SHIFT 8U

5144

#define LPDDR4__DENALI_PI_295__PI_MEMDATA_RATIO_3_WIDTH 3U

5145

#define LPDDR4__PI_MEMDATA_RATIO_3__REG DENALI_PI_295

5146

#define LPDDR4__PI_MEMDATA_RATIO_3__FLD LPDDR4__DENALI_PI_295__PI_MEMDATA_RATIO_3

5147

5148

#define LPDDR4__DENALI_PI_295__PI_ODT_RD_MAP_CS0_MASK 0x000F0000U

5149

#define LPDDR4__DENALI_PI_295__PI_ODT_RD_MAP_CS0_SHIFT 16U

5150

#define LPDDR4__DENALI_PI_295__PI_ODT_RD_MAP_CS0_WIDTH 4U

5151

#define LPDDR4__PI_ODT_RD_MAP_CS0__REG DENALI_PI_295

5152

#define LPDDR4__PI_ODT_RD_MAP_CS0__FLD LPDDR4__DENALI_PI_295__PI_ODT_RD_MAP_CS0

5153

5154

#define LPDDR4__DENALI_PI_295__PI_ODT_WR_MAP_CS0_MASK 0x0F000000U

5155

#define LPDDR4__DENALI_PI_295__PI_ODT_WR_MAP_CS0_SHIFT 24U

5156

#define LPDDR4__DENALI_PI_295__PI_ODT_WR_MAP_CS0_WIDTH 4U

5157

#define LPDDR4__PI_ODT_WR_MAP_CS0__REG DENALI_PI_295

5158

#define LPDDR4__PI_ODT_WR_MAP_CS0__FLD LPDDR4__DENALI_PI_295__PI_ODT_WR_MAP_CS0

5159

5160

#define LPDDR4__DENALI_PI_296_READ_MASK 0x0F0F0F0FU

5161

#define LPDDR4__DENALI_PI_296_WRITE_MASK 0x0F0F0F0FU

5162

#define LPDDR4__DENALI_PI_296__PI_ODT_RD_MAP_CS1_MASK 0x0000000FU

5163

#define LPDDR4__DENALI_PI_296__PI_ODT_RD_MAP_CS1_SHIFT 0U

5164

#define LPDDR4__DENALI_PI_296__PI_ODT_RD_MAP_CS1_WIDTH 4U

5165

#define LPDDR4__PI_ODT_RD_MAP_CS1__REG DENALI_PI_296

5166

#define LPDDR4__PI_ODT_RD_MAP_CS1__FLD LPDDR4__DENALI_PI_296__PI_ODT_RD_MAP_CS1

5167

5168

#define LPDDR4__DENALI_PI_296__PI_ODT_WR_MAP_CS1_MASK 0x00000F00U

5169

#define LPDDR4__DENALI_PI_296__PI_ODT_WR_MAP_CS1_SHIFT 8U

5170

#define LPDDR4__DENALI_PI_296__PI_ODT_WR_MAP_CS1_WIDTH 4U

5171

#define LPDDR4__PI_ODT_WR_MAP_CS1__REG DENALI_PI_296

5172

#define LPDDR4__PI_ODT_WR_MAP_CS1__FLD LPDDR4__DENALI_PI_296__PI_ODT_WR_MAP_CS1

5173

5174

#define LPDDR4__DENALI_PI_296__PI_ODT_RD_MAP_CS2_MASK 0x000F0000U

5175

#define LPDDR4__DENALI_PI_296__PI_ODT_RD_MAP_CS2_SHIFT 16U

5176

#define LPDDR4__DENALI_PI_296__PI_ODT_RD_MAP_CS2_WIDTH 4U

5177

#define LPDDR4__PI_ODT_RD_MAP_CS2__REG DENALI_PI_296

5178

#define LPDDR4__PI_ODT_RD_MAP_CS2__FLD LPDDR4__DENALI_PI_296__PI_ODT_RD_MAP_CS2

5179

5180

#define LPDDR4__DENALI_PI_296__PI_ODT_WR_MAP_CS2_MASK 0x0F000000U

5181

#define LPDDR4__DENALI_PI_296__PI_ODT_WR_MAP_CS2_SHIFT 24U

5182

#define LPDDR4__DENALI_PI_296__PI_ODT_WR_MAP_CS2_WIDTH 4U

5183

#define LPDDR4__PI_ODT_WR_MAP_CS2__REG DENALI_PI_296

5184

#define LPDDR4__PI_ODT_WR_MAP_CS2__FLD LPDDR4__DENALI_PI_296__PI_ODT_WR_MAP_CS2

5185

5186

#define LPDDR4__DENALI_PI_297_READ_MASK 0x7F7F0F0FU

5187

#define LPDDR4__DENALI_PI_297_WRITE_MASK 0x7F7F0F0FU

5188

#define LPDDR4__DENALI_PI_297__PI_ODT_RD_MAP_CS3_MASK 0x0000000FU

5189

#define LPDDR4__DENALI_PI_297__PI_ODT_RD_MAP_CS3_SHIFT 0U

5190

#define LPDDR4__DENALI_PI_297__PI_ODT_RD_MAP_CS3_WIDTH 4U

5191

#define LPDDR4__PI_ODT_RD_MAP_CS3__REG DENALI_PI_297

5192

#define LPDDR4__PI_ODT_RD_MAP_CS3__FLD LPDDR4__DENALI_PI_297__PI_ODT_RD_MAP_CS3

5193

5194

#define LPDDR4__DENALI_PI_297__PI_ODT_WR_MAP_CS3_MASK 0x00000F00U

5195

#define LPDDR4__DENALI_PI_297__PI_ODT_WR_MAP_CS3_SHIFT 8U

5196

#define LPDDR4__DENALI_PI_297__PI_ODT_WR_MAP_CS3_WIDTH 4U

5197

#define LPDDR4__PI_ODT_WR_MAP_CS3__REG DENALI_PI_297

5198

#define LPDDR4__PI_ODT_WR_MAP_CS3__FLD LPDDR4__DENALI_PI_297__PI_ODT_WR_MAP_CS3

5199

5200

#define LPDDR4__DENALI_PI_297__PI_VREF_VAL_DEV0_0_MASK 0x007F0000U

5201

#define LPDDR4__DENALI_PI_297__PI_VREF_VAL_DEV0_0_SHIFT 16U

5202

#define LPDDR4__DENALI_PI_297__PI_VREF_VAL_DEV0_0_WIDTH 7U

5203

#define LPDDR4__PI_VREF_VAL_DEV0_0__REG DENALI_PI_297

5204

#define LPDDR4__PI_VREF_VAL_DEV0_0__FLD LPDDR4__DENALI_PI_297__PI_VREF_VAL_DEV0_0

5205

5206

#define LPDDR4__DENALI_PI_297__PI_VREF_VAL_DEV0_1_MASK 0x7F000000U

5207

#define LPDDR4__DENALI_PI_297__PI_VREF_VAL_DEV0_1_SHIFT 24U

5208

#define LPDDR4__DENALI_PI_297__PI_VREF_VAL_DEV0_1_WIDTH 7U

5209

#define LPDDR4__PI_VREF_VAL_DEV0_1__REG DENALI_PI_297

5210

#define LPDDR4__PI_VREF_VAL_DEV0_1__FLD LPDDR4__DENALI_PI_297__PI_VREF_VAL_DEV0_1

5211

5212

#define LPDDR4__DENALI_PI_298_READ_MASK 0x7F7F7F7FU

5213

#define LPDDR4__DENALI_PI_298_WRITE_MASK 0x7F7F7F7FU

5214

#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV0_2_MASK 0x0000007FU

5215

#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV0_2_SHIFT 0U

5216

#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV0_2_WIDTH 7U

5217

#define LPDDR4__PI_VREF_VAL_DEV0_2__REG DENALI_PI_298

5218

#define LPDDR4__PI_VREF_VAL_DEV0_2__FLD LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV0_2

5219

5220

#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV0_3_MASK 0x00007F00U

5221

#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV0_3_SHIFT 8U

5222

#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV0_3_WIDTH 7U

5223

#define LPDDR4__PI_VREF_VAL_DEV0_3__REG DENALI_PI_298

5224

#define LPDDR4__PI_VREF_VAL_DEV0_3__FLD LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV0_3

5225

5226

#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV1_0_MASK 0x007F0000U

5227

#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV1_0_SHIFT 16U

5228

#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV1_0_WIDTH 7U

5229

#define LPDDR4__PI_VREF_VAL_DEV1_0__REG DENALI_PI_298

5230

#define LPDDR4__PI_VREF_VAL_DEV1_0__FLD LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV1_0

5231

5232

#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV1_1_MASK 0x7F000000U

5233

#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV1_1_SHIFT 24U

5234

#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV1_1_WIDTH 7U

5235

#define LPDDR4__PI_VREF_VAL_DEV1_1__REG DENALI_PI_298

5236

#define LPDDR4__PI_VREF_VAL_DEV1_1__FLD LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV1_1

5237

5238

#define LPDDR4__DENALI_PI_299_READ_MASK 0x7F7F7F7FU

5239

#define LPDDR4__DENALI_PI_299_WRITE_MASK 0x7F7F7F7FU

5240

#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV1_2_MASK 0x0000007FU

5241

#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV1_2_SHIFT 0U

5242

#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV1_2_WIDTH 7U

5243

#define LPDDR4__PI_VREF_VAL_DEV1_2__REG DENALI_PI_299

5244

#define LPDDR4__PI_VREF_VAL_DEV1_2__FLD LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV1_2

5245

5246

#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV1_3_MASK 0x00007F00U

5247

#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV1_3_SHIFT 8U

5248

#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV1_3_WIDTH 7U

5249

#define LPDDR4__PI_VREF_VAL_DEV1_3__REG DENALI_PI_299

5250

#define LPDDR4__PI_VREF_VAL_DEV1_3__FLD LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV1_3

5251

5252

#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV2_0_MASK 0x007F0000U

5253

#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV2_0_SHIFT 16U

5254

#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV2_0_WIDTH 7U

5255

#define LPDDR4__PI_VREF_VAL_DEV2_0__REG DENALI_PI_299

5256

#define LPDDR4__PI_VREF_VAL_DEV2_0__FLD LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV2_0

5257

5258

#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV2_1_MASK 0x7F000000U

5259

#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV2_1_SHIFT 24U

5260

#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV2_1_WIDTH 7U

5261

#define LPDDR4__PI_VREF_VAL_DEV2_1__REG DENALI_PI_299

5262

#define LPDDR4__PI_VREF_VAL_DEV2_1__FLD LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV2_1

5263

5264

#define LPDDR4__DENALI_PI_300_READ_MASK 0x7F7F7F7FU

5265

#define LPDDR4__DENALI_PI_300_WRITE_MASK 0x7F7F7F7FU

5266

#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV2_2_MASK 0x0000007FU

5267

#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV2_2_SHIFT 0U

5268

#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV2_2_WIDTH 7U

5269

#define LPDDR4__PI_VREF_VAL_DEV2_2__REG DENALI_PI_300

5270

#define LPDDR4__PI_VREF_VAL_DEV2_2__FLD LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV2_2

5271

5272

#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV2_3_MASK 0x00007F00U

5273

#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV2_3_SHIFT 8U

5274

#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV2_3_WIDTH 7U

5275

#define LPDDR4__PI_VREF_VAL_DEV2_3__REG DENALI_PI_300

5276

#define LPDDR4__PI_VREF_VAL_DEV2_3__FLD LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV2_3

5277

5278

#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV3_0_MASK 0x007F0000U

5279

#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV3_0_SHIFT 16U

5280

#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV3_0_WIDTH 7U

5281

#define LPDDR4__PI_VREF_VAL_DEV3_0__REG DENALI_PI_300

5282

#define LPDDR4__PI_VREF_VAL_DEV3_0__FLD LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV3_0

5283

5284

#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV3_1_MASK 0x7F000000U

5285

#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV3_1_SHIFT 24U

5286

#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV3_1_WIDTH 7U

5287

#define LPDDR4__PI_VREF_VAL_DEV3_1__REG DENALI_PI_300

5288

#define LPDDR4__PI_VREF_VAL_DEV3_1__FLD LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV3_1

5289

5290

#define LPDDR4__DENALI_PI_301_READ_MASK 0x03037F7FU

5291

#define LPDDR4__DENALI_PI_301_WRITE_MASK 0x03037F7FU

5292

#define LPDDR4__DENALI_PI_301__PI_VREF_VAL_DEV3_2_MASK 0x0000007FU

5293

#define LPDDR4__DENALI_PI_301__PI_VREF_VAL_DEV3_2_SHIFT 0U

5294

#define LPDDR4__DENALI_PI_301__PI_VREF_VAL_DEV3_2_WIDTH 7U

5295

#define LPDDR4__PI_VREF_VAL_DEV3_2__REG DENALI_PI_301

5296

#define LPDDR4__PI_VREF_VAL_DEV3_2__FLD LPDDR4__DENALI_PI_301__PI_VREF_VAL_DEV3_2

5297

5298

#define LPDDR4__DENALI_PI_301__PI_VREF_VAL_DEV3_3_MASK 0x00007F00U

5299

#define LPDDR4__DENALI_PI_301__PI_VREF_VAL_DEV3_3_SHIFT 8U

5300

#define LPDDR4__DENALI_PI_301__PI_VREF_VAL_DEV3_3_WIDTH 7U

5301

#define LPDDR4__PI_VREF_VAL_DEV3_3__REG DENALI_PI_301

5302

#define LPDDR4__PI_VREF_VAL_DEV3_3__FLD LPDDR4__DENALI_PI_301__PI_VREF_VAL_DEV3_3

5303

5304

#define LPDDR4__DENALI_PI_301__PI_SLICE_PER_DEV_0_MASK 0x00030000U

5305

#define LPDDR4__DENALI_PI_301__PI_SLICE_PER_DEV_0_SHIFT 16U

5306

#define LPDDR4__DENALI_PI_301__PI_SLICE_PER_DEV_0_WIDTH 2U

5307

#define LPDDR4__PI_SLICE_PER_DEV_0__REG DENALI_PI_301

5308

#define LPDDR4__PI_SLICE_PER_DEV_0__FLD LPDDR4__DENALI_PI_301__PI_SLICE_PER_DEV_0

5309

5310

#define LPDDR4__DENALI_PI_301__PI_SLICE_PER_DEV_1_MASK 0x03000000U

5311

#define LPDDR4__DENALI_PI_301__PI_SLICE_PER_DEV_1_SHIFT 24U

5312

#define LPDDR4__DENALI_PI_301__PI_SLICE_PER_DEV_1_WIDTH 2U

5313

#define LPDDR4__PI_SLICE_PER_DEV_1__REG DENALI_PI_301

5314

#define LPDDR4__PI_SLICE_PER_DEV_1__FLD LPDDR4__DENALI_PI_301__PI_SLICE_PER_DEV_1

5315

5316

#define LPDDR4__DENALI_PI_302_READ_MASK 0x3F3F0303U

5317

#define LPDDR4__DENALI_PI_302_WRITE_MASK 0x3F3F0303U

5318

#define LPDDR4__DENALI_PI_302__PI_SLICE_PER_DEV_2_MASK 0x00000003U

5319

#define LPDDR4__DENALI_PI_302__PI_SLICE_PER_DEV_2_SHIFT 0U

5320

#define LPDDR4__DENALI_PI_302__PI_SLICE_PER_DEV_2_WIDTH 2U

5321

#define LPDDR4__PI_SLICE_PER_DEV_2__REG DENALI_PI_302

5322

#define LPDDR4__PI_SLICE_PER_DEV_2__FLD LPDDR4__DENALI_PI_302__PI_SLICE_PER_DEV_2

5323

5324

#define LPDDR4__DENALI_PI_302__PI_SLICE_PER_DEV_3_MASK 0x00000300U

5325

#define LPDDR4__DENALI_PI_302__PI_SLICE_PER_DEV_3_SHIFT 8U

5326

#define LPDDR4__DENALI_PI_302__PI_SLICE_PER_DEV_3_WIDTH 2U

5327

#define LPDDR4__PI_SLICE_PER_DEV_3__REG DENALI_PI_302

5328

#define LPDDR4__PI_SLICE_PER_DEV_3__FLD LPDDR4__DENALI_PI_302__PI_SLICE_PER_DEV_3

5329

5330

#define LPDDR4__DENALI_PI_302__PI_MR6_VREF_0_0_MASK 0x003F0000U

5331

#define LPDDR4__DENALI_PI_302__PI_MR6_VREF_0_0_SHIFT 16U

5332

#define LPDDR4__DENALI_PI_302__PI_MR6_VREF_0_0_WIDTH 6U

5333

#define LPDDR4__PI_MR6_VREF_0_0__REG DENALI_PI_302

5334

#define LPDDR4__PI_MR6_VREF_0_0__FLD LPDDR4__DENALI_PI_302__PI_MR6_VREF_0_0

5335

5336

#define LPDDR4__DENALI_PI_302__PI_MR6_VREF_0_1_MASK 0x3F000000U

5337

#define LPDDR4__DENALI_PI_302__PI_MR6_VREF_0_1_SHIFT 24U

5338

#define LPDDR4__DENALI_PI_302__PI_MR6_VREF_0_1_WIDTH 6U

5339

#define LPDDR4__PI_MR6_VREF_0_1__REG DENALI_PI_302

5340

#define LPDDR4__PI_MR6_VREF_0_1__FLD LPDDR4__DENALI_PI_302__PI_MR6_VREF_0_1

5341

5342

#define LPDDR4__DENALI_PI_303_READ_MASK 0x3F3F3F3FU

5343

#define LPDDR4__DENALI_PI_303_WRITE_MASK 0x3F3F3F3FU

5344

#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_0_2_MASK 0x0000003FU

5345

#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_0_2_SHIFT 0U

5346

#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_0_2_WIDTH 6U

5347

#define LPDDR4__PI_MR6_VREF_0_2__REG DENALI_PI_303

5348

#define LPDDR4__PI_MR6_VREF_0_2__FLD LPDDR4__DENALI_PI_303__PI_MR6_VREF_0_2

5349

5350

#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_0_3_MASK 0x00003F00U

5351

#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_0_3_SHIFT 8U

5352

#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_0_3_WIDTH 6U

5353

#define LPDDR4__PI_MR6_VREF_0_3__REG DENALI_PI_303

5354

#define LPDDR4__PI_MR6_VREF_0_3__FLD LPDDR4__DENALI_PI_303__PI_MR6_VREF_0_3

5355

5356

#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_1_0_MASK 0x003F0000U

5357

#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_1_0_SHIFT 16U

5358

#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_1_0_WIDTH 6U

5359

#define LPDDR4__PI_MR6_VREF_1_0__REG DENALI_PI_303

5360

#define LPDDR4__PI_MR6_VREF_1_0__FLD LPDDR4__DENALI_PI_303__PI_MR6_VREF_1_0

5361

5362

#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_1_1_MASK 0x3F000000U

5363

#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_1_1_SHIFT 24U

5364

#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_1_1_WIDTH 6U

5365

#define LPDDR4__PI_MR6_VREF_1_1__REG DENALI_PI_303

5366

#define LPDDR4__PI_MR6_VREF_1_1__FLD LPDDR4__DENALI_PI_303__PI_MR6_VREF_1_1

5367

5368

#define LPDDR4__DENALI_PI_304_READ_MASK 0x3F3F3F3FU

5369

#define LPDDR4__DENALI_PI_304_WRITE_MASK 0x3F3F3F3FU

5370

#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_1_2_MASK 0x0000003FU

5371

#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_1_2_SHIFT 0U

5372

#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_1_2_WIDTH 6U

5373

#define LPDDR4__PI_MR6_VREF_1_2__REG DENALI_PI_304

5374

#define LPDDR4__PI_MR6_VREF_1_2__FLD LPDDR4__DENALI_PI_304__PI_MR6_VREF_1_2

5375

5376

#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_1_3_MASK 0x00003F00U

5377

#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_1_3_SHIFT 8U

5378

#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_1_3_WIDTH 6U

5379

#define LPDDR4__PI_MR6_VREF_1_3__REG DENALI_PI_304

5380

#define LPDDR4__PI_MR6_VREF_1_3__FLD LPDDR4__DENALI_PI_304__PI_MR6_VREF_1_3

5381

5382

#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_2_0_MASK 0x003F0000U

5383

#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_2_0_SHIFT 16U

5384

#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_2_0_WIDTH 6U

5385

#define LPDDR4__PI_MR6_VREF_2_0__REG DENALI_PI_304

5386

#define LPDDR4__PI_MR6_VREF_2_0__FLD LPDDR4__DENALI_PI_304__PI_MR6_VREF_2_0

5387

5388

#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_2_1_MASK 0x3F000000U

5389

#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_2_1_SHIFT 24U

5390

#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_2_1_WIDTH 6U

5391

#define LPDDR4__PI_MR6_VREF_2_1__REG DENALI_PI_304

5392

#define LPDDR4__PI_MR6_VREF_2_1__FLD LPDDR4__DENALI_PI_304__PI_MR6_VREF_2_1

5393

5394

#define LPDDR4__DENALI_PI_305_READ_MASK 0x3F3F3F3FU

5395

#define LPDDR4__DENALI_PI_305_WRITE_MASK 0x3F3F3F3FU

5396

#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_2_2_MASK 0x0000003FU

5397

#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_2_2_SHIFT 0U

5398

#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_2_2_WIDTH 6U

5399

#define LPDDR4__PI_MR6_VREF_2_2__REG DENALI_PI_305

5400

#define LPDDR4__PI_MR6_VREF_2_2__FLD LPDDR4__DENALI_PI_305__PI_MR6_VREF_2_2

5401

5402

#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_2_3_MASK 0x00003F00U

5403

#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_2_3_SHIFT 8U

5404

#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_2_3_WIDTH 6U

5405

#define LPDDR4__PI_MR6_VREF_2_3__REG DENALI_PI_305

5406

#define LPDDR4__PI_MR6_VREF_2_3__FLD LPDDR4__DENALI_PI_305__PI_MR6_VREF_2_3

5407

5408

#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_3_0_MASK 0x003F0000U

5409

#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_3_0_SHIFT 16U

5410

#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_3_0_WIDTH 6U

5411

#define LPDDR4__PI_MR6_VREF_3_0__REG DENALI_PI_305

5412

#define LPDDR4__PI_MR6_VREF_3_0__FLD LPDDR4__DENALI_PI_305__PI_MR6_VREF_3_0

5413

5414

#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_3_1_MASK 0x3F000000U

5415

#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_3_1_SHIFT 24U

5416

#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_3_1_WIDTH 6U

5417

#define LPDDR4__PI_MR6_VREF_3_1__REG DENALI_PI_305

5418

#define LPDDR4__PI_MR6_VREF_3_1__FLD LPDDR4__DENALI_PI_305__PI_MR6_VREF_3_1

5419

5420

#define LPDDR4__DENALI_PI_306_READ_MASK 0xFFFF3F3FU

5421

#define LPDDR4__DENALI_PI_306_WRITE_MASK 0xFFFF3F3FU

5422

#define LPDDR4__DENALI_PI_306__PI_MR6_VREF_3_2_MASK 0x0000003FU

5423

#define LPDDR4__DENALI_PI_306__PI_MR6_VREF_3_2_SHIFT 0U

5424

#define LPDDR4__DENALI_PI_306__PI_MR6_VREF_3_2_WIDTH 6U

5425

#define LPDDR4__PI_MR6_VREF_3_2__REG DENALI_PI_306

5426

#define LPDDR4__PI_MR6_VREF_3_2__FLD LPDDR4__DENALI_PI_306__PI_MR6_VREF_3_2

5427

5428

#define LPDDR4__DENALI_PI_306__PI_MR6_VREF_3_3_MASK 0x00003F00U

5429

#define LPDDR4__DENALI_PI_306__PI_MR6_VREF_3_3_SHIFT 8U

5430

#define LPDDR4__DENALI_PI_306__PI_MR6_VREF_3_3_WIDTH 6U

5431

#define LPDDR4__PI_MR6_VREF_3_3__REG DENALI_PI_306

5432

#define LPDDR4__PI_MR6_VREF_3_3__FLD LPDDR4__DENALI_PI_306__PI_MR6_VREF_3_3

5433

5434

#define LPDDR4__DENALI_PI_306__PI_MR13_DATA_0_MASK 0x00FF0000U

5435

#define LPDDR4__DENALI_PI_306__PI_MR13_DATA_0_SHIFT 16U

5436

#define LPDDR4__DENALI_PI_306__PI_MR13_DATA_0_WIDTH 8U

5437

#define LPDDR4__PI_MR13_DATA_0__REG DENALI_PI_306

5438

#define LPDDR4__PI_MR13_DATA_0__FLD LPDDR4__DENALI_PI_306__PI_MR13_DATA_0

5439

5440

#define LPDDR4__DENALI_PI_306__PI_MR15_DATA_0_MASK 0xFF000000U

5441

#define LPDDR4__DENALI_PI_306__PI_MR15_DATA_0_SHIFT 24U

5442

#define LPDDR4__DENALI_PI_306__PI_MR15_DATA_0_WIDTH 8U

5443

#define LPDDR4__PI_MR15_DATA_0__REG DENALI_PI_306

5444

#define LPDDR4__PI_MR15_DATA_0__FLD LPDDR4__DENALI_PI_306__PI_MR15_DATA_0

5445

5446

#define LPDDR4__DENALI_PI_307_READ_MASK 0x00FFFFFFU

5447

#define LPDDR4__DENALI_PI_307_WRITE_MASK 0x00FFFFFFU

5448

#define LPDDR4__DENALI_PI_307__PI_MR16_DATA_0_MASK 0x000000FFU

5449

#define LPDDR4__DENALI_PI_307__PI_MR16_DATA_0_SHIFT 0U

5450

#define LPDDR4__DENALI_PI_307__PI_MR16_DATA_0_WIDTH 8U

5451

#define LPDDR4__PI_MR16_DATA_0__REG DENALI_PI_307

5452

#define LPDDR4__PI_MR16_DATA_0__FLD LPDDR4__DENALI_PI_307__PI_MR16_DATA_0

5453

5454

#define LPDDR4__DENALI_PI_307__PI_MR17_DATA_0_MASK 0x0000FF00U

5455

#define LPDDR4__DENALI_PI_307__PI_MR17_DATA_0_SHIFT 8U

5456

#define LPDDR4__DENALI_PI_307__PI_MR17_DATA_0_WIDTH 8U

5457

#define LPDDR4__PI_MR17_DATA_0__REG DENALI_PI_307

5458

#define LPDDR4__PI_MR17_DATA_0__FLD LPDDR4__DENALI_PI_307__PI_MR17_DATA_0

5459

5460

#define LPDDR4__DENALI_PI_307__PI_MR20_DATA_0_MASK 0x00FF0000U

5461

#define LPDDR4__DENALI_PI_307__PI_MR20_DATA_0_SHIFT 16U

5462

#define LPDDR4__DENALI_PI_307__PI_MR20_DATA_0_WIDTH 8U

5463

#define LPDDR4__PI_MR20_DATA_0__REG DENALI_PI_307

5464

#define LPDDR4__PI_MR20_DATA_0__FLD LPDDR4__DENALI_PI_307__PI_MR20_DATA_0

5465

5466

#define LPDDR4__DENALI_PI_308_READ_MASK 0xFF01FFFFU

5467

#define LPDDR4__DENALI_PI_308_WRITE_MASK 0xFF01FFFFU

5468

#define LPDDR4__DENALI_PI_308__PI_MR32_DATA_0_MASK 0x0001FFFFU

5469

#define LPDDR4__DENALI_PI_308__PI_MR32_DATA_0_SHIFT 0U

5470

#define LPDDR4__DENALI_PI_308__PI_MR32_DATA_0_WIDTH 17U

5471

#define LPDDR4__PI_MR32_DATA_0__REG DENALI_PI_308

5472

#define LPDDR4__PI_MR32_DATA_0__FLD LPDDR4__DENALI_PI_308__PI_MR32_DATA_0

5473

5474

#define LPDDR4__DENALI_PI_308__PI_MR40_DATA_0_MASK 0xFF000000U

5475

#define LPDDR4__DENALI_PI_308__PI_MR40_DATA_0_SHIFT 24U

5476

#define LPDDR4__DENALI_PI_308__PI_MR40_DATA_0_WIDTH 8U

5477

#define LPDDR4__PI_MR40_DATA_0__REG DENALI_PI_308

5478

#define LPDDR4__PI_MR40_DATA_0__FLD LPDDR4__DENALI_PI_308__PI_MR40_DATA_0

5479

5480

#define LPDDR4__DENALI_PI_309_READ_MASK 0xFFFFFFFFU

5481

#define LPDDR4__DENALI_PI_309_WRITE_MASK 0xFFFFFFFFU

5482

#define LPDDR4__DENALI_PI_309__PI_MR13_DATA_1_MASK 0x000000FFU

5483

#define LPDDR4__DENALI_PI_309__PI_MR13_DATA_1_SHIFT 0U

5484

#define LPDDR4__DENALI_PI_309__PI_MR13_DATA_1_WIDTH 8U

5485

#define LPDDR4__PI_MR13_DATA_1__REG DENALI_PI_309

5486

#define LPDDR4__PI_MR13_DATA_1__FLD LPDDR4__DENALI_PI_309__PI_MR13_DATA_1

5487

5488

#define LPDDR4__DENALI_PI_309__PI_MR15_DATA_1_MASK 0x0000FF00U

5489

#define LPDDR4__DENALI_PI_309__PI_MR15_DATA_1_SHIFT 8U

5490

#define LPDDR4__DENALI_PI_309__PI_MR15_DATA_1_WIDTH 8U

5491

#define LPDDR4__PI_MR15_DATA_1__REG DENALI_PI_309

5492

#define LPDDR4__PI_MR15_DATA_1__FLD LPDDR4__DENALI_PI_309__PI_MR15_DATA_1

5493

5494

#define LPDDR4__DENALI_PI_309__PI_MR16_DATA_1_MASK 0x00FF0000U

5495

#define LPDDR4__DENALI_PI_309__PI_MR16_DATA_1_SHIFT 16U

5496

#define LPDDR4__DENALI_PI_309__PI_MR16_DATA_1_WIDTH 8U

5497

#define LPDDR4__PI_MR16_DATA_1__REG DENALI_PI_309

5498

#define LPDDR4__PI_MR16_DATA_1__FLD LPDDR4__DENALI_PI_309__PI_MR16_DATA_1

5499

5500

#define LPDDR4__DENALI_PI_309__PI_MR17_DATA_1_MASK 0xFF000000U

5501

#define LPDDR4__DENALI_PI_309__PI_MR17_DATA_1_SHIFT 24U

5502

#define LPDDR4__DENALI_PI_309__PI_MR17_DATA_1_WIDTH 8U

5503

#define LPDDR4__PI_MR17_DATA_1__REG DENALI_PI_309

5504

#define LPDDR4__PI_MR17_DATA_1__FLD LPDDR4__DENALI_PI_309__PI_MR17_DATA_1

5505

5506

#define LPDDR4__DENALI_PI_310_READ_MASK 0x01FFFFFFU

5507

#define LPDDR4__DENALI_PI_310_WRITE_MASK 0x01FFFFFFU

5508

#define LPDDR4__DENALI_PI_310__PI_MR20_DATA_1_MASK 0x000000FFU

5509

#define LPDDR4__DENALI_PI_310__PI_MR20_DATA_1_SHIFT 0U

5510

#define LPDDR4__DENALI_PI_310__PI_MR20_DATA_1_WIDTH 8U

5511

#define LPDDR4__PI_MR20_DATA_1__REG DENALI_PI_310

5512

#define LPDDR4__PI_MR20_DATA_1__FLD LPDDR4__DENALI_PI_310__PI_MR20_DATA_1

5513

5514

#define LPDDR4__DENALI_PI_310__PI_MR32_DATA_1_MASK 0x01FFFF00U

5515

#define LPDDR4__DENALI_PI_310__PI_MR32_DATA_1_SHIFT 8U

5516

#define LPDDR4__DENALI_PI_310__PI_MR32_DATA_1_WIDTH 17U

5517

#define LPDDR4__PI_MR32_DATA_1__REG DENALI_PI_310

5518

#define LPDDR4__PI_MR32_DATA_1__FLD LPDDR4__DENALI_PI_310__PI_MR32_DATA_1

5519

5520

#define LPDDR4__DENALI_PI_311_READ_MASK 0xFFFFFFFFU

5521

#define LPDDR4__DENALI_PI_311_WRITE_MASK 0xFFFFFFFFU

5522

#define LPDDR4__DENALI_PI_311__PI_MR40_DATA_1_MASK 0x000000FFU

5523

#define LPDDR4__DENALI_PI_311__PI_MR40_DATA_1_SHIFT 0U

5524

#define LPDDR4__DENALI_PI_311__PI_MR40_DATA_1_WIDTH 8U

5525

#define LPDDR4__PI_MR40_DATA_1__REG DENALI_PI_311

5526

#define LPDDR4__PI_MR40_DATA_1__FLD LPDDR4__DENALI_PI_311__PI_MR40_DATA_1

5527

5528

#define LPDDR4__DENALI_PI_311__PI_MR13_DATA_2_MASK 0x0000FF00U

5529

#define LPDDR4__DENALI_PI_311__PI_MR13_DATA_2_SHIFT 8U

5530

#define LPDDR4__DENALI_PI_311__PI_MR13_DATA_2_WIDTH 8U

5531

#define LPDDR4__PI_MR13_DATA_2__REG DENALI_PI_311

5532

#define LPDDR4__PI_MR13_DATA_2__FLD LPDDR4__DENALI_PI_311__PI_MR13_DATA_2

5533

5534

#define LPDDR4__DENALI_PI_311__PI_MR15_DATA_2_MASK 0x00FF0000U

5535

#define LPDDR4__DENALI_PI_311__PI_MR15_DATA_2_SHIFT 16U

5536

#define LPDDR4__DENALI_PI_311__PI_MR15_DATA_2_WIDTH 8U

5537

#define LPDDR4__PI_MR15_DATA_2__REG DENALI_PI_311

5538

#define LPDDR4__PI_MR15_DATA_2__FLD LPDDR4__DENALI_PI_311__PI_MR15_DATA_2

5539

5540

#define LPDDR4__DENALI_PI_311__PI_MR16_DATA_2_MASK 0xFF000000U

5541

#define LPDDR4__DENALI_PI_311__PI_MR16_DATA_2_SHIFT 24U

5542

#define LPDDR4__DENALI_PI_311__PI_MR16_DATA_2_WIDTH 8U

5543

#define LPDDR4__PI_MR16_DATA_2__REG DENALI_PI_311

5544

#define LPDDR4__PI_MR16_DATA_2__FLD LPDDR4__DENALI_PI_311__PI_MR16_DATA_2

5545

5546

#define LPDDR4__DENALI_PI_312_READ_MASK 0x0000FFFFU

5547

#define LPDDR4__DENALI_PI_312_WRITE_MASK 0x0000FFFFU

5548

#define LPDDR4__DENALI_PI_312__PI_MR17_DATA_2_MASK 0x000000FFU

5549

#define LPDDR4__DENALI_PI_312__PI_MR17_DATA_2_SHIFT 0U

5550

#define LPDDR4__DENALI_PI_312__PI_MR17_DATA_2_WIDTH 8U

5551

#define LPDDR4__PI_MR17_DATA_2__REG DENALI_PI_312

5552

#define LPDDR4__PI_MR17_DATA_2__FLD LPDDR4__DENALI_PI_312__PI_MR17_DATA_2

5553

5554

#define LPDDR4__DENALI_PI_312__PI_MR20_DATA_2_MASK 0x0000FF00U

5555

#define LPDDR4__DENALI_PI_312__PI_MR20_DATA_2_SHIFT 8U

5556

#define LPDDR4__DENALI_PI_312__PI_MR20_DATA_2_WIDTH 8U

5557

#define LPDDR4__PI_MR20_DATA_2__REG DENALI_PI_312

5558

#define LPDDR4__PI_MR20_DATA_2__FLD LPDDR4__DENALI_PI_312__PI_MR20_DATA_2

5559

5560

#define LPDDR4__DENALI_PI_313_READ_MASK 0xFF01FFFFU

5561

#define LPDDR4__DENALI_PI_313_WRITE_MASK 0xFF01FFFFU

5562

#define LPDDR4__DENALI_PI_313__PI_MR32_DATA_2_MASK 0x0001FFFFU

5563

#define LPDDR4__DENALI_PI_313__PI_MR32_DATA_2_SHIFT 0U

5564

#define LPDDR4__DENALI_PI_313__PI_MR32_DATA_2_WIDTH 17U

5565

#define LPDDR4__PI_MR32_DATA_2__REG DENALI_PI_313

5566

#define LPDDR4__PI_MR32_DATA_2__FLD LPDDR4__DENALI_PI_313__PI_MR32_DATA_2

5567

5568

#define LPDDR4__DENALI_PI_313__PI_MR40_DATA_2_MASK 0xFF000000U

5569

#define LPDDR4__DENALI_PI_313__PI_MR40_DATA_2_SHIFT 24U

5570

#define LPDDR4__DENALI_PI_313__PI_MR40_DATA_2_WIDTH 8U

5571

#define LPDDR4__PI_MR40_DATA_2__REG DENALI_PI_313

5572

#define LPDDR4__PI_MR40_DATA_2__FLD LPDDR4__DENALI_PI_313__PI_MR40_DATA_2

5573

5574

#define LPDDR4__DENALI_PI_314_READ_MASK 0xFFFFFFFFU

5575

#define LPDDR4__DENALI_PI_314_WRITE_MASK 0xFFFFFFFFU

5576

#define LPDDR4__DENALI_PI_314__PI_MR13_DATA_3_MASK 0x000000FFU

5577

#define LPDDR4__DENALI_PI_314__PI_MR13_DATA_3_SHIFT 0U

5578

#define LPDDR4__DENALI_PI_314__PI_MR13_DATA_3_WIDTH 8U

5579

#define LPDDR4__PI_MR13_DATA_3__REG DENALI_PI_314

5580

#define LPDDR4__PI_MR13_DATA_3__FLD LPDDR4__DENALI_PI_314__PI_MR13_DATA_3

5581

5582

#define LPDDR4__DENALI_PI_314__PI_MR15_DATA_3_MASK 0x0000FF00U

5583

#define LPDDR4__DENALI_PI_314__PI_MR15_DATA_3_SHIFT 8U

5584

#define LPDDR4__DENALI_PI_314__PI_MR15_DATA_3_WIDTH 8U

5585

#define LPDDR4__PI_MR15_DATA_3__REG DENALI_PI_314

5586

#define LPDDR4__PI_MR15_DATA_3__FLD LPDDR4__DENALI_PI_314__PI_MR15_DATA_3

5587

5588

#define LPDDR4__DENALI_PI_314__PI_MR16_DATA_3_MASK 0x00FF0000U

5589

#define LPDDR4__DENALI_PI_314__PI_MR16_DATA_3_SHIFT 16U

5590

#define LPDDR4__DENALI_PI_314__PI_MR16_DATA_3_WIDTH 8U

5591

#define LPDDR4__PI_MR16_DATA_3__REG DENALI_PI_314

5592

#define LPDDR4__PI_MR16_DATA_3__FLD LPDDR4__DENALI_PI_314__PI_MR16_DATA_3

5593

5594

#define LPDDR4__DENALI_PI_314__PI_MR17_DATA_3_MASK 0xFF000000U

5595

#define LPDDR4__DENALI_PI_314__PI_MR17_DATA_3_SHIFT 24U

5596

#define LPDDR4__DENALI_PI_314__PI_MR17_DATA_3_WIDTH 8U

5597

#define LPDDR4__PI_MR17_DATA_3__REG DENALI_PI_314

5598

#define LPDDR4__PI_MR17_DATA_3__FLD LPDDR4__DENALI_PI_314__PI_MR17_DATA_3

5599

5600

#define LPDDR4__DENALI_PI_315_READ_MASK 0x01FFFFFFU

5601

#define LPDDR4__DENALI_PI_315_WRITE_MASK 0x01FFFFFFU

5602

#define LPDDR4__DENALI_PI_315__PI_MR20_DATA_3_MASK 0x000000FFU

5603

#define LPDDR4__DENALI_PI_315__PI_MR20_DATA_3_SHIFT 0U

5604

#define LPDDR4__DENALI_PI_315__PI_MR20_DATA_3_WIDTH 8U

5605

#define LPDDR4__PI_MR20_DATA_3__REG DENALI_PI_315

5606

#define LPDDR4__PI_MR20_DATA_3__FLD LPDDR4__DENALI_PI_315__PI_MR20_DATA_3

5607

5608

#define LPDDR4__DENALI_PI_315__PI_MR32_DATA_3_MASK 0x01FFFF00U

5609

#define LPDDR4__DENALI_PI_315__PI_MR32_DATA_3_SHIFT 8U

5610

#define LPDDR4__DENALI_PI_315__PI_MR32_DATA_3_WIDTH 17U

5611

#define LPDDR4__PI_MR32_DATA_3__REG DENALI_PI_315

5612

#define LPDDR4__PI_MR32_DATA_3__FLD LPDDR4__DENALI_PI_315__PI_MR32_DATA_3

5613

5614

#define LPDDR4__DENALI_PI_316_READ_MASK 0x1F1F1FFFU

5615

#define LPDDR4__DENALI_PI_316_WRITE_MASK 0x1F1F1FFFU

5616

#define LPDDR4__DENALI_PI_316__PI_MR40_DATA_3_MASK 0x000000FFU

5617

#define LPDDR4__DENALI_PI_316__PI_MR40_DATA_3_SHIFT 0U

5618

#define LPDDR4__DENALI_PI_316__PI_MR40_DATA_3_WIDTH 8U

5619

#define LPDDR4__PI_MR40_DATA_3__REG DENALI_PI_316

5620

#define LPDDR4__PI_MR40_DATA_3__FLD LPDDR4__DENALI_PI_316__PI_MR40_DATA_3

5621

5622

#define LPDDR4__DENALI_PI_316__PI_CKE_MUX_0_MASK 0x00001F00U

5623

#define LPDDR4__DENALI_PI_316__PI_CKE_MUX_0_SHIFT 8U

5624

#define LPDDR4__DENALI_PI_316__PI_CKE_MUX_0_WIDTH 5U

5625

#define LPDDR4__PI_CKE_MUX_0__REG DENALI_PI_316

5626

#define LPDDR4__PI_CKE_MUX_0__FLD LPDDR4__DENALI_PI_316__PI_CKE_MUX_0

5627

5628

#define LPDDR4__DENALI_PI_316__PI_CKE_MUX_1_MASK 0x001F0000U

5629

#define LPDDR4__DENALI_PI_316__PI_CKE_MUX_1_SHIFT 16U

5630

#define LPDDR4__DENALI_PI_316__PI_CKE_MUX_1_WIDTH 5U

5631

#define LPDDR4__PI_CKE_MUX_1__REG DENALI_PI_316

5632

#define LPDDR4__PI_CKE_MUX_1__FLD LPDDR4__DENALI_PI_316__PI_CKE_MUX_1

5633

5634

#define LPDDR4__DENALI_PI_316__PI_CKE_MUX_2_MASK 0x1F000000U

5635

#define LPDDR4__DENALI_PI_316__PI_CKE_MUX_2_SHIFT 24U

5636

#define LPDDR4__DENALI_PI_316__PI_CKE_MUX_2_WIDTH 5U

5637

#define LPDDR4__PI_CKE_MUX_2__REG DENALI_PI_316

5638

#define LPDDR4__PI_CKE_MUX_2__FLD LPDDR4__DENALI_PI_316__PI_CKE_MUX_2

5639

5640

#define LPDDR4__DENALI_PI_317_READ_MASK 0x1F1F1F1FU

5641

#define LPDDR4__DENALI_PI_317_WRITE_MASK 0x1F1F1F1FU

5642

#define LPDDR4__DENALI_PI_317__PI_CKE_MUX_3_MASK 0x0000001FU

5643

#define LPDDR4__DENALI_PI_317__PI_CKE_MUX_3_SHIFT 0U

5644

#define LPDDR4__DENALI_PI_317__PI_CKE_MUX_3_WIDTH 5U

5645

#define LPDDR4__PI_CKE_MUX_3__REG DENALI_PI_317

5646

#define LPDDR4__PI_CKE_MUX_3__FLD LPDDR4__DENALI_PI_317__PI_CKE_MUX_3

5647

5648

#define LPDDR4__DENALI_PI_317__PI_CS_MUX_0_MASK 0x00001F00U

5649

#define LPDDR4__DENALI_PI_317__PI_CS_MUX_0_SHIFT 8U

5650

#define LPDDR4__DENALI_PI_317__PI_CS_MUX_0_WIDTH 5U

5651

#define LPDDR4__PI_CS_MUX_0__REG DENALI_PI_317

5652

#define LPDDR4__PI_CS_MUX_0__FLD LPDDR4__DENALI_PI_317__PI_CS_MUX_0

5653

5654

#define LPDDR4__DENALI_PI_317__PI_CS_MUX_1_MASK 0x001F0000U

5655

#define LPDDR4__DENALI_PI_317__PI_CS_MUX_1_SHIFT 16U

5656

#define LPDDR4__DENALI_PI_317__PI_CS_MUX_1_WIDTH 5U

5657

#define LPDDR4__PI_CS_MUX_1__REG DENALI_PI_317

5658

#define LPDDR4__PI_CS_MUX_1__FLD LPDDR4__DENALI_PI_317__PI_CS_MUX_1

5659

5660

#define LPDDR4__DENALI_PI_317__PI_CS_MUX_2_MASK 0x1F000000U

5661

#define LPDDR4__DENALI_PI_317__PI_CS_MUX_2_SHIFT 24U

5662

#define LPDDR4__DENALI_PI_317__PI_CS_MUX_2_WIDTH 5U

5663

#define LPDDR4__PI_CS_MUX_2__REG DENALI_PI_317

5664

#define LPDDR4__PI_CS_MUX_2__FLD LPDDR4__DENALI_PI_317__PI_CS_MUX_2

5665

5666

#define LPDDR4__DENALI_PI_318_READ_MASK 0x1F1F1F1FU

5667

#define LPDDR4__DENALI_PI_318_WRITE_MASK 0x1F1F1F1FU

5668

#define LPDDR4__DENALI_PI_318__PI_CS_MUX_3_MASK 0x0000001FU

5669

#define LPDDR4__DENALI_PI_318__PI_CS_MUX_3_SHIFT 0U

5670

#define LPDDR4__DENALI_PI_318__PI_CS_MUX_3_WIDTH 5U

5671

#define LPDDR4__PI_CS_MUX_3__REG DENALI_PI_318

5672

#define LPDDR4__PI_CS_MUX_3__FLD LPDDR4__DENALI_PI_318__PI_CS_MUX_3

5673

5674

#define LPDDR4__DENALI_PI_318__PI_ODT_MUX_0_MASK 0x00001F00U

5675

#define LPDDR4__DENALI_PI_318__PI_ODT_MUX_0_SHIFT 8U

5676

#define LPDDR4__DENALI_PI_318__PI_ODT_MUX_0_WIDTH 5U

5677

#define LPDDR4__PI_ODT_MUX_0__REG DENALI_PI_318

5678

#define LPDDR4__PI_ODT_MUX_0__FLD LPDDR4__DENALI_PI_318__PI_ODT_MUX_0

5679

5680

#define LPDDR4__DENALI_PI_318__PI_ODT_MUX_1_MASK 0x001F0000U

5681

#define LPDDR4__DENALI_PI_318__PI_ODT_MUX_1_SHIFT 16U

5682

#define LPDDR4__DENALI_PI_318__PI_ODT_MUX_1_WIDTH 5U

5683

#define LPDDR4__PI_ODT_MUX_1__REG DENALI_PI_318

5684

#define LPDDR4__PI_ODT_MUX_1__FLD LPDDR4__DENALI_PI_318__PI_ODT_MUX_1

5685

5686

#define LPDDR4__DENALI_PI_318__PI_ODT_MUX_2_MASK 0x1F000000U

5687

#define LPDDR4__DENALI_PI_318__PI_ODT_MUX_2_SHIFT 24U

5688

#define LPDDR4__DENALI_PI_318__PI_ODT_MUX_2_WIDTH 5U

5689

#define LPDDR4__PI_ODT_MUX_2__REG DENALI_PI_318

5690

#define LPDDR4__PI_ODT_MUX_2__FLD LPDDR4__DENALI_PI_318__PI_ODT_MUX_2

5691

5692

#define LPDDR4__DENALI_PI_319_READ_MASK 0x1F1F1F1FU

5693

#define LPDDR4__DENALI_PI_319_WRITE_MASK 0x1F1F1F1FU

5694

#define LPDDR4__DENALI_PI_319__PI_ODT_MUX_3_MASK 0x0000001FU

5695

#define LPDDR4__DENALI_PI_319__PI_ODT_MUX_3_SHIFT 0U

5696

#define LPDDR4__DENALI_PI_319__PI_ODT_MUX_3_WIDTH 5U

5697

#define LPDDR4__PI_ODT_MUX_3__REG DENALI_PI_319

5698

#define LPDDR4__PI_ODT_MUX_3__FLD LPDDR4__DENALI_PI_319__PI_ODT_MUX_3

5699

5700

#define LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_0_MASK 0x00001F00U

5701

#define LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_0_SHIFT 8U

5702

#define LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_0_WIDTH 5U

5703

#define LPDDR4__PI_RESET_N_MUX_0__REG DENALI_PI_319

5704

#define LPDDR4__PI_RESET_N_MUX_0__FLD LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_0

5705

5706

#define LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_1_MASK 0x001F0000U

5707

#define LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_1_SHIFT 16U

5708

#define LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_1_WIDTH 5U

5709

#define LPDDR4__PI_RESET_N_MUX_1__REG DENALI_PI_319

5710

#define LPDDR4__PI_RESET_N_MUX_1__FLD LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_1

5711

5712

#define LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_2_MASK 0x1F000000U

5713

#define LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_2_SHIFT 24U

5714

#define LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_2_WIDTH 5U

5715

#define LPDDR4__PI_RESET_N_MUX_2__REG DENALI_PI_319

5716

#define LPDDR4__PI_RESET_N_MUX_2__FLD LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_2

5717

5718

#define LPDDR4__DENALI_PI_320_READ_MASK 0x01FFFF1FU

5719

#define LPDDR4__DENALI_PI_320_WRITE_MASK 0x01FFFF1FU

5720

#define LPDDR4__DENALI_PI_320__PI_RESET_N_MUX_3_MASK 0x0000001FU

5721

#define LPDDR4__DENALI_PI_320__PI_RESET_N_MUX_3_SHIFT 0U

5722

#define LPDDR4__DENALI_PI_320__PI_RESET_N_MUX_3_WIDTH 5U

5723

#define LPDDR4__PI_RESET_N_MUX_3__REG DENALI_PI_320

5724

#define LPDDR4__PI_RESET_N_MUX_3__FLD LPDDR4__DENALI_PI_320__PI_RESET_N_MUX_3

5725

5726

#define LPDDR4__DENALI_PI_320__PI_MRSINGLE_DATA_0_MASK 0x01FFFF00U

5727

#define LPDDR4__DENALI_PI_320__PI_MRSINGLE_DATA_0_SHIFT 8U

5728

#define LPDDR4__DENALI_PI_320__PI_MRSINGLE_DATA_0_WIDTH 17U

5729

#define LPDDR4__PI_MRSINGLE_DATA_0__REG DENALI_PI_320

5730

#define LPDDR4__PI_MRSINGLE_DATA_0__FLD LPDDR4__DENALI_PI_320__PI_MRSINGLE_DATA_0

5731

5732

#define LPDDR4__DENALI_PI_321_READ_MASK 0x0001FFFFU

5733

#define LPDDR4__DENALI_PI_321_WRITE_MASK 0x0001FFFFU

5734

#define LPDDR4__DENALI_PI_321__PI_MRSINGLE_DATA_1_MASK 0x0001FFFFU

5735

#define LPDDR4__DENALI_PI_321__PI_MRSINGLE_DATA_1_SHIFT 0U

5736

#define LPDDR4__DENALI_PI_321__PI_MRSINGLE_DATA_1_WIDTH 17U

5737

#define LPDDR4__PI_MRSINGLE_DATA_1__REG DENALI_PI_321

5738

#define LPDDR4__PI_MRSINGLE_DATA_1__FLD LPDDR4__DENALI_PI_321__PI_MRSINGLE_DATA_1

5739

5740

#define LPDDR4__DENALI_PI_322_READ_MASK 0x0001FFFFU

5741

#define LPDDR4__DENALI_PI_322_WRITE_MASK 0x0001FFFFU

5742

#define LPDDR4__DENALI_PI_322__PI_MRSINGLE_DATA_2_MASK 0x0001FFFFU

5743

#define LPDDR4__DENALI_PI_322__PI_MRSINGLE_DATA_2_SHIFT 0U

5744

#define LPDDR4__DENALI_PI_322__PI_MRSINGLE_DATA_2_WIDTH 17U

5745

#define LPDDR4__PI_MRSINGLE_DATA_2__REG DENALI_PI_322

5746

#define LPDDR4__PI_MRSINGLE_DATA_2__FLD LPDDR4__DENALI_PI_322__PI_MRSINGLE_DATA_2

5747

5748

#define LPDDR4__DENALI_PI_323_READ_MASK 0x0F01FFFFU

5749

#define LPDDR4__DENALI_PI_323_WRITE_MASK 0x0F01FFFFU

5750

#define LPDDR4__DENALI_PI_323__PI_MRSINGLE_DATA_3_MASK 0x0001FFFFU

5751

#define LPDDR4__DENALI_PI_323__PI_MRSINGLE_DATA_3_SHIFT 0U

5752

#define LPDDR4__DENALI_PI_323__PI_MRSINGLE_DATA_3_WIDTH 17U

5753

#define LPDDR4__PI_MRSINGLE_DATA_3__REG DENALI_PI_323

5754

#define LPDDR4__PI_MRSINGLE_DATA_3__FLD LPDDR4__DENALI_PI_323__PI_MRSINGLE_DATA_3

5755

5756

#define LPDDR4__DENALI_PI_323__PI_ZQ_CAL_START_MAP_0_MASK 0x0F000000U

5757

#define LPDDR4__DENALI_PI_323__PI_ZQ_CAL_START_MAP_0_SHIFT 24U

5758

#define LPDDR4__DENALI_PI_323__PI_ZQ_CAL_START_MAP_0_WIDTH 4U

5759

#define LPDDR4__PI_ZQ_CAL_START_MAP_0__REG DENALI_PI_323

5760

#define LPDDR4__PI_ZQ_CAL_START_MAP_0__FLD LPDDR4__DENALI_PI_323__PI_ZQ_CAL_START_MAP_0

5761

5762

#define LPDDR4__DENALI_PI_324_READ_MASK 0x0F0F0F0FU

5763

#define LPDDR4__DENALI_PI_324_WRITE_MASK 0x0F0F0F0FU

5764

#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_LATCH_MAP_0_MASK 0x0000000FU

5765

#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_LATCH_MAP_0_SHIFT 0U

5766

#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_LATCH_MAP_0_WIDTH 4U

5767

#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_0__REG DENALI_PI_324

5768

#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_0__FLD LPDDR4__DENALI_PI_324__PI_ZQ_CAL_LATCH_MAP_0

5769

5770

#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_START_MAP_1_MASK 0x00000F00U

5771

#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_START_MAP_1_SHIFT 8U

5772

#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_START_MAP_1_WIDTH 4U

5773

#define LPDDR4__PI_ZQ_CAL_START_MAP_1__REG DENALI_PI_324

5774

#define LPDDR4__PI_ZQ_CAL_START_MAP_1__FLD LPDDR4__DENALI_PI_324__PI_ZQ_CAL_START_MAP_1

5775

5776

#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_LATCH_MAP_1_MASK 0x000F0000U

5777

#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_LATCH_MAP_1_SHIFT 16U

5778

#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_LATCH_MAP_1_WIDTH 4U

5779

#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_1__REG DENALI_PI_324

5780

#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_1__FLD LPDDR4__DENALI_PI_324__PI_ZQ_CAL_LATCH_MAP_1

5781

5782

#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_START_MAP_2_MASK 0x0F000000U

5783

#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_START_MAP_2_SHIFT 24U

5784

#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_START_MAP_2_WIDTH 4U

5785

#define LPDDR4__PI_ZQ_CAL_START_MAP_2__REG DENALI_PI_324

5786

#define LPDDR4__PI_ZQ_CAL_START_MAP_2__FLD LPDDR4__DENALI_PI_324__PI_ZQ_CAL_START_MAP_2

5787

5788

#define LPDDR4__DENALI_PI_325_READ_MASK 0x000F0F0FU

5789

#define LPDDR4__DENALI_PI_325_WRITE_MASK 0x000F0F0FU

5790

#define LPDDR4__DENALI_PI_325__PI_ZQ_CAL_LATCH_MAP_2_MASK 0x0000000FU

5791

#define LPDDR4__DENALI_PI_325__PI_ZQ_CAL_LATCH_MAP_2_SHIFT 0U

5792

#define LPDDR4__DENALI_PI_325__PI_ZQ_CAL_LATCH_MAP_2_WIDTH 4U

5793

#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_2__REG DENALI_PI_325

5794

#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_2__FLD LPDDR4__DENALI_PI_325__PI_ZQ_CAL_LATCH_MAP_2

5795

5796

#define LPDDR4__DENALI_PI_325__PI_ZQ_CAL_START_MAP_3_MASK 0x00000F00U

5797

#define LPDDR4__DENALI_PI_325__PI_ZQ_CAL_START_MAP_3_SHIFT 8U

5798

#define LPDDR4__DENALI_PI_325__PI_ZQ_CAL_START_MAP_3_WIDTH 4U

5799

#define LPDDR4__PI_ZQ_CAL_START_MAP_3__REG DENALI_PI_325

5800

#define LPDDR4__PI_ZQ_CAL_START_MAP_3__FLD LPDDR4__DENALI_PI_325__PI_ZQ_CAL_START_MAP_3

5801

5802

#define LPDDR4__DENALI_PI_325__PI_ZQ_CAL_LATCH_MAP_3_MASK 0x000F0000U

5803

#define LPDDR4__DENALI_PI_325__PI_ZQ_CAL_LATCH_MAP_3_SHIFT 16U

5804

#define LPDDR4__DENALI_PI_325__PI_ZQ_CAL_LATCH_MAP_3_WIDTH 4U

5805

#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_3__REG DENALI_PI_325

5806

#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_3__FLD LPDDR4__DENALI_PI_325__PI_ZQ_CAL_LATCH_MAP_3

5807

5808

#define LPDDR4__DENALI_PI_326_READ_MASK 0xFFFFFFFFU

5809

#define LPDDR4__DENALI_PI_326_WRITE_MASK 0xFFFFFFFFU

5810

#define LPDDR4__DENALI_PI_326__PI_DQS_OSC_BASE_VALUE_0_0_MASK 0x0000FFFFU

5811

#define LPDDR4__DENALI_PI_326__PI_DQS_OSC_BASE_VALUE_0_0_SHIFT 0U

5812

#define LPDDR4__DENALI_PI_326__PI_DQS_OSC_BASE_VALUE_0_0_WIDTH 16U

5813

#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_0__REG DENALI_PI_326

5814

#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_0__FLD LPDDR4__DENALI_PI_326__PI_DQS_OSC_BASE_VALUE_0_0

5815

5816

#define LPDDR4__DENALI_PI_326__PI_DQS_OSC_BASE_VALUE_1_0_MASK 0xFFFF0000U

5817

#define LPDDR4__DENALI_PI_326__PI_DQS_OSC_BASE_VALUE_1_0_SHIFT 16U

5818

#define LPDDR4__DENALI_PI_326__PI_DQS_OSC_BASE_VALUE_1_0_WIDTH 16U

5819

#define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_0__REG DENALI_PI_326

5820

#define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_0__FLD LPDDR4__DENALI_PI_326__PI_DQS_OSC_BASE_VALUE_1_0

5821

5822

#define LPDDR4__DENALI_PI_327_READ_MASK 0xFFFFFFFFU

5823

#define LPDDR4__DENALI_PI_327_WRITE_MASK 0xFFFFFFFFU

5824

#define LPDDR4__DENALI_PI_327__PI_DQS_OSC_BASE_VALUE_0_1_MASK 0x0000FFFFU

5825

#define LPDDR4__DENALI_PI_327__PI_DQS_OSC_BASE_VALUE_0_1_SHIFT 0U

5826

#define LPDDR4__DENALI_PI_327__PI_DQS_OSC_BASE_VALUE_0_1_WIDTH 16U

5827

#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_1__REG DENALI_PI_327

5828

#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_1__FLD LPDDR4__DENALI_PI_327__PI_DQS_OSC_BASE_VALUE_0_1

5829

5830

#define LPDDR4__DENALI_PI_327__PI_DQS_OSC_BASE_VALUE_1_1_MASK 0xFFFF0000U

5831

#define LPDDR4__DENALI_PI_327__PI_DQS_OSC_BASE_VALUE_1_1_SHIFT 16U

5832

#define LPDDR4__DENALI_PI_327__PI_DQS_OSC_BASE_VALUE_1_1_WIDTH 16U

5833

#define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_1__REG DENALI_PI_327

5834

#define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_1__FLD LPDDR4__DENALI_PI_327__PI_DQS_OSC_BASE_VALUE_1_1

5835

5836

#define LPDDR4__DENALI_PI_328_READ_MASK 0x0001FFFFU

5837

#define LPDDR4__DENALI_PI_328_WRITE_MASK 0x0001FFFFU

5838

#define LPDDR4__DENALI_PI_328__PI_MR0_DATA_F0_0_MASK 0x0001FFFFU

5839

#define LPDDR4__DENALI_PI_328__PI_MR0_DATA_F0_0_SHIFT 0U

5840

#define LPDDR4__DENALI_PI_328__PI_MR0_DATA_F0_0_WIDTH 17U

5841

#define LPDDR4__PI_MR0_DATA_F0_0__REG DENALI_PI_328

5842

#define LPDDR4__PI_MR0_DATA_F0_0__FLD LPDDR4__DENALI_PI_328__PI_MR0_DATA_F0_0

5843

5844

#define LPDDR4__DENALI_PI_329_READ_MASK 0x0001FFFFU

5845

#define LPDDR4__DENALI_PI_329_WRITE_MASK 0x0001FFFFU

5846

#define LPDDR4__DENALI_PI_329__PI_MR1_DATA_F0_0_MASK 0x0001FFFFU

5847

#define LPDDR4__DENALI_PI_329__PI_MR1_DATA_F0_0_SHIFT 0U

5848

#define LPDDR4__DENALI_PI_329__PI_MR1_DATA_F0_0_WIDTH 17U

5849

#define LPDDR4__PI_MR1_DATA_F0_0__REG DENALI_PI_329

5850

#define LPDDR4__PI_MR1_DATA_F0_0__FLD LPDDR4__DENALI_PI_329__PI_MR1_DATA_F0_0

5851

5852

#define LPDDR4__DENALI_PI_330_READ_MASK 0x0001FFFFU

5853

#define LPDDR4__DENALI_PI_330_WRITE_MASK 0x0001FFFFU

5854

#define LPDDR4__DENALI_PI_330__PI_MR2_DATA_F0_0_MASK 0x0001FFFFU

5855

#define LPDDR4__DENALI_PI_330__PI_MR2_DATA_F0_0_SHIFT 0U

5856

#define LPDDR4__DENALI_PI_330__PI_MR2_DATA_F0_0_WIDTH 17U

5857

#define LPDDR4__PI_MR2_DATA_F0_0__REG DENALI_PI_330

5858

#define LPDDR4__PI_MR2_DATA_F0_0__FLD LPDDR4__DENALI_PI_330__PI_MR2_DATA_F0_0

5859

5860

#define LPDDR4__DENALI_PI_331_READ_MASK 0x0001FFFFU

5861

#define LPDDR4__DENALI_PI_331_WRITE_MASK 0x0001FFFFU

5862

#define LPDDR4__DENALI_PI_331__PI_MR3_DATA_F0_0_MASK 0x0001FFFFU

5863

#define LPDDR4__DENALI_PI_331__PI_MR3_DATA_F0_0_SHIFT 0U

5864

#define LPDDR4__DENALI_PI_331__PI_MR3_DATA_F0_0_WIDTH 17U

5865

#define LPDDR4__PI_MR3_DATA_F0_0__REG DENALI_PI_331

5866

#define LPDDR4__PI_MR3_DATA_F0_0__FLD LPDDR4__DENALI_PI_331__PI_MR3_DATA_F0_0

5867

5868

#define LPDDR4__DENALI_PI_332_READ_MASK 0x0001FFFFU

5869

#define LPDDR4__DENALI_PI_332_WRITE_MASK 0x0001FFFFU

5870

#define LPDDR4__DENALI_PI_332__PI_MR4_DATA_F0_0_MASK 0x0001FFFFU

5871

#define LPDDR4__DENALI_PI_332__PI_MR4_DATA_F0_0_SHIFT 0U

5872

#define LPDDR4__DENALI_PI_332__PI_MR4_DATA_F0_0_WIDTH 17U

5873

#define LPDDR4__PI_MR4_DATA_F0_0__REG DENALI_PI_332

5874

#define LPDDR4__PI_MR4_DATA_F0_0__FLD LPDDR4__DENALI_PI_332__PI_MR4_DATA_F0_0

5875

5876

#define LPDDR4__DENALI_PI_333_READ_MASK 0x0001FFFFU

5877

#define LPDDR4__DENALI_PI_333_WRITE_MASK 0x0001FFFFU

5878

#define LPDDR4__DENALI_PI_333__PI_MR5_DATA_F0_0_MASK 0x0001FFFFU

5879

#define LPDDR4__DENALI_PI_333__PI_MR5_DATA_F0_0_SHIFT 0U

5880

#define LPDDR4__DENALI_PI_333__PI_MR5_DATA_F0_0_WIDTH 17U

5881

#define LPDDR4__PI_MR5_DATA_F0_0__REG DENALI_PI_333

5882

#define LPDDR4__PI_MR5_DATA_F0_0__FLD LPDDR4__DENALI_PI_333__PI_MR5_DATA_F0_0

5883

5884

#define LPDDR4__DENALI_PI_334_READ_MASK 0xFF01FFFFU

5885

#define LPDDR4__DENALI_PI_334_WRITE_MASK 0xFF01FFFFU

5886

#define LPDDR4__DENALI_PI_334__PI_MR6_DATA_F0_0_MASK 0x0001FFFFU

5887

#define LPDDR4__DENALI_PI_334__PI_MR6_DATA_F0_0_SHIFT 0U

5888

#define LPDDR4__DENALI_PI_334__PI_MR6_DATA_F0_0_WIDTH 17U

5889

#define LPDDR4__PI_MR6_DATA_F0_0__REG DENALI_PI_334

5890

#define LPDDR4__PI_MR6_DATA_F0_0__FLD LPDDR4__DENALI_PI_334__PI_MR6_DATA_F0_0

5891

5892

#define LPDDR4__DENALI_PI_334__PI_MR11_DATA_F0_0_MASK 0xFF000000U

5893

#define LPDDR4__DENALI_PI_334__PI_MR11_DATA_F0_0_SHIFT 24U

5894

#define LPDDR4__DENALI_PI_334__PI_MR11_DATA_F0_0_WIDTH 8U

5895

#define LPDDR4__PI_MR11_DATA_F0_0__REG DENALI_PI_334

5896

#define LPDDR4__PI_MR11_DATA_F0_0__FLD LPDDR4__DENALI_PI_334__PI_MR11_DATA_F0_0

5897

5898

#define LPDDR4__DENALI_PI_335_READ_MASK 0xFFFFFFFFU

5899

#define LPDDR4__DENALI_PI_335_WRITE_MASK 0xFFFFFFFFU

5900

#define LPDDR4__DENALI_PI_335__PI_MR12_DATA_F0_0_MASK 0x000000FFU

5901

#define LPDDR4__DENALI_PI_335__PI_MR12_DATA_F0_0_SHIFT 0U

5902

#define LPDDR4__DENALI_PI_335__PI_MR12_DATA_F0_0_WIDTH 8U

5903

#define LPDDR4__PI_MR12_DATA_F0_0__REG DENALI_PI_335

5904

#define LPDDR4__PI_MR12_DATA_F0_0__FLD LPDDR4__DENALI_PI_335__PI_MR12_DATA_F0_0

5905

5906

#define LPDDR4__DENALI_PI_335__PI_MR14_DATA_F0_0_MASK 0x0000FF00U

5907

#define LPDDR4__DENALI_PI_335__PI_MR14_DATA_F0_0_SHIFT 8U

5908

#define LPDDR4__DENALI_PI_335__PI_MR14_DATA_F0_0_WIDTH 8U

5909

#define LPDDR4__PI_MR14_DATA_F0_0__REG DENALI_PI_335

5910

#define LPDDR4__PI_MR14_DATA_F0_0__FLD LPDDR4__DENALI_PI_335__PI_MR14_DATA_F0_0

5911

5912

#define LPDDR4__DENALI_PI_335__PI_MR22_DATA_F0_0_MASK 0x00FF0000U

5913

#define LPDDR4__DENALI_PI_335__PI_MR22_DATA_F0_0_SHIFT 16U

5914

#define LPDDR4__DENALI_PI_335__PI_MR22_DATA_F0_0_WIDTH 8U

5915

#define LPDDR4__PI_MR22_DATA_F0_0__REG DENALI_PI_335

5916

#define LPDDR4__PI_MR22_DATA_F0_0__FLD LPDDR4__DENALI_PI_335__PI_MR22_DATA_F0_0

5917

5918

#define LPDDR4__DENALI_PI_335__PI_MR23_DATA_F0_0_MASK 0xFF000000U

5919

#define LPDDR4__DENALI_PI_335__PI_MR23_DATA_F0_0_SHIFT 24U

5920

#define LPDDR4__DENALI_PI_335__PI_MR23_DATA_F0_0_WIDTH 8U

5921

#define LPDDR4__PI_MR23_DATA_F0_0__REG DENALI_PI_335

5922

#define LPDDR4__PI_MR23_DATA_F0_0__FLD LPDDR4__DENALI_PI_335__PI_MR23_DATA_F0_0

5923

5924

#define LPDDR4__DENALI_PI_336_READ_MASK 0x0001FFFFU

5925

#define LPDDR4__DENALI_PI_336_WRITE_MASK 0x0001FFFFU

5926

#define LPDDR4__DENALI_PI_336__PI_MR0_DATA_F1_0_MASK 0x0001FFFFU

5927

#define LPDDR4__DENALI_PI_336__PI_MR0_DATA_F1_0_SHIFT 0U

5928

#define LPDDR4__DENALI_PI_336__PI_MR0_DATA_F1_0_WIDTH 17U

5929

#define LPDDR4__PI_MR0_DATA_F1_0__REG DENALI_PI_336

5930

#define LPDDR4__PI_MR0_DATA_F1_0__FLD LPDDR4__DENALI_PI_336__PI_MR0_DATA_F1_0

5931

5932

#define LPDDR4__DENALI_PI_337_READ_MASK 0x0001FFFFU

5933

#define LPDDR4__DENALI_PI_337_WRITE_MASK 0x0001FFFFU

5934

#define LPDDR4__DENALI_PI_337__PI_MR1_DATA_F1_0_MASK 0x0001FFFFU

5935

#define LPDDR4__DENALI_PI_337__PI_MR1_DATA_F1_0_SHIFT 0U

5936

#define LPDDR4__DENALI_PI_337__PI_MR1_DATA_F1_0_WIDTH 17U

5937

#define LPDDR4__PI_MR1_DATA_F1_0__REG DENALI_PI_337

5938

#define LPDDR4__PI_MR1_DATA_F1_0__FLD LPDDR4__DENALI_PI_337__PI_MR1_DATA_F1_0

5939

5940

#define LPDDR4__DENALI_PI_338_READ_MASK 0x0001FFFFU

5941

#define LPDDR4__DENALI_PI_338_WRITE_MASK 0x0001FFFFU

5942

#define LPDDR4__DENALI_PI_338__PI_MR2_DATA_F1_0_MASK 0x0001FFFFU

5943

#define LPDDR4__DENALI_PI_338__PI_MR2_DATA_F1_0_SHIFT 0U

5944

#define LPDDR4__DENALI_PI_338__PI_MR2_DATA_F1_0_WIDTH 17U

5945

#define LPDDR4__PI_MR2_DATA_F1_0__REG DENALI_PI_338

5946

#define LPDDR4__PI_MR2_DATA_F1_0__FLD LPDDR4__DENALI_PI_338__PI_MR2_DATA_F1_0

5947

5948

#define LPDDR4__DENALI_PI_339_READ_MASK 0x0001FFFFU

5949

#define LPDDR4__DENALI_PI_339_WRITE_MASK 0x0001FFFFU

5950

#define LPDDR4__DENALI_PI_339__PI_MR3_DATA_F1_0_MASK 0x0001FFFFU

5951

#define LPDDR4__DENALI_PI_339__PI_MR3_DATA_F1_0_SHIFT 0U

5952

#define LPDDR4__DENALI_PI_339__PI_MR3_DATA_F1_0_WIDTH 17U

5953

#define LPDDR4__PI_MR3_DATA_F1_0__REG DENALI_PI_339

5954

#define LPDDR4__PI_MR3_DATA_F1_0__FLD LPDDR4__DENALI_PI_339__PI_MR3_DATA_F1_0

5955

5956

#define LPDDR4__DENALI_PI_340_READ_MASK 0x0001FFFFU

5957

#define LPDDR4__DENALI_PI_340_WRITE_MASK 0x0001FFFFU

5958

#define LPDDR4__DENALI_PI_340__PI_MR4_DATA_F1_0_MASK 0x0001FFFFU

5959

#define LPDDR4__DENALI_PI_340__PI_MR4_DATA_F1_0_SHIFT 0U

5960

#define LPDDR4__DENALI_PI_340__PI_MR4_DATA_F1_0_WIDTH 17U

5961

#define LPDDR4__PI_MR4_DATA_F1_0__REG DENALI_PI_340

5962

#define LPDDR4__PI_MR4_DATA_F1_0__FLD LPDDR4__DENALI_PI_340__PI_MR4_DATA_F1_0

5963

5964

#define LPDDR4__DENALI_PI_341_READ_MASK 0x0001FFFFU

5965

#define LPDDR4__DENALI_PI_341_WRITE_MASK 0x0001FFFFU

5966

#define LPDDR4__DENALI_PI_341__PI_MR5_DATA_F1_0_MASK 0x0001FFFFU

5967

#define LPDDR4__DENALI_PI_341__PI_MR5_DATA_F1_0_SHIFT 0U

5968

#define LPDDR4__DENALI_PI_341__PI_MR5_DATA_F1_0_WIDTH 17U

5969

#define LPDDR4__PI_MR5_DATA_F1_0__REG DENALI_PI_341

5970

#define LPDDR4__PI_MR5_DATA_F1_0__FLD LPDDR4__DENALI_PI_341__PI_MR5_DATA_F1_0

5971

5972

#define LPDDR4__DENALI_PI_342_READ_MASK 0xFF01FFFFU

5973

#define LPDDR4__DENALI_PI_342_WRITE_MASK 0xFF01FFFFU

5974

#define LPDDR4__DENALI_PI_342__PI_MR6_DATA_F1_0_MASK 0x0001FFFFU

5975

#define LPDDR4__DENALI_PI_342__PI_MR6_DATA_F1_0_SHIFT 0U

5976

#define LPDDR4__DENALI_PI_342__PI_MR6_DATA_F1_0_WIDTH 17U

5977

#define LPDDR4__PI_MR6_DATA_F1_0__REG DENALI_PI_342

5978

#define LPDDR4__PI_MR6_DATA_F1_0__FLD LPDDR4__DENALI_PI_342__PI_MR6_DATA_F1_0

5979

5980

#define LPDDR4__DENALI_PI_342__PI_MR11_DATA_F1_0_MASK 0xFF000000U

5981

#define LPDDR4__DENALI_PI_342__PI_MR11_DATA_F1_0_SHIFT 24U

5982

#define LPDDR4__DENALI_PI_342__PI_MR11_DATA_F1_0_WIDTH 8U

5983

#define LPDDR4__PI_MR11_DATA_F1_0__REG DENALI_PI_342

5984

#define LPDDR4__PI_MR11_DATA_F1_0__FLD LPDDR4__DENALI_PI_342__PI_MR11_DATA_F1_0

5985

5986

#define LPDDR4__DENALI_PI_343_READ_MASK 0xFFFFFFFFU

5987

#define LPDDR4__DENALI_PI_343_WRITE_MASK 0xFFFFFFFFU

5988

#define LPDDR4__DENALI_PI_343__PI_MR12_DATA_F1_0_MASK 0x000000FFU

5989

#define LPDDR4__DENALI_PI_343__PI_MR12_DATA_F1_0_SHIFT 0U

5990

#define LPDDR4__DENALI_PI_343__PI_MR12_DATA_F1_0_WIDTH 8U

5991

#define LPDDR4__PI_MR12_DATA_F1_0__REG DENALI_PI_343

5992

#define LPDDR4__PI_MR12_DATA_F1_0__FLD LPDDR4__DENALI_PI_343__PI_MR12_DATA_F1_0

5993

5994

#define LPDDR4__DENALI_PI_343__PI_MR14_DATA_F1_0_MASK 0x0000FF00U

5995

#define LPDDR4__DENALI_PI_343__PI_MR14_DATA_F1_0_SHIFT 8U

5996

#define LPDDR4__DENALI_PI_343__PI_MR14_DATA_F1_0_WIDTH 8U

5997

#define LPDDR4__PI_MR14_DATA_F1_0__REG DENALI_PI_343

5998

#define LPDDR4__PI_MR14_DATA_F1_0__FLD LPDDR4__DENALI_PI_343__PI_MR14_DATA_F1_0

5999

6000

#define LPDDR4__DENALI_PI_343__PI_MR22_DATA_F1_0_MASK 0x00FF0000U

6001

#define LPDDR4__DENALI_PI_343__PI_MR22_DATA_F1_0_SHIFT 16U

6002

#define LPDDR4__DENALI_PI_343__PI_MR22_DATA_F1_0_WIDTH 8U

6003

#define LPDDR4__PI_MR22_DATA_F1_0__REG DENALI_PI_343

6004

#define LPDDR4__PI_MR22_DATA_F1_0__FLD LPDDR4__DENALI_PI_343__PI_MR22_DATA_F1_0

6005

6006

#define LPDDR4__DENALI_PI_343__PI_MR23_DATA_F1_0_MASK 0xFF000000U

6007

#define LPDDR4__DENALI_PI_343__PI_MR23_DATA_F1_0_SHIFT 24U

6008

#define LPDDR4__DENALI_PI_343__PI_MR23_DATA_F1_0_WIDTH 8U

6009

#define LPDDR4__PI_MR23_DATA_F1_0__REG DENALI_PI_343

6010

#define LPDDR4__PI_MR23_DATA_F1_0__FLD LPDDR4__DENALI_PI_343__PI_MR23_DATA_F1_0

6011

6012

#define LPDDR4__DENALI_PI_344_READ_MASK 0x0001FFFFU

6013

#define LPDDR4__DENALI_PI_344_WRITE_MASK 0x0001FFFFU

6014

#define LPDDR4__DENALI_PI_344__PI_MR0_DATA_F2_0_MASK 0x0001FFFFU

6015

#define LPDDR4__DENALI_PI_344__PI_MR0_DATA_F2_0_SHIFT 0U

6016

#define LPDDR4__DENALI_PI_344__PI_MR0_DATA_F2_0_WIDTH 17U

6017

#define LPDDR4__PI_MR0_DATA_F2_0__REG DENALI_PI_344

6018

#define LPDDR4__PI_MR0_DATA_F2_0__FLD LPDDR4__DENALI_PI_344__PI_MR0_DATA_F2_0

6019

6020

#define LPDDR4__DENALI_PI_345_READ_MASK 0x0001FFFFU

6021

#define LPDDR4__DENALI_PI_345_WRITE_MASK 0x0001FFFFU

6022

#define LPDDR4__DENALI_PI_345__PI_MR1_DATA_F2_0_MASK 0x0001FFFFU

6023

#define LPDDR4__DENALI_PI_345__PI_MR1_DATA_F2_0_SHIFT 0U

6024

#define LPDDR4__DENALI_PI_345__PI_MR1_DATA_F2_0_WIDTH 17U

6025

#define LPDDR4__PI_MR1_DATA_F2_0__REG DENALI_PI_345

6026

#define LPDDR4__PI_MR1_DATA_F2_0__FLD LPDDR4__DENALI_PI_345__PI_MR1_DATA_F2_0

6027

6028

#define LPDDR4__DENALI_PI_346_READ_MASK 0x0001FFFFU

6029

#define LPDDR4__DENALI_PI_346_WRITE_MASK 0x0001FFFFU

6030

#define LPDDR4__DENALI_PI_346__PI_MR2_DATA_F2_0_MASK 0x0001FFFFU

6031

#define LPDDR4__DENALI_PI_346__PI_MR2_DATA_F2_0_SHIFT 0U

6032

#define LPDDR4__DENALI_PI_346__PI_MR2_DATA_F2_0_WIDTH 17U

6033

#define LPDDR4__PI_MR2_DATA_F2_0__REG DENALI_PI_346

6034

#define LPDDR4__PI_MR2_DATA_F2_0__FLD LPDDR4__DENALI_PI_346__PI_MR2_DATA_F2_0

6035

6036

#define LPDDR4__DENALI_PI_347_READ_MASK 0x0001FFFFU

6037

#define LPDDR4__DENALI_PI_347_WRITE_MASK 0x0001FFFFU

6038

#define LPDDR4__DENALI_PI_347__PI_MR3_DATA_F2_0_MASK 0x0001FFFFU

6039

#define LPDDR4__DENALI_PI_347__PI_MR3_DATA_F2_0_SHIFT 0U

6040

#define LPDDR4__DENALI_PI_347__PI_MR3_DATA_F2_0_WIDTH 17U

6041

#define LPDDR4__PI_MR3_DATA_F2_0__REG DENALI_PI_347

6042

#define LPDDR4__PI_MR3_DATA_F2_0__FLD LPDDR4__DENALI_PI_347__PI_MR3_DATA_F2_0

6043

6044

#define LPDDR4__DENALI_PI_348_READ_MASK 0x0001FFFFU

6045

#define LPDDR4__DENALI_PI_348_WRITE_MASK 0x0001FFFFU

6046

#define LPDDR4__DENALI_PI_348__PI_MR4_DATA_F2_0_MASK 0x0001FFFFU

6047

#define LPDDR4__DENALI_PI_348__PI_MR4_DATA_F2_0_SHIFT 0U

6048

#define LPDDR4__DENALI_PI_348__PI_MR4_DATA_F2_0_WIDTH 17U

6049

#define LPDDR4__PI_MR4_DATA_F2_0__REG DENALI_PI_348

6050

#define LPDDR4__PI_MR4_DATA_F2_0__FLD LPDDR4__DENALI_PI_348__PI_MR4_DATA_F2_0

6051

6052

#define LPDDR4__DENALI_PI_349_READ_MASK 0x0001FFFFU

6053

#define LPDDR4__DENALI_PI_349_WRITE_MASK 0x0001FFFFU

6054

#define LPDDR4__DENALI_PI_349__PI_MR5_DATA_F2_0_MASK 0x0001FFFFU

6055

#define LPDDR4__DENALI_PI_349__PI_MR5_DATA_F2_0_SHIFT 0U

6056

#define LPDDR4__DENALI_PI_349__PI_MR5_DATA_F2_0_WIDTH 17U

6057

#define LPDDR4__PI_MR5_DATA_F2_0__REG DENALI_PI_349

6058

#define LPDDR4__PI_MR5_DATA_F2_0__FLD LPDDR4__DENALI_PI_349__PI_MR5_DATA_F2_0

6059

6060

#define LPDDR4__DENALI_PI_350_READ_MASK 0xFF01FFFFU

6061

#define LPDDR4__DENALI_PI_350_WRITE_MASK 0xFF01FFFFU

6062

#define LPDDR4__DENALI_PI_350__PI_MR6_DATA_F2_0_MASK 0x0001FFFFU

6063

#define LPDDR4__DENALI_PI_350__PI_MR6_DATA_F2_0_SHIFT 0U

6064

#define LPDDR4__DENALI_PI_350__PI_MR6_DATA_F2_0_WIDTH 17U

6065

#define LPDDR4__PI_MR6_DATA_F2_0__REG DENALI_PI_350

6066

#define LPDDR4__PI_MR6_DATA_F2_0__FLD LPDDR4__DENALI_PI_350__PI_MR6_DATA_F2_0

6067

6068

#define LPDDR4__DENALI_PI_350__PI_MR11_DATA_F2_0_MASK 0xFF000000U

6069

#define LPDDR4__DENALI_PI_350__PI_MR11_DATA_F2_0_SHIFT 24U

6070

#define LPDDR4__DENALI_PI_350__PI_MR11_DATA_F2_0_WIDTH 8U

6071

#define LPDDR4__PI_MR11_DATA_F2_0__REG DENALI_PI_350

6072

#define LPDDR4__PI_MR11_DATA_F2_0__FLD LPDDR4__DENALI_PI_350__PI_MR11_DATA_F2_0

6073

6074

#define LPDDR4__DENALI_PI_351_READ_MASK 0xFFFFFFFFU

6075

#define LPDDR4__DENALI_PI_351_WRITE_MASK 0xFFFFFFFFU

6076

#define LPDDR4__DENALI_PI_351__PI_MR12_DATA_F2_0_MASK 0x000000FFU

6077

#define LPDDR4__DENALI_PI_351__PI_MR12_DATA_F2_0_SHIFT 0U

6078

#define LPDDR4__DENALI_PI_351__PI_MR12_DATA_F2_0_WIDTH 8U

6079

#define LPDDR4__PI_MR12_DATA_F2_0__REG DENALI_PI_351

6080

#define LPDDR4__PI_MR12_DATA_F2_0__FLD LPDDR4__DENALI_PI_351__PI_MR12_DATA_F2_0

6081

6082

#define LPDDR4__DENALI_PI_351__PI_MR14_DATA_F2_0_MASK 0x0000FF00U

6083

#define LPDDR4__DENALI_PI_351__PI_MR14_DATA_F2_0_SHIFT 8U

6084

#define LPDDR4__DENALI_PI_351__PI_MR14_DATA_F2_0_WIDTH 8U

6085

#define LPDDR4__PI_MR14_DATA_F2_0__REG DENALI_PI_351

6086

#define LPDDR4__PI_MR14_DATA_F2_0__FLD LPDDR4__DENALI_PI_351__PI_MR14_DATA_F2_0

6087

6088

#define LPDDR4__DENALI_PI_351__PI_MR22_DATA_F2_0_MASK 0x00FF0000U

6089

#define LPDDR4__DENALI_PI_351__PI_MR22_DATA_F2_0_SHIFT 16U

6090

#define LPDDR4__DENALI_PI_351__PI_MR22_DATA_F2_0_WIDTH 8U

6091

#define LPDDR4__PI_MR22_DATA_F2_0__REG DENALI_PI_351

6092

#define LPDDR4__PI_MR22_DATA_F2_0__FLD LPDDR4__DENALI_PI_351__PI_MR22_DATA_F2_0

6093

6094

#define LPDDR4__DENALI_PI_351__PI_MR23_DATA_F2_0_MASK 0xFF000000U

6095

#define LPDDR4__DENALI_PI_351__PI_MR23_DATA_F2_0_SHIFT 24U

6096

#define LPDDR4__DENALI_PI_351__PI_MR23_DATA_F2_0_WIDTH 8U

6097

#define LPDDR4__PI_MR23_DATA_F2_0__REG DENALI_PI_351

6098

#define LPDDR4__PI_MR23_DATA_F2_0__FLD LPDDR4__DENALI_PI_351__PI_MR23_DATA_F2_0

6099

6100

#define LPDDR4__DENALI_PI_352_READ_MASK 0x0001FFFFU

6101

#define LPDDR4__DENALI_PI_352_WRITE_MASK 0x0001FFFFU

6102

#define LPDDR4__DENALI_PI_352__PI_MR0_DATA_F0_1_MASK 0x0001FFFFU

6103

#define LPDDR4__DENALI_PI_352__PI_MR0_DATA_F0_1_SHIFT 0U

6104

#define LPDDR4__DENALI_PI_352__PI_MR0_DATA_F0_1_WIDTH 17U

6105

#define LPDDR4__PI_MR0_DATA_F0_1__REG DENALI_PI_352

6106

#define LPDDR4__PI_MR0_DATA_F0_1__FLD LPDDR4__DENALI_PI_352__PI_MR0_DATA_F0_1

6107

6108

#define LPDDR4__DENALI_PI_353_READ_MASK 0x0001FFFFU

6109

#define LPDDR4__DENALI_PI_353_WRITE_MASK 0x0001FFFFU

6110

#define LPDDR4__DENALI_PI_353__PI_MR1_DATA_F0_1_MASK 0x0001FFFFU

6111

#define LPDDR4__DENALI_PI_353__PI_MR1_DATA_F0_1_SHIFT 0U

6112

#define LPDDR4__DENALI_PI_353__PI_MR1_DATA_F0_1_WIDTH 17U

6113

#define LPDDR4__PI_MR1_DATA_F0_1__REG DENALI_PI_353

6114

#define LPDDR4__PI_MR1_DATA_F0_1__FLD LPDDR4__DENALI_PI_353__PI_MR1_DATA_F0_1

6115

6116

#define LPDDR4__DENALI_PI_354_READ_MASK 0x0001FFFFU

6117

#define LPDDR4__DENALI_PI_354_WRITE_MASK 0x0001FFFFU

6118

#define LPDDR4__DENALI_PI_354__PI_MR2_DATA_F0_1_MASK 0x0001FFFFU

6119

#define LPDDR4__DENALI_PI_354__PI_MR2_DATA_F0_1_SHIFT 0U

6120

#define LPDDR4__DENALI_PI_354__PI_MR2_DATA_F0_1_WIDTH 17U

6121

#define LPDDR4__PI_MR2_DATA_F0_1__REG DENALI_PI_354

6122

#define LPDDR4__PI_MR2_DATA_F0_1__FLD LPDDR4__DENALI_PI_354__PI_MR2_DATA_F0_1

6123

6124

#define LPDDR4__DENALI_PI_355_READ_MASK 0x0001FFFFU

6125

#define LPDDR4__DENALI_PI_355_WRITE_MASK 0x0001FFFFU

6126

#define LPDDR4__DENALI_PI_355__PI_MR3_DATA_F0_1_MASK 0x0001FFFFU

6127

#define LPDDR4__DENALI_PI_355__PI_MR3_DATA_F0_1_SHIFT 0U

6128

#define LPDDR4__DENALI_PI_355__PI_MR3_DATA_F0_1_WIDTH 17U

6129

#define LPDDR4__PI_MR3_DATA_F0_1__REG DENALI_PI_355

6130

#define LPDDR4__PI_MR3_DATA_F0_1__FLD LPDDR4__DENALI_PI_355__PI_MR3_DATA_F0_1

6131

6132

#define LPDDR4__DENALI_PI_356_READ_MASK 0x0001FFFFU

6133

#define LPDDR4__DENALI_PI_356_WRITE_MASK 0x0001FFFFU

6134

#define LPDDR4__DENALI_PI_356__PI_MR4_DATA_F0_1_MASK 0x0001FFFFU

6135

#define LPDDR4__DENALI_PI_356__PI_MR4_DATA_F0_1_SHIFT 0U

6136

#define LPDDR4__DENALI_PI_356__PI_MR4_DATA_F0_1_WIDTH 17U

6137

#define LPDDR4__PI_MR4_DATA_F0_1__REG DENALI_PI_356

6138

#define LPDDR4__PI_MR4_DATA_F0_1__FLD LPDDR4__DENALI_PI_356__PI_MR4_DATA_F0_1

6139

6140

#define LPDDR4__DENALI_PI_357_READ_MASK 0x0001FFFFU

6141

#define LPDDR4__DENALI_PI_357_WRITE_MASK 0x0001FFFFU

6142

#define LPDDR4__DENALI_PI_357__PI_MR5_DATA_F0_1_MASK 0x0001FFFFU

6143

#define LPDDR4__DENALI_PI_357__PI_MR5_DATA_F0_1_SHIFT 0U

6144

#define LPDDR4__DENALI_PI_357__PI_MR5_DATA_F0_1_WIDTH 17U

6145

#define LPDDR4__PI_MR5_DATA_F0_1__REG DENALI_PI_357

6146

#define LPDDR4__PI_MR5_DATA_F0_1__FLD LPDDR4__DENALI_PI_357__PI_MR5_DATA_F0_1

6147

6148

#define LPDDR4__DENALI_PI_358_READ_MASK 0xFF01FFFFU

6149

#define LPDDR4__DENALI_PI_358_WRITE_MASK 0xFF01FFFFU

6150

#define LPDDR4__DENALI_PI_358__PI_MR6_DATA_F0_1_MASK 0x0001FFFFU

6151

#define LPDDR4__DENALI_PI_358__PI_MR6_DATA_F0_1_SHIFT 0U

6152

#define LPDDR4__DENALI_PI_358__PI_MR6_DATA_F0_1_WIDTH 17U

6153

#define LPDDR4__PI_MR6_DATA_F0_1__REG DENALI_PI_358

6154

#define LPDDR4__PI_MR6_DATA_F0_1__FLD LPDDR4__DENALI_PI_358__PI_MR6_DATA_F0_1

6155

6156

#define LPDDR4__DENALI_PI_358__PI_MR11_DATA_F0_1_MASK 0xFF000000U

6157

#define LPDDR4__DENALI_PI_358__PI_MR11_DATA_F0_1_SHIFT 24U

6158

#define LPDDR4__DENALI_PI_358__PI_MR11_DATA_F0_1_WIDTH 8U

6159

#define LPDDR4__PI_MR11_DATA_F0_1__REG DENALI_PI_358

6160

#define LPDDR4__PI_MR11_DATA_F0_1__FLD LPDDR4__DENALI_PI_358__PI_MR11_DATA_F0_1

6161

6162

#define LPDDR4__DENALI_PI_359_READ_MASK 0xFFFFFFFFU

6163

#define LPDDR4__DENALI_PI_359_WRITE_MASK 0xFFFFFFFFU

6164

#define LPDDR4__DENALI_PI_359__PI_MR12_DATA_F0_1_MASK 0x000000FFU

6165

#define LPDDR4__DENALI_PI_359__PI_MR12_DATA_F0_1_SHIFT 0U

6166

#define LPDDR4__DENALI_PI_359__PI_MR12_DATA_F0_1_WIDTH 8U

6167

#define LPDDR4__PI_MR12_DATA_F0_1__REG DENALI_PI_359

6168

#define LPDDR4__PI_MR12_DATA_F0_1__FLD LPDDR4__DENALI_PI_359__PI_MR12_DATA_F0_1

6169

6170

#define LPDDR4__DENALI_PI_359__PI_MR14_DATA_F0_1_MASK 0x0000FF00U

6171

#define LPDDR4__DENALI_PI_359__PI_MR14_DATA_F0_1_SHIFT 8U

6172

#define LPDDR4__DENALI_PI_359__PI_MR14_DATA_F0_1_WIDTH 8U

6173

#define LPDDR4__PI_MR14_DATA_F0_1__REG DENALI_PI_359

6174

#define LPDDR4__PI_MR14_DATA_F0_1__FLD LPDDR4__DENALI_PI_359__PI_MR14_DATA_F0_1

6175

6176

#define LPDDR4__DENALI_PI_359__PI_MR22_DATA_F0_1_MASK 0x00FF0000U

6177

#define LPDDR4__DENALI_PI_359__PI_MR22_DATA_F0_1_SHIFT 16U

6178

#define LPDDR4__DENALI_PI_359__PI_MR22_DATA_F0_1_WIDTH 8U

6179

#define LPDDR4__PI_MR22_DATA_F0_1__REG DENALI_PI_359

6180

#define LPDDR4__PI_MR22_DATA_F0_1__FLD LPDDR4__DENALI_PI_359__PI_MR22_DATA_F0_1

6181

6182

#define LPDDR4__DENALI_PI_359__PI_MR23_DATA_F0_1_MASK 0xFF000000U

6183

#define LPDDR4__DENALI_PI_359__PI_MR23_DATA_F0_1_SHIFT 24U

6184

#define LPDDR4__DENALI_PI_359__PI_MR23_DATA_F0_1_WIDTH 8U

6185

#define LPDDR4__PI_MR23_DATA_F0_1__REG DENALI_PI_359

6186

#define LPDDR4__PI_MR23_DATA_F0_1__FLD LPDDR4__DENALI_PI_359__PI_MR23_DATA_F0_1

6187

6188

#define LPDDR4__DENALI_PI_360_READ_MASK 0x0001FFFFU

6189

#define LPDDR4__DENALI_PI_360_WRITE_MASK 0x0001FFFFU

6190

#define LPDDR4__DENALI_PI_360__PI_MR0_DATA_F1_1_MASK 0x0001FFFFU

6191

#define LPDDR4__DENALI_PI_360__PI_MR0_DATA_F1_1_SHIFT 0U

6192

#define LPDDR4__DENALI_PI_360__PI_MR0_DATA_F1_1_WIDTH 17U

6193

#define LPDDR4__PI_MR0_DATA_F1_1__REG DENALI_PI_360

6194

#define LPDDR4__PI_MR0_DATA_F1_1__FLD LPDDR4__DENALI_PI_360__PI_MR0_DATA_F1_1

6195

6196

#define LPDDR4__DENALI_PI_361_READ_MASK 0x0001FFFFU

6197

#define LPDDR4__DENALI_PI_361_WRITE_MASK 0x0001FFFFU

6198

#define LPDDR4__DENALI_PI_361__PI_MR1_DATA_F1_1_MASK 0x0001FFFFU

6199

#define LPDDR4__DENALI_PI_361__PI_MR1_DATA_F1_1_SHIFT 0U

6200

#define LPDDR4__DENALI_PI_361__PI_MR1_DATA_F1_1_WIDTH 17U

6201

#define LPDDR4__PI_MR1_DATA_F1_1__REG DENALI_PI_361

6202

#define LPDDR4__PI_MR1_DATA_F1_1__FLD LPDDR4__DENALI_PI_361__PI_MR1_DATA_F1_1

6203

6204

#define LPDDR4__DENALI_PI_362_READ_MASK 0x0001FFFFU

6205

#define LPDDR4__DENALI_PI_362_WRITE_MASK 0x0001FFFFU

6206

#define LPDDR4__DENALI_PI_362__PI_MR2_DATA_F1_1_MASK 0x0001FFFFU

6207

#define LPDDR4__DENALI_PI_362__PI_MR2_DATA_F1_1_SHIFT 0U

6208

#define LPDDR4__DENALI_PI_362__PI_MR2_DATA_F1_1_WIDTH 17U

6209

#define LPDDR4__PI_MR2_DATA_F1_1__REG DENALI_PI_362

6210

#define LPDDR4__PI_MR2_DATA_F1_1__FLD LPDDR4__DENALI_PI_362__PI_MR2_DATA_F1_1

6211

6212

#define LPDDR4__DENALI_PI_363_READ_MASK 0x0001FFFFU

6213

#define LPDDR4__DENALI_PI_363_WRITE_MASK 0x0001FFFFU

6214

#define LPDDR4__DENALI_PI_363__PI_MR3_DATA_F1_1_MASK 0x0001FFFFU

6215

#define LPDDR4__DENALI_PI_363__PI_MR3_DATA_F1_1_SHIFT 0U

6216

#define LPDDR4__DENALI_PI_363__PI_MR3_DATA_F1_1_WIDTH 17U

6217

#define LPDDR4__PI_MR3_DATA_F1_1__REG DENALI_PI_363

6218

#define LPDDR4__PI_MR3_DATA_F1_1__FLD LPDDR4__DENALI_PI_363__PI_MR3_DATA_F1_1

6219

6220

#define LPDDR4__DENALI_PI_364_READ_MASK 0x0001FFFFU

6221

#define LPDDR4__DENALI_PI_364_WRITE_MASK 0x0001FFFFU

6222

#define LPDDR4__DENALI_PI_364__PI_MR4_DATA_F1_1_MASK 0x0001FFFFU

6223

#define LPDDR4__DENALI_PI_364__PI_MR4_DATA_F1_1_SHIFT 0U

6224

#define LPDDR4__DENALI_PI_364__PI_MR4_DATA_F1_1_WIDTH 17U

6225

#define LPDDR4__PI_MR4_DATA_F1_1__REG DENALI_PI_364

6226

#define LPDDR4__PI_MR4_DATA_F1_1__FLD LPDDR4__DENALI_PI_364__PI_MR4_DATA_F1_1

6227

6228

#define LPDDR4__DENALI_PI_365_READ_MASK 0x0001FFFFU

6229

#define LPDDR4__DENALI_PI_365_WRITE_MASK 0x0001FFFFU

6230

#define LPDDR4__DENALI_PI_365__PI_MR5_DATA_F1_1_MASK 0x0001FFFFU

6231

#define LPDDR4__DENALI_PI_365__PI_MR5_DATA_F1_1_SHIFT 0U

6232

#define LPDDR4__DENALI_PI_365__PI_MR5_DATA_F1_1_WIDTH 17U

6233

#define LPDDR4__PI_MR5_DATA_F1_1__REG DENALI_PI_365

6234

#define LPDDR4__PI_MR5_DATA_F1_1__FLD LPDDR4__DENALI_PI_365__PI_MR5_DATA_F1_1

6235

6236

#define LPDDR4__DENALI_PI_366_READ_MASK 0xFF01FFFFU

6237

#define LPDDR4__DENALI_PI_366_WRITE_MASK 0xFF01FFFFU

6238

#define LPDDR4__DENALI_PI_366__PI_MR6_DATA_F1_1_MASK 0x0001FFFFU

6239

#define LPDDR4__DENALI_PI_366__PI_MR6_DATA_F1_1_SHIFT 0U

6240

#define LPDDR4__DENALI_PI_366__PI_MR6_DATA_F1_1_WIDTH 17U

6241

#define LPDDR4__PI_MR6_DATA_F1_1__REG DENALI_PI_366

6242

#define LPDDR4__PI_MR6_DATA_F1_1__FLD LPDDR4__DENALI_PI_366__PI_MR6_DATA_F1_1

6243

6244

#define LPDDR4__DENALI_PI_366__PI_MR11_DATA_F1_1_MASK 0xFF000000U

6245

#define LPDDR4__DENALI_PI_366__PI_MR11_DATA_F1_1_SHIFT 24U

6246

#define LPDDR4__DENALI_PI_366__PI_MR11_DATA_F1_1_WIDTH 8U

6247

#define LPDDR4__PI_MR11_DATA_F1_1__REG DENALI_PI_366

6248

#define LPDDR4__PI_MR11_DATA_F1_1__FLD LPDDR4__DENALI_PI_366__PI_MR11_DATA_F1_1

6249

6250

#define LPDDR4__DENALI_PI_367_READ_MASK 0xFFFFFFFFU

6251

#define LPDDR4__DENALI_PI_367_WRITE_MASK 0xFFFFFFFFU

6252

#define LPDDR4__DENALI_PI_367__PI_MR12_DATA_F1_1_MASK 0x000000FFU

6253

#define LPDDR4__DENALI_PI_367__PI_MR12_DATA_F1_1_SHIFT 0U

6254

#define LPDDR4__DENALI_PI_367__PI_MR12_DATA_F1_1_WIDTH 8U

6255

#define LPDDR4__PI_MR12_DATA_F1_1__REG DENALI_PI_367

6256

#define LPDDR4__PI_MR12_DATA_F1_1__FLD LPDDR4__DENALI_PI_367__PI_MR12_DATA_F1_1

6257

6258

#define LPDDR4__DENALI_PI_367__PI_MR14_DATA_F1_1_MASK 0x0000FF00U

6259

#define LPDDR4__DENALI_PI_367__PI_MR14_DATA_F1_1_SHIFT 8U

6260

#define LPDDR4__DENALI_PI_367__PI_MR14_DATA_F1_1_WIDTH 8U

6261

#define LPDDR4__PI_MR14_DATA_F1_1__REG DENALI_PI_367

6262

#define LPDDR4__PI_MR14_DATA_F1_1__FLD LPDDR4__DENALI_PI_367__PI_MR14_DATA_F1_1

6263

6264

#define LPDDR4__DENALI_PI_367__PI_MR22_DATA_F1_1_MASK 0x00FF0000U

6265

#define LPDDR4__DENALI_PI_367__PI_MR22_DATA_F1_1_SHIFT 16U

6266

#define LPDDR4__DENALI_PI_367__PI_MR22_DATA_F1_1_WIDTH 8U

6267

#define LPDDR4__PI_MR22_DATA_F1_1__REG DENALI_PI_367

6268

#define LPDDR4__PI_MR22_DATA_F1_1__FLD LPDDR4__DENALI_PI_367__PI_MR22_DATA_F1_1

6269

6270

#define LPDDR4__DENALI_PI_367__PI_MR23_DATA_F1_1_MASK 0xFF000000U

6271

#define LPDDR4__DENALI_PI_367__PI_MR23_DATA_F1_1_SHIFT 24U

6272

#define LPDDR4__DENALI_PI_367__PI_MR23_DATA_F1_1_WIDTH 8U

6273

#define LPDDR4__PI_MR23_DATA_F1_1__REG DENALI_PI_367

6274

#define LPDDR4__PI_MR23_DATA_F1_1__FLD LPDDR4__DENALI_PI_367__PI_MR23_DATA_F1_1

6275

6276

#define LPDDR4__DENALI_PI_368_READ_MASK 0x0001FFFFU

6277

#define LPDDR4__DENALI_PI_368_WRITE_MASK 0x0001FFFFU

6278

#define LPDDR4__DENALI_PI_368__PI_MR0_DATA_F2_1_MASK 0x0001FFFFU

6279

#define LPDDR4__DENALI_PI_368__PI_MR0_DATA_F2_1_SHIFT 0U

6280

#define LPDDR4__DENALI_PI_368__PI_MR0_DATA_F2_1_WIDTH 17U

6281

#define LPDDR4__PI_MR0_DATA_F2_1__REG DENALI_PI_368

6282

#define LPDDR4__PI_MR0_DATA_F2_1__FLD LPDDR4__DENALI_PI_368__PI_MR0_DATA_F2_1

6283

6284

#define LPDDR4__DENALI_PI_369_READ_MASK 0x0001FFFFU

6285

#define LPDDR4__DENALI_PI_369_WRITE_MASK 0x0001FFFFU

6286

#define LPDDR4__DENALI_PI_369__PI_MR1_DATA_F2_1_MASK 0x0001FFFFU

6287

#define LPDDR4__DENALI_PI_369__PI_MR1_DATA_F2_1_SHIFT 0U

6288

#define LPDDR4__DENALI_PI_369__PI_MR1_DATA_F2_1_WIDTH 17U

6289

#define LPDDR4__PI_MR1_DATA_F2_1__REG DENALI_PI_369

6290

#define LPDDR4__PI_MR1_DATA_F2_1__FLD LPDDR4__DENALI_PI_369__PI_MR1_DATA_F2_1

6291

6292

#define LPDDR4__DENALI_PI_370_READ_MASK 0x0001FFFFU

6293

#define LPDDR4__DENALI_PI_370_WRITE_MASK 0x0001FFFFU

6294

#define LPDDR4__DENALI_PI_370__PI_MR2_DATA_F2_1_MASK 0x0001FFFFU

6295

#define LPDDR4__DENALI_PI_370__PI_MR2_DATA_F2_1_SHIFT 0U

6296

#define LPDDR4__DENALI_PI_370__PI_MR2_DATA_F2_1_WIDTH 17U

6297

#define LPDDR4__PI_MR2_DATA_F2_1__REG DENALI_PI_370

6298

#define LPDDR4__PI_MR2_DATA_F2_1__FLD LPDDR4__DENALI_PI_370__PI_MR2_DATA_F2_1

6299

6300

#define LPDDR4__DENALI_PI_371_READ_MASK 0x0001FFFFU

6301

#define LPDDR4__DENALI_PI_371_WRITE_MASK 0x0001FFFFU

6302

#define LPDDR4__DENALI_PI_371__PI_MR3_DATA_F2_1_MASK 0x0001FFFFU

6303

#define LPDDR4__DENALI_PI_371__PI_MR3_DATA_F2_1_SHIFT 0U

6304

#define LPDDR4__DENALI_PI_371__PI_MR3_DATA_F2_1_WIDTH 17U

6305

#define LPDDR4__PI_MR3_DATA_F2_1__REG DENALI_PI_371

6306

#define LPDDR4__PI_MR3_DATA_F2_1__FLD LPDDR4__DENALI_PI_371__PI_MR3_DATA_F2_1

6307

6308

#define LPDDR4__DENALI_PI_372_READ_MASK 0x0001FFFFU

6309

#define LPDDR4__DENALI_PI_372_WRITE_MASK 0x0001FFFFU

6310

#define LPDDR4__DENALI_PI_372__PI_MR4_DATA_F2_1_MASK 0x0001FFFFU

6311

#define LPDDR4__DENALI_PI_372__PI_MR4_DATA_F2_1_SHIFT 0U

6312

#define LPDDR4__DENALI_PI_372__PI_MR4_DATA_F2_1_WIDTH 17U

6313

#define LPDDR4__PI_MR4_DATA_F2_1__REG DENALI_PI_372

6314

#define LPDDR4__PI_MR4_DATA_F2_1__FLD LPDDR4__DENALI_PI_372__PI_MR4_DATA_F2_1

6315

6316

#define LPDDR4__DENALI_PI_373_READ_MASK 0x0001FFFFU

6317

#define LPDDR4__DENALI_PI_373_WRITE_MASK 0x0001FFFFU

6318

#define LPDDR4__DENALI_PI_373__PI_MR5_DATA_F2_1_MASK 0x0001FFFFU

6319

#define LPDDR4__DENALI_PI_373__PI_MR5_DATA_F2_1_SHIFT 0U

6320

#define LPDDR4__DENALI_PI_373__PI_MR5_DATA_F2_1_WIDTH 17U

6321

#define LPDDR4__PI_MR5_DATA_F2_1__REG DENALI_PI_373

6322

#define LPDDR4__PI_MR5_DATA_F2_1__FLD LPDDR4__DENALI_PI_373__PI_MR5_DATA_F2_1

6323

6324

#define LPDDR4__DENALI_PI_374_READ_MASK 0xFF01FFFFU

6325

#define LPDDR4__DENALI_PI_374_WRITE_MASK 0xFF01FFFFU

6326

#define LPDDR4__DENALI_PI_374__PI_MR6_DATA_F2_1_MASK 0x0001FFFFU

6327

#define LPDDR4__DENALI_PI_374__PI_MR6_DATA_F2_1_SHIFT 0U

6328

#define LPDDR4__DENALI_PI_374__PI_MR6_DATA_F2_1_WIDTH 17U

6329

#define LPDDR4__PI_MR6_DATA_F2_1__REG DENALI_PI_374

6330

#define LPDDR4__PI_MR6_DATA_F2_1__FLD LPDDR4__DENALI_PI_374__PI_MR6_DATA_F2_1

6331

6332

#define LPDDR4__DENALI_PI_374__PI_MR11_DATA_F2_1_MASK 0xFF000000U

6333

#define LPDDR4__DENALI_PI_374__PI_MR11_DATA_F2_1_SHIFT 24U

6334

#define LPDDR4__DENALI_PI_374__PI_MR11_DATA_F2_1_WIDTH 8U

6335

#define LPDDR4__PI_MR11_DATA_F2_1__REG DENALI_PI_374

6336

#define LPDDR4__PI_MR11_DATA_F2_1__FLD LPDDR4__DENALI_PI_374__PI_MR11_DATA_F2_1

6337

6338

#define LPDDR4__DENALI_PI_375_READ_MASK 0xFFFFFFFFU

6339

#define LPDDR4__DENALI_PI_375_WRITE_MASK 0xFFFFFFFFU

6340

#define LPDDR4__DENALI_PI_375__PI_MR12_DATA_F2_1_MASK 0x000000FFU

6341

#define LPDDR4__DENALI_PI_375__PI_MR12_DATA_F2_1_SHIFT 0U

6342

#define LPDDR4__DENALI_PI_375__PI_MR12_DATA_F2_1_WIDTH 8U

6343

#define LPDDR4__PI_MR12_DATA_F2_1__REG DENALI_PI_375

6344

#define LPDDR4__PI_MR12_DATA_F2_1__FLD LPDDR4__DENALI_PI_375__PI_MR12_DATA_F2_1

6345

6346

#define LPDDR4__DENALI_PI_375__PI_MR14_DATA_F2_1_MASK 0x0000FF00U

6347

#define LPDDR4__DENALI_PI_375__PI_MR14_DATA_F2_1_SHIFT 8U

6348

#define LPDDR4__DENALI_PI_375__PI_MR14_DATA_F2_1_WIDTH 8U

6349

#define LPDDR4__PI_MR14_DATA_F2_1__REG DENALI_PI_375

6350

#define LPDDR4__PI_MR14_DATA_F2_1__FLD LPDDR4__DENALI_PI_375__PI_MR14_DATA_F2_1

6351

6352

#define LPDDR4__DENALI_PI_375__PI_MR22_DATA_F2_1_MASK 0x00FF0000U

6353

#define LPDDR4__DENALI_PI_375__PI_MR22_DATA_F2_1_SHIFT 16U

6354

#define LPDDR4__DENALI_PI_375__PI_MR22_DATA_F2_1_WIDTH 8U

6355

#define LPDDR4__PI_MR22_DATA_F2_1__REG DENALI_PI_375

6356

#define LPDDR4__PI_MR22_DATA_F2_1__FLD LPDDR4__DENALI_PI_375__PI_MR22_DATA_F2_1

6357

6358

#define LPDDR4__DENALI_PI_375__PI_MR23_DATA_F2_1_MASK 0xFF000000U

6359

#define LPDDR4__DENALI_PI_375__PI_MR23_DATA_F2_1_SHIFT 24U

6360

#define LPDDR4__DENALI_PI_375__PI_MR23_DATA_F2_1_WIDTH 8U

6361

#define LPDDR4__PI_MR23_DATA_F2_1__REG DENALI_PI_375

6362

#define LPDDR4__PI_MR23_DATA_F2_1__FLD LPDDR4__DENALI_PI_375__PI_MR23_DATA_F2_1

6363

6364

#define LPDDR4__DENALI_PI_376_READ_MASK 0x0001FFFFU

6365

#define LPDDR4__DENALI_PI_376_WRITE_MASK 0x0001FFFFU

6366

#define LPDDR4__DENALI_PI_376__PI_MR0_DATA_F0_2_MASK 0x0001FFFFU

6367

#define LPDDR4__DENALI_PI_376__PI_MR0_DATA_F0_2_SHIFT 0U

6368

#define LPDDR4__DENALI_PI_376__PI_MR0_DATA_F0_2_WIDTH 17U

6369

#define LPDDR4__PI_MR0_DATA_F0_2__REG DENALI_PI_376

6370

#define LPDDR4__PI_MR0_DATA_F0_2__FLD LPDDR4__DENALI_PI_376__PI_MR0_DATA_F0_2

6371

6372

#define LPDDR4__DENALI_PI_377_READ_MASK 0x0001FFFFU

6373

#define LPDDR4__DENALI_PI_377_WRITE_MASK 0x0001FFFFU

6374

#define LPDDR4__DENALI_PI_377__PI_MR1_DATA_F0_2_MASK 0x0001FFFFU

6375

#define LPDDR4__DENALI_PI_377__PI_MR1_DATA_F0_2_SHIFT 0U

6376

#define LPDDR4__DENALI_PI_377__PI_MR1_DATA_F0_2_WIDTH 17U

6377

#define LPDDR4__PI_MR1_DATA_F0_2__REG DENALI_PI_377

6378

#define LPDDR4__PI_MR1_DATA_F0_2__FLD LPDDR4__DENALI_PI_377__PI_MR1_DATA_F0_2

6379

6380

#define LPDDR4__DENALI_PI_378_READ_MASK 0x0001FFFFU

6381

#define LPDDR4__DENALI_PI_378_WRITE_MASK 0x0001FFFFU

6382

#define LPDDR4__DENALI_PI_378__PI_MR2_DATA_F0_2_MASK 0x0001FFFFU

6383

#define LPDDR4__DENALI_PI_378__PI_MR2_DATA_F0_2_SHIFT 0U

6384

#define LPDDR4__DENALI_PI_378__PI_MR2_DATA_F0_2_WIDTH 17U

6385

#define LPDDR4__PI_MR2_DATA_F0_2__REG DENALI_PI_378

6386

#define LPDDR4__PI_MR2_DATA_F0_2__FLD LPDDR4__DENALI_PI_378__PI_MR2_DATA_F0_2

6387

6388

#define LPDDR4__DENALI_PI_379_READ_MASK 0x0001FFFFU

6389

#define LPDDR4__DENALI_PI_379_WRITE_MASK 0x0001FFFFU

6390

#define LPDDR4__DENALI_PI_379__PI_MR3_DATA_F0_2_MASK 0x0001FFFFU

6391

#define LPDDR4__DENALI_PI_379__PI_MR3_DATA_F0_2_SHIFT 0U

6392

#define LPDDR4__DENALI_PI_379__PI_MR3_DATA_F0_2_WIDTH 17U

6393

#define LPDDR4__PI_MR3_DATA_F0_2__REG DENALI_PI_379

6394

#define LPDDR4__PI_MR3_DATA_F0_2__FLD LPDDR4__DENALI_PI_379__PI_MR3_DATA_F0_2

6395

6396

#define LPDDR4__DENALI_PI_380_READ_MASK 0x0001FFFFU

6397

#define LPDDR4__DENALI_PI_380_WRITE_MASK 0x0001FFFFU

6398

#define LPDDR4__DENALI_PI_380__PI_MR4_DATA_F0_2_MASK 0x0001FFFFU

6399

#define LPDDR4__DENALI_PI_380__PI_MR4_DATA_F0_2_SHIFT 0U

6400

#define LPDDR4__DENALI_PI_380__PI_MR4_DATA_F0_2_WIDTH 17U

6401

#define LPDDR4__PI_MR4_DATA_F0_2__REG DENALI_PI_380

6402

#define LPDDR4__PI_MR4_DATA_F0_2__FLD LPDDR4__DENALI_PI_380__PI_MR4_DATA_F0_2

6403

6404

#define LPDDR4__DENALI_PI_381_READ_MASK 0x0001FFFFU

6405

#define LPDDR4__DENALI_PI_381_WRITE_MASK 0x0001FFFFU

6406

#define LPDDR4__DENALI_PI_381__PI_MR5_DATA_F0_2_MASK 0x0001FFFFU

6407

#define LPDDR4__DENALI_PI_381__PI_MR5_DATA_F0_2_SHIFT 0U

6408

#define LPDDR4__DENALI_PI_381__PI_MR5_DATA_F0_2_WIDTH 17U

6409

#define LPDDR4__PI_MR5_DATA_F0_2__REG DENALI_PI_381

6410

#define LPDDR4__PI_MR5_DATA_F0_2__FLD LPDDR4__DENALI_PI_381__PI_MR5_DATA_F0_2

6411

6412

#define LPDDR4__DENALI_PI_382_READ_MASK 0xFF01FFFFU

6413

#define LPDDR4__DENALI_PI_382_WRITE_MASK 0xFF01FFFFU

6414

#define LPDDR4__DENALI_PI_382__PI_MR6_DATA_F0_2_MASK 0x0001FFFFU

6415

#define LPDDR4__DENALI_PI_382__PI_MR6_DATA_F0_2_SHIFT 0U

6416

#define LPDDR4__DENALI_PI_382__PI_MR6_DATA_F0_2_WIDTH 17U

6417

#define LPDDR4__PI_MR6_DATA_F0_2__REG DENALI_PI_382

6418

#define LPDDR4__PI_MR6_DATA_F0_2__FLD LPDDR4__DENALI_PI_382__PI_MR6_DATA_F0_2

6419

6420

#define LPDDR4__DENALI_PI_382__PI_MR11_DATA_F0_2_MASK 0xFF000000U

6421

#define LPDDR4__DENALI_PI_382__PI_MR11_DATA_F0_2_SHIFT 24U

6422

#define LPDDR4__DENALI_PI_382__PI_MR11_DATA_F0_2_WIDTH 8U

6423

#define LPDDR4__PI_MR11_DATA_F0_2__REG DENALI_PI_382

6424

#define LPDDR4__PI_MR11_DATA_F0_2__FLD LPDDR4__DENALI_PI_382__PI_MR11_DATA_F0_2

6425

6426

#define LPDDR4__DENALI_PI_383_READ_MASK 0xFFFFFFFFU

6427

#define LPDDR4__DENALI_PI_383_WRITE_MASK 0xFFFFFFFFU

6428

#define LPDDR4__DENALI_PI_383__PI_MR12_DATA_F0_2_MASK 0x000000FFU

6429

#define LPDDR4__DENALI_PI_383__PI_MR12_DATA_F0_2_SHIFT 0U

6430

#define LPDDR4__DENALI_PI_383__PI_MR12_DATA_F0_2_WIDTH 8U

6431

#define LPDDR4__PI_MR12_DATA_F0_2__REG DENALI_PI_383

6432

#define LPDDR4__PI_MR12_DATA_F0_2__FLD LPDDR4__DENALI_PI_383__PI_MR12_DATA_F0_2

6433

6434

#define LPDDR4__DENALI_PI_383__PI_MR14_DATA_F0_2_MASK 0x0000FF00U

6435

#define LPDDR4__DENALI_PI_383__PI_MR14_DATA_F0_2_SHIFT 8U

6436

#define LPDDR4__DENALI_PI_383__PI_MR14_DATA_F0_2_WIDTH 8U

6437

#define LPDDR4__PI_MR14_DATA_F0_2__REG DENALI_PI_383

6438

#define LPDDR4__PI_MR14_DATA_F0_2__FLD LPDDR4__DENALI_PI_383__PI_MR14_DATA_F0_2

6439

6440

#define LPDDR4__DENALI_PI_383__PI_MR22_DATA_F0_2_MASK 0x00FF0000U

6441

#define LPDDR4__DENALI_PI_383__PI_MR22_DATA_F0_2_SHIFT 16U

6442

#define LPDDR4__DENALI_PI_383__PI_MR22_DATA_F0_2_WIDTH 8U

6443

#define LPDDR4__PI_MR22_DATA_F0_2__REG DENALI_PI_383

6444

#define LPDDR4__PI_MR22_DATA_F0_2__FLD LPDDR4__DENALI_PI_383__PI_MR22_DATA_F0_2

6445

6446

#define LPDDR4__DENALI_PI_383__PI_MR23_DATA_F0_2_MASK 0xFF000000U

6447

#define LPDDR4__DENALI_PI_383__PI_MR23_DATA_F0_2_SHIFT 24U

6448

#define LPDDR4__DENALI_PI_383__PI_MR23_DATA_F0_2_WIDTH 8U

6449

#define LPDDR4__PI_MR23_DATA_F0_2__REG DENALI_PI_383

6450

#define LPDDR4__PI_MR23_DATA_F0_2__FLD LPDDR4__DENALI_PI_383__PI_MR23_DATA_F0_2

6451

6452

#define LPDDR4__DENALI_PI_384_READ_MASK 0x0001FFFFU

6453

#define LPDDR4__DENALI_PI_384_WRITE_MASK 0x0001FFFFU

6454

#define LPDDR4__DENALI_PI_384__PI_MR0_DATA_F1_2_MASK 0x0001FFFFU

6455

#define LPDDR4__DENALI_PI_384__PI_MR0_DATA_F1_2_SHIFT 0U

6456

#define LPDDR4__DENALI_PI_384__PI_MR0_DATA_F1_2_WIDTH 17U

6457

#define LPDDR4__PI_MR0_DATA_F1_2__REG DENALI_PI_384

6458

#define LPDDR4__PI_MR0_DATA_F1_2__FLD LPDDR4__DENALI_PI_384__PI_MR0_DATA_F1_2

6459

6460

#define LPDDR4__DENALI_PI_385_READ_MASK 0x0001FFFFU

6461

#define LPDDR4__DENALI_PI_385_WRITE_MASK 0x0001FFFFU

6462

#define LPDDR4__DENALI_PI_385__PI_MR1_DATA_F1_2_MASK 0x0001FFFFU

6463

#define LPDDR4__DENALI_PI_385__PI_MR1_DATA_F1_2_SHIFT 0U

6464

#define LPDDR4__DENALI_PI_385__PI_MR1_DATA_F1_2_WIDTH 17U

6465

#define LPDDR4__PI_MR1_DATA_F1_2__REG DENALI_PI_385

6466

#define LPDDR4__PI_MR1_DATA_F1_2__FLD LPDDR4__DENALI_PI_385__PI_MR1_DATA_F1_2

6467

6468

#define LPDDR4__DENALI_PI_386_READ_MASK 0x0001FFFFU

6469

#define LPDDR4__DENALI_PI_386_WRITE_MASK 0x0001FFFFU

6470

#define LPDDR4__DENALI_PI_386__PI_MR2_DATA_F1_2_MASK 0x0001FFFFU

6471

#define LPDDR4__DENALI_PI_386__PI_MR2_DATA_F1_2_SHIFT 0U

6472

#define LPDDR4__DENALI_PI_386__PI_MR2_DATA_F1_2_WIDTH 17U

6473

#define LPDDR4__PI_MR2_DATA_F1_2__REG DENALI_PI_386

6474

#define LPDDR4__PI_MR2_DATA_F1_2__FLD LPDDR4__DENALI_PI_386__PI_MR2_DATA_F1_2

6475

6476

#define LPDDR4__DENALI_PI_387_READ_MASK 0x0001FFFFU

6477

#define LPDDR4__DENALI_PI_387_WRITE_MASK 0x0001FFFFU

6478

#define LPDDR4__DENALI_PI_387__PI_MR3_DATA_F1_2_MASK 0x0001FFFFU

6479

#define LPDDR4__DENALI_PI_387__PI_MR3_DATA_F1_2_SHIFT 0U

6480

#define LPDDR4__DENALI_PI_387__PI_MR3_DATA_F1_2_WIDTH 17U

6481

#define LPDDR4__PI_MR3_DATA_F1_2__REG DENALI_PI_387

6482

#define LPDDR4__PI_MR3_DATA_F1_2__FLD LPDDR4__DENALI_PI_387__PI_MR3_DATA_F1_2

6483

6484

#define LPDDR4__DENALI_PI_388_READ_MASK 0x0001FFFFU

6485

#define LPDDR4__DENALI_PI_388_WRITE_MASK 0x0001FFFFU

6486

#define LPDDR4__DENALI_PI_388__PI_MR4_DATA_F1_2_MASK 0x0001FFFFU

6487

#define LPDDR4__DENALI_PI_388__PI_MR4_DATA_F1_2_SHIFT 0U

6488

#define LPDDR4__DENALI_PI_388__PI_MR4_DATA_F1_2_WIDTH 17U

6489

#define LPDDR4__PI_MR4_DATA_F1_2__REG DENALI_PI_388

6490

#define LPDDR4__PI_MR4_DATA_F1_2__FLD LPDDR4__DENALI_PI_388__PI_MR4_DATA_F1_2

6491

6492

#define LPDDR4__DENALI_PI_389_READ_MASK 0x0001FFFFU

6493

#define LPDDR4__DENALI_PI_389_WRITE_MASK 0x0001FFFFU

6494

#define LPDDR4__DENALI_PI_389__PI_MR5_DATA_F1_2_MASK 0x0001FFFFU

6495

#define LPDDR4__DENALI_PI_389__PI_MR5_DATA_F1_2_SHIFT 0U

6496

#define LPDDR4__DENALI_PI_389__PI_MR5_DATA_F1_2_WIDTH 17U

6497

#define LPDDR4__PI_MR5_DATA_F1_2__REG DENALI_PI_389

6498

#define LPDDR4__PI_MR5_DATA_F1_2__FLD LPDDR4__DENALI_PI_389__PI_MR5_DATA_F1_2

6499

6500

#define LPDDR4__DENALI_PI_390_READ_MASK 0xFF01FFFFU

6501

#define LPDDR4__DENALI_PI_390_WRITE_MASK 0xFF01FFFFU

6502

#define LPDDR4__DENALI_PI_390__PI_MR6_DATA_F1_2_MASK 0x0001FFFFU

6503

#define LPDDR4__DENALI_PI_390__PI_MR6_DATA_F1_2_SHIFT 0U

6504

#define LPDDR4__DENALI_PI_390__PI_MR6_DATA_F1_2_WIDTH 17U

6505

#define LPDDR4__PI_MR6_DATA_F1_2__REG DENALI_PI_390

6506

#define LPDDR4__PI_MR6_DATA_F1_2__FLD LPDDR4__DENALI_PI_390__PI_MR6_DATA_F1_2

6507

6508

#define LPDDR4__DENALI_PI_390__PI_MR11_DATA_F1_2_MASK 0xFF000000U

6509

#define LPDDR4__DENALI_PI_390__PI_MR11_DATA_F1_2_SHIFT 24U

6510

#define LPDDR4__DENALI_PI_390__PI_MR11_DATA_F1_2_WIDTH 8U

6511

#define LPDDR4__PI_MR11_DATA_F1_2__REG DENALI_PI_390

6512

#define LPDDR4__PI_MR11_DATA_F1_2__FLD LPDDR4__DENALI_PI_390__PI_MR11_DATA_F1_2

6513

6514

#define LPDDR4__DENALI_PI_391_READ_MASK 0xFFFFFFFFU

6515

#define LPDDR4__DENALI_PI_391_WRITE_MASK 0xFFFFFFFFU

6516

#define LPDDR4__DENALI_PI_391__PI_MR12_DATA_F1_2_MASK 0x000000FFU

6517

#define LPDDR4__DENALI_PI_391__PI_MR12_DATA_F1_2_SHIFT 0U

6518

#define LPDDR4__DENALI_PI_391__PI_MR12_DATA_F1_2_WIDTH 8U

6519

#define LPDDR4__PI_MR12_DATA_F1_2__REG DENALI_PI_391

6520

#define LPDDR4__PI_MR12_DATA_F1_2__FLD LPDDR4__DENALI_PI_391__PI_MR12_DATA_F1_2

6521

6522

#define LPDDR4__DENALI_PI_391__PI_MR14_DATA_F1_2_MASK 0x0000FF00U

6523

#define LPDDR4__DENALI_PI_391__PI_MR14_DATA_F1_2_SHIFT 8U

6524

#define LPDDR4__DENALI_PI_391__PI_MR14_DATA_F1_2_WIDTH 8U

6525

#define LPDDR4__PI_MR14_DATA_F1_2__REG DENALI_PI_391

6526

#define LPDDR4__PI_MR14_DATA_F1_2__FLD LPDDR4__DENALI_PI_391__PI_MR14_DATA_F1_2

6527

6528

#define LPDDR4__DENALI_PI_391__PI_MR22_DATA_F1_2_MASK 0x00FF0000U

6529

#define LPDDR4__DENALI_PI_391__PI_MR22_DATA_F1_2_SHIFT 16U

6530

#define LPDDR4__DENALI_PI_391__PI_MR22_DATA_F1_2_WIDTH 8U

6531

#define LPDDR4__PI_MR22_DATA_F1_2__REG DENALI_PI_391

6532

#define LPDDR4__PI_MR22_DATA_F1_2__FLD LPDDR4__DENALI_PI_391__PI_MR22_DATA_F1_2

6533

6534

#define LPDDR4__DENALI_PI_391__PI_MR23_DATA_F1_2_MASK 0xFF000000U

6535

#define LPDDR4__DENALI_PI_391__PI_MR23_DATA_F1_2_SHIFT 24U

6536

#define LPDDR4__DENALI_PI_391__PI_MR23_DATA_F1_2_WIDTH 8U

6537

#define LPDDR4__PI_MR23_DATA_F1_2__REG DENALI_PI_391

6538

#define LPDDR4__PI_MR23_DATA_F1_2__FLD LPDDR4__DENALI_PI_391__PI_MR23_DATA_F1_2

6539

6540

#define LPDDR4__DENALI_PI_392_READ_MASK 0x0001FFFFU

6541

#define LPDDR4__DENALI_PI_392_WRITE_MASK 0x0001FFFFU

6542

#define LPDDR4__DENALI_PI_392__PI_MR0_DATA_F2_2_MASK 0x0001FFFFU

6543

#define LPDDR4__DENALI_PI_392__PI_MR0_DATA_F2_2_SHIFT 0U

6544

#define LPDDR4__DENALI_PI_392__PI_MR0_DATA_F2_2_WIDTH 17U

6545

#define LPDDR4__PI_MR0_DATA_F2_2__REG DENALI_PI_392

6546

#define LPDDR4__PI_MR0_DATA_F2_2__FLD LPDDR4__DENALI_PI_392__PI_MR0_DATA_F2_2

6547

6548

#define LPDDR4__DENALI_PI_393_READ_MASK 0x0001FFFFU

6549

#define LPDDR4__DENALI_PI_393_WRITE_MASK 0x0001FFFFU

6550

#define LPDDR4__DENALI_PI_393__PI_MR1_DATA_F2_2_MASK 0x0001FFFFU

6551

#define LPDDR4__DENALI_PI_393__PI_MR1_DATA_F2_2_SHIFT 0U

6552

#define LPDDR4__DENALI_PI_393__PI_MR1_DATA_F2_2_WIDTH 17U

6553

#define LPDDR4__PI_MR1_DATA_F2_2__REG DENALI_PI_393

6554

#define LPDDR4__PI_MR1_DATA_F2_2__FLD LPDDR4__DENALI_PI_393__PI_MR1_DATA_F2_2

6555

6556

#define LPDDR4__DENALI_PI_394_READ_MASK 0x0001FFFFU

6557

#define LPDDR4__DENALI_PI_394_WRITE_MASK 0x0001FFFFU

6558

#define LPDDR4__DENALI_PI_394__PI_MR2_DATA_F2_2_MASK 0x0001FFFFU

6559

#define LPDDR4__DENALI_PI_394__PI_MR2_DATA_F2_2_SHIFT 0U

6560

#define LPDDR4__DENALI_PI_394__PI_MR2_DATA_F2_2_WIDTH 17U

6561

#define LPDDR4__PI_MR2_DATA_F2_2__REG DENALI_PI_394

6562

#define LPDDR4__PI_MR2_DATA_F2_2__FLD LPDDR4__DENALI_PI_394__PI_MR2_DATA_F2_2

6563

6564

#define LPDDR4__DENALI_PI_395_READ_MASK 0x0001FFFFU

6565

#define LPDDR4__DENALI_PI_395_WRITE_MASK 0x0001FFFFU

6566

#define LPDDR4__DENALI_PI_395__PI_MR3_DATA_F2_2_MASK 0x0001FFFFU

6567

#define LPDDR4__DENALI_PI_395__PI_MR3_DATA_F2_2_SHIFT 0U

6568

#define LPDDR4__DENALI_PI_395__PI_MR3_DATA_F2_2_WIDTH 17U

6569

#define LPDDR4__PI_MR3_DATA_F2_2__REG DENALI_PI_395

6570

#define LPDDR4__PI_MR3_DATA_F2_2__FLD LPDDR4__DENALI_PI_395__PI_MR3_DATA_F2_2

6571

6572

#define LPDDR4__DENALI_PI_396_READ_MASK 0x0001FFFFU

6573

#define LPDDR4__DENALI_PI_396_WRITE_MASK 0x0001FFFFU

6574

#define LPDDR4__DENALI_PI_396__PI_MR4_DATA_F2_2_MASK 0x0001FFFFU

6575

#define LPDDR4__DENALI_PI_396__PI_MR4_DATA_F2_2_SHIFT 0U

6576

#define LPDDR4__DENALI_PI_396__PI_MR4_DATA_F2_2_WIDTH 17U

6577

#define LPDDR4__PI_MR4_DATA_F2_2__REG DENALI_PI_396

6578

#define LPDDR4__PI_MR4_DATA_F2_2__FLD LPDDR4__DENALI_PI_396__PI_MR4_DATA_F2_2

6579

6580

#define LPDDR4__DENALI_PI_397_READ_MASK 0x0001FFFFU

6581

#define LPDDR4__DENALI_PI_397_WRITE_MASK 0x0001FFFFU

6582

#define LPDDR4__DENALI_PI_397__PI_MR5_DATA_F2_2_MASK 0x0001FFFFU

6583

#define LPDDR4__DENALI_PI_397__PI_MR5_DATA_F2_2_SHIFT 0U

6584

#define LPDDR4__DENALI_PI_397__PI_MR5_DATA_F2_2_WIDTH 17U

6585

#define LPDDR4__PI_MR5_DATA_F2_2__REG DENALI_PI_397

6586

#define LPDDR4__PI_MR5_DATA_F2_2__FLD LPDDR4__DENALI_PI_397__PI_MR5_DATA_F2_2

6587

6588

#define LPDDR4__DENALI_PI_398_READ_MASK 0xFF01FFFFU

6589

#define LPDDR4__DENALI_PI_398_WRITE_MASK 0xFF01FFFFU

6590

#define LPDDR4__DENALI_PI_398__PI_MR6_DATA_F2_2_MASK 0x0001FFFFU

6591

#define LPDDR4__DENALI_PI_398__PI_MR6_DATA_F2_2_SHIFT 0U

6592

#define LPDDR4__DENALI_PI_398__PI_MR6_DATA_F2_2_WIDTH 17U

6593

#define LPDDR4__PI_MR6_DATA_F2_2__REG DENALI_PI_398

6594

#define LPDDR4__PI_MR6_DATA_F2_2__FLD LPDDR4__DENALI_PI_398__PI_MR6_DATA_F2_2

6595

6596

#define LPDDR4__DENALI_PI_398__PI_MR11_DATA_F2_2_MASK 0xFF000000U

6597

#define LPDDR4__DENALI_PI_398__PI_MR11_DATA_F2_2_SHIFT 24U

6598

#define LPDDR4__DENALI_PI_398__PI_MR11_DATA_F2_2_WIDTH 8U

6599

#define LPDDR4__PI_MR11_DATA_F2_2__REG DENALI_PI_398

6600

#define LPDDR4__PI_MR11_DATA_F2_2__FLD LPDDR4__DENALI_PI_398__PI_MR11_DATA_F2_2

6601

6602

#define LPDDR4__DENALI_PI_399_READ_MASK 0xFFFFFFFFU

6603

#define LPDDR4__DENALI_PI_399_WRITE_MASK 0xFFFFFFFFU

6604

#define LPDDR4__DENALI_PI_399__PI_MR12_DATA_F2_2_MASK 0x000000FFU

6605

#define LPDDR4__DENALI_PI_399__PI_MR12_DATA_F2_2_SHIFT 0U

6606

#define LPDDR4__DENALI_PI_399__PI_MR12_DATA_F2_2_WIDTH 8U

6607

#define LPDDR4__PI_MR12_DATA_F2_2__REG DENALI_PI_399

6608

#define LPDDR4__PI_MR12_DATA_F2_2__FLD LPDDR4__DENALI_PI_399__PI_MR12_DATA_F2_2

6609

6610

#define LPDDR4__DENALI_PI_399__PI_MR14_DATA_F2_2_MASK 0x0000FF00U

6611

#define LPDDR4__DENALI_PI_399__PI_MR14_DATA_F2_2_SHIFT 8U

6612

#define LPDDR4__DENALI_PI_399__PI_MR14_DATA_F2_2_WIDTH 8U

6613

#define LPDDR4__PI_MR14_DATA_F2_2__REG DENALI_PI_399

6614

#define LPDDR4__PI_MR14_DATA_F2_2__FLD LPDDR4__DENALI_PI_399__PI_MR14_DATA_F2_2

6615

6616

#define LPDDR4__DENALI_PI_399__PI_MR22_DATA_F2_2_MASK 0x00FF0000U

6617

#define LPDDR4__DENALI_PI_399__PI_MR22_DATA_F2_2_SHIFT 16U

6618

#define LPDDR4__DENALI_PI_399__PI_MR22_DATA_F2_2_WIDTH 8U

6619

#define LPDDR4__PI_MR22_DATA_F2_2__REG DENALI_PI_399

6620

#define LPDDR4__PI_MR22_DATA_F2_2__FLD LPDDR4__DENALI_PI_399__PI_MR22_DATA_F2_2

6621

6622

#define LPDDR4__DENALI_PI_399__PI_MR23_DATA_F2_2_MASK 0xFF000000U

6623

#define LPDDR4__DENALI_PI_399__PI_MR23_DATA_F2_2_SHIFT 24U

6624

#define LPDDR4__DENALI_PI_399__PI_MR23_DATA_F2_2_WIDTH 8U

6625

#define LPDDR4__PI_MR23_DATA_F2_2__REG DENALI_PI_399

6626

#define LPDDR4__PI_MR23_DATA_F2_2__FLD LPDDR4__DENALI_PI_399__PI_MR23_DATA_F2_2

6627

6628

#define LPDDR4__DENALI_PI_400_READ_MASK 0x0001FFFFU

6629

#define LPDDR4__DENALI_PI_400_WRITE_MASK 0x0001FFFFU

6630

#define LPDDR4__DENALI_PI_400__PI_MR0_DATA_F0_3_MASK 0x0001FFFFU

6631

#define LPDDR4__DENALI_PI_400__PI_MR0_DATA_F0_3_SHIFT 0U

6632

#define LPDDR4__DENALI_PI_400__PI_MR0_DATA_F0_3_WIDTH 17U

6633

#define LPDDR4__PI_MR0_DATA_F0_3__REG DENALI_PI_400

6634

#define LPDDR4__PI_MR0_DATA_F0_3__FLD LPDDR4__DENALI_PI_400__PI_MR0_DATA_F0_3

6635

6636

#define LPDDR4__DENALI_PI_401_READ_MASK 0x0001FFFFU

6637

#define LPDDR4__DENALI_PI_401_WRITE_MASK 0x0001FFFFU

6638

#define LPDDR4__DENALI_PI_401__PI_MR1_DATA_F0_3_MASK 0x0001FFFFU

6639

#define LPDDR4__DENALI_PI_401__PI_MR1_DATA_F0_3_SHIFT 0U

6640

#define LPDDR4__DENALI_PI_401__PI_MR1_DATA_F0_3_WIDTH 17U

6641

#define LPDDR4__PI_MR1_DATA_F0_3__REG DENALI_PI_401

6642

#define LPDDR4__PI_MR1_DATA_F0_3__FLD LPDDR4__DENALI_PI_401__PI_MR1_DATA_F0_3

6643

6644

#define LPDDR4__DENALI_PI_402_READ_MASK 0x0001FFFFU

6645

#define LPDDR4__DENALI_PI_402_WRITE_MASK 0x0001FFFFU

6646

#define LPDDR4__DENALI_PI_402__PI_MR2_DATA_F0_3_MASK 0x0001FFFFU

6647

#define LPDDR4__DENALI_PI_402__PI_MR2_DATA_F0_3_SHIFT 0U

6648

#define LPDDR4__DENALI_PI_402__PI_MR2_DATA_F0_3_WIDTH 17U

6649

#define LPDDR4__PI_MR2_DATA_F0_3__REG DENALI_PI_402

6650

#define LPDDR4__PI_MR2_DATA_F0_3__FLD LPDDR4__DENALI_PI_402__PI_MR2_DATA_F0_3

6651

6652

#define LPDDR4__DENALI_PI_403_READ_MASK 0x0001FFFFU

6653

#define LPDDR4__DENALI_PI_403_WRITE_MASK 0x0001FFFFU

6654

#define LPDDR4__DENALI_PI_403__PI_MR3_DATA_F0_3_MASK 0x0001FFFFU

6655

#define LPDDR4__DENALI_PI_403__PI_MR3_DATA_F0_3_SHIFT 0U

6656

#define LPDDR4__DENALI_PI_403__PI_MR3_DATA_F0_3_WIDTH 17U

6657

#define LPDDR4__PI_MR3_DATA_F0_3__REG DENALI_PI_403

6658

#define LPDDR4__PI_MR3_DATA_F0_3__FLD LPDDR4__DENALI_PI_403__PI_MR3_DATA_F0_3

6659

6660

#define LPDDR4__DENALI_PI_404_READ_MASK 0x0001FFFFU

6661

#define LPDDR4__DENALI_PI_404_WRITE_MASK 0x0001FFFFU

6662

#define LPDDR4__DENALI_PI_404__PI_MR4_DATA_F0_3_MASK 0x0001FFFFU

6663

#define LPDDR4__DENALI_PI_404__PI_MR4_DATA_F0_3_SHIFT 0U

6664

#define LPDDR4__DENALI_PI_404__PI_MR4_DATA_F0_3_WIDTH 17U

6665

#define LPDDR4__PI_MR4_DATA_F0_3__REG DENALI_PI_404

6666

#define LPDDR4__PI_MR4_DATA_F0_3__FLD LPDDR4__DENALI_PI_404__PI_MR4_DATA_F0_3

6667

6668

#define LPDDR4__DENALI_PI_405_READ_MASK 0x0001FFFFU

6669

#define LPDDR4__DENALI_PI_405_WRITE_MASK 0x0001FFFFU

6670

#define LPDDR4__DENALI_PI_405__PI_MR5_DATA_F0_3_MASK 0x0001FFFFU

6671

#define LPDDR4__DENALI_PI_405__PI_MR5_DATA_F0_3_SHIFT 0U

6672

#define LPDDR4__DENALI_PI_405__PI_MR5_DATA_F0_3_WIDTH 17U

6673

#define LPDDR4__PI_MR5_DATA_F0_3__REG DENALI_PI_405

6674

#define LPDDR4__PI_MR5_DATA_F0_3__FLD LPDDR4__DENALI_PI_405__PI_MR5_DATA_F0_3

6675

6676

#define LPDDR4__DENALI_PI_406_READ_MASK 0xFF01FFFFU

6677

#define LPDDR4__DENALI_PI_406_WRITE_MASK 0xFF01FFFFU

6678

#define LPDDR4__DENALI_PI_406__PI_MR6_DATA_F0_3_MASK 0x0001FFFFU

6679

#define LPDDR4__DENALI_PI_406__PI_MR6_DATA_F0_3_SHIFT 0U

6680

#define LPDDR4__DENALI_PI_406__PI_MR6_DATA_F0_3_WIDTH 17U

6681

#define LPDDR4__PI_MR6_DATA_F0_3__REG DENALI_PI_406

6682

#define LPDDR4__PI_MR6_DATA_F0_3__FLD LPDDR4__DENALI_PI_406__PI_MR6_DATA_F0_3

6683

6684

#define LPDDR4__DENALI_PI_406__PI_MR11_DATA_F0_3_MASK 0xFF000000U

6685

#define LPDDR4__DENALI_PI_406__PI_MR11_DATA_F0_3_SHIFT 24U

6686

#define LPDDR4__DENALI_PI_406__PI_MR11_DATA_F0_3_WIDTH 8U

6687

#define LPDDR4__PI_MR11_DATA_F0_3__REG DENALI_PI_406

6688

#define LPDDR4__PI_MR11_DATA_F0_3__FLD LPDDR4__DENALI_PI_406__PI_MR11_DATA_F0_3

6689

6690

#define LPDDR4__DENALI_PI_407_READ_MASK 0xFFFFFFFFU

6691

#define LPDDR4__DENALI_PI_407_WRITE_MASK 0xFFFFFFFFU

6692

#define LPDDR4__DENALI_PI_407__PI_MR12_DATA_F0_3_MASK 0x000000FFU

6693

#define LPDDR4__DENALI_PI_407__PI_MR12_DATA_F0_3_SHIFT 0U

6694

#define LPDDR4__DENALI_PI_407__PI_MR12_DATA_F0_3_WIDTH 8U

6695

#define LPDDR4__PI_MR12_DATA_F0_3__REG DENALI_PI_407

6696

#define LPDDR4__PI_MR12_DATA_F0_3__FLD LPDDR4__DENALI_PI_407__PI_MR12_DATA_F0_3

6697

6698

#define LPDDR4__DENALI_PI_407__PI_MR14_DATA_F0_3_MASK 0x0000FF00U

6699

#define LPDDR4__DENALI_PI_407__PI_MR14_DATA_F0_3_SHIFT 8U

6700

#define LPDDR4__DENALI_PI_407__PI_MR14_DATA_F0_3_WIDTH 8U

6701

#define LPDDR4__PI_MR14_DATA_F0_3__REG DENALI_PI_407

6702

#define LPDDR4__PI_MR14_DATA_F0_3__FLD LPDDR4__DENALI_PI_407__PI_MR14_DATA_F0_3

6703

6704

#define LPDDR4__DENALI_PI_407__PI_MR22_DATA_F0_3_MASK 0x00FF0000U

6705

#define LPDDR4__DENALI_PI_407__PI_MR22_DATA_F0_3_SHIFT 16U

6706

#define LPDDR4__DENALI_PI_407__PI_MR22_DATA_F0_3_WIDTH 8U

6707

#define LPDDR4__PI_MR22_DATA_F0_3__REG DENALI_PI_407

6708

#define LPDDR4__PI_MR22_DATA_F0_3__FLD LPDDR4__DENALI_PI_407__PI_MR22_DATA_F0_3

6709

6710

#define LPDDR4__DENALI_PI_407__PI_MR23_DATA_F0_3_MASK 0xFF000000U

6711

#define LPDDR4__DENALI_PI_407__PI_MR23_DATA_F0_3_SHIFT 24U

6712

#define LPDDR4__DENALI_PI_407__PI_MR23_DATA_F0_3_WIDTH 8U

6713

#define LPDDR4__PI_MR23_DATA_F0_3__REG DENALI_PI_407

6714

#define LPDDR4__PI_MR23_DATA_F0_3__FLD LPDDR4__DENALI_PI_407__PI_MR23_DATA_F0_3

6715

6716

#define LPDDR4__DENALI_PI_408_READ_MASK 0x0001FFFFU

6717

#define LPDDR4__DENALI_PI_408_WRITE_MASK 0x0001FFFFU

6718

#define LPDDR4__DENALI_PI_408__PI_MR0_DATA_F1_3_MASK 0x0001FFFFU

6719

#define LPDDR4__DENALI_PI_408__PI_MR0_DATA_F1_3_SHIFT 0U

6720

#define LPDDR4__DENALI_PI_408__PI_MR0_DATA_F1_3_WIDTH 17U

6721

#define LPDDR4__PI_MR0_DATA_F1_3__REG DENALI_PI_408

6722

#define LPDDR4__PI_MR0_DATA_F1_3__FLD LPDDR4__DENALI_PI_408__PI_MR0_DATA_F1_3

6723

6724

#define LPDDR4__DENALI_PI_409_READ_MASK 0x0001FFFFU

6725

#define LPDDR4__DENALI_PI_409_WRITE_MASK 0x0001FFFFU

6726

#define LPDDR4__DENALI_PI_409__PI_MR1_DATA_F1_3_MASK 0x0001FFFFU

6727

#define LPDDR4__DENALI_PI_409__PI_MR1_DATA_F1_3_SHIFT 0U

6728

#define LPDDR4__DENALI_PI_409__PI_MR1_DATA_F1_3_WIDTH 17U

6729

#define LPDDR4__PI_MR1_DATA_F1_3__REG DENALI_PI_409

6730

#define LPDDR4__PI_MR1_DATA_F1_3__FLD LPDDR4__DENALI_PI_409__PI_MR1_DATA_F1_3

6731

6732

#define LPDDR4__DENALI_PI_410_READ_MASK 0x0001FFFFU

6733

#define LPDDR4__DENALI_PI_410_WRITE_MASK 0x0001FFFFU

6734

#define LPDDR4__DENALI_PI_410__PI_MR2_DATA_F1_3_MASK 0x0001FFFFU

6735

#define LPDDR4__DENALI_PI_410__PI_MR2_DATA_F1_3_SHIFT 0U

6736

#define LPDDR4__DENALI_PI_410__PI_MR2_DATA_F1_3_WIDTH 17U

6737

#define LPDDR4__PI_MR2_DATA_F1_3__REG DENALI_PI_410

6738

#define LPDDR4__PI_MR2_DATA_F1_3__FLD LPDDR4__DENALI_PI_410__PI_MR2_DATA_F1_3

6739

6740

#define LPDDR4__DENALI_PI_411_READ_MASK 0x0001FFFFU

6741

#define LPDDR4__DENALI_PI_411_WRITE_MASK 0x0001FFFFU

6742

#define LPDDR4__DENALI_PI_411__PI_MR3_DATA_F1_3_MASK 0x0001FFFFU

6743

#define LPDDR4__DENALI_PI_411__PI_MR3_DATA_F1_3_SHIFT 0U

6744

#define LPDDR4__DENALI_PI_411__PI_MR3_DATA_F1_3_WIDTH 17U

6745

#define LPDDR4__PI_MR3_DATA_F1_3__REG DENALI_PI_411

6746

#define LPDDR4__PI_MR3_DATA_F1_3__FLD LPDDR4__DENALI_PI_411__PI_MR3_DATA_F1_3

6747

6748

#define LPDDR4__DENALI_PI_412_READ_MASK 0x0001FFFFU

6749

#define LPDDR4__DENALI_PI_412_WRITE_MASK 0x0001FFFFU

6750

#define LPDDR4__DENALI_PI_412__PI_MR4_DATA_F1_3_MASK 0x0001FFFFU

6751

#define LPDDR4__DENALI_PI_412__PI_MR4_DATA_F1_3_SHIFT 0U

6752

#define LPDDR4__DENALI_PI_412__PI_MR4_DATA_F1_3_WIDTH 17U

6753

#define LPDDR4__PI_MR4_DATA_F1_3__REG DENALI_PI_412

6754

#define LPDDR4__PI_MR4_DATA_F1_3__FLD LPDDR4__DENALI_PI_412__PI_MR4_DATA_F1_3

6755

6756

#define LPDDR4__DENALI_PI_413_READ_MASK 0x0001FFFFU

6757

#define LPDDR4__DENALI_PI_413_WRITE_MASK 0x0001FFFFU

6758

#define LPDDR4__DENALI_PI_413__PI_MR5_DATA_F1_3_MASK 0x0001FFFFU

6759

#define LPDDR4__DENALI_PI_413__PI_MR5_DATA_F1_3_SHIFT 0U

6760

#define LPDDR4__DENALI_PI_413__PI_MR5_DATA_F1_3_WIDTH 17U

6761

#define LPDDR4__PI_MR5_DATA_F1_3__REG DENALI_PI_413

6762

#define LPDDR4__PI_MR5_DATA_F1_3__FLD LPDDR4__DENALI_PI_413__PI_MR5_DATA_F1_3

6763

6764

#define LPDDR4__DENALI_PI_414_READ_MASK 0xFF01FFFFU

6765

#define LPDDR4__DENALI_PI_414_WRITE_MASK 0xFF01FFFFU

6766

#define LPDDR4__DENALI_PI_414__PI_MR6_DATA_F1_3_MASK 0x0001FFFFU

6767

#define LPDDR4__DENALI_PI_414__PI_MR6_DATA_F1_3_SHIFT 0U

6768

#define LPDDR4__DENALI_PI_414__PI_MR6_DATA_F1_3_WIDTH 17U

6769

#define LPDDR4__PI_MR6_DATA_F1_3__REG DENALI_PI_414

6770

#define LPDDR4__PI_MR6_DATA_F1_3__FLD LPDDR4__DENALI_PI_414__PI_MR6_DATA_F1_3

6771

6772

#define LPDDR4__DENALI_PI_414__PI_MR11_DATA_F1_3_MASK 0xFF000000U

6773

#define LPDDR4__DENALI_PI_414__PI_MR11_DATA_F1_3_SHIFT 24U

6774

#define LPDDR4__DENALI_PI_414__PI_MR11_DATA_F1_3_WIDTH 8U

6775

#define LPDDR4__PI_MR11_DATA_F1_3__REG DENALI_PI_414

6776

#define LPDDR4__PI_MR11_DATA_F1_3__FLD LPDDR4__DENALI_PI_414__PI_MR11_DATA_F1_3

6777

6778

#define LPDDR4__DENALI_PI_415_READ_MASK 0xFFFFFFFFU

6779

#define LPDDR4__DENALI_PI_415_WRITE_MASK 0xFFFFFFFFU

6780

#define LPDDR4__DENALI_PI_415__PI_MR12_DATA_F1_3_MASK 0x000000FFU

6781

#define LPDDR4__DENALI_PI_415__PI_MR12_DATA_F1_3_SHIFT 0U

6782

#define LPDDR4__DENALI_PI_415__PI_MR12_DATA_F1_3_WIDTH 8U

6783

#define LPDDR4__PI_MR12_DATA_F1_3__REG DENALI_PI_415

6784

#define LPDDR4__PI_MR12_DATA_F1_3__FLD LPDDR4__DENALI_PI_415__PI_MR12_DATA_F1_3

6785

6786

#define LPDDR4__DENALI_PI_415__PI_MR14_DATA_F1_3_MASK 0x0000FF00U

6787

#define LPDDR4__DENALI_PI_415__PI_MR14_DATA_F1_3_SHIFT 8U

6788

#define LPDDR4__DENALI_PI_415__PI_MR14_DATA_F1_3_WIDTH 8U

6789

#define LPDDR4__PI_MR14_DATA_F1_3__REG DENALI_PI_415

6790

#define LPDDR4__PI_MR14_DATA_F1_3__FLD LPDDR4__DENALI_PI_415__PI_MR14_DATA_F1_3

6791

6792

#define LPDDR4__DENALI_PI_415__PI_MR22_DATA_F1_3_MASK 0x00FF0000U

6793

#define LPDDR4__DENALI_PI_415__PI_MR22_DATA_F1_3_SHIFT 16U

6794

#define LPDDR4__DENALI_PI_415__PI_MR22_DATA_F1_3_WIDTH 8U

6795

#define LPDDR4__PI_MR22_DATA_F1_3__REG DENALI_PI_415

6796

#define LPDDR4__PI_MR22_DATA_F1_3__FLD LPDDR4__DENALI_PI_415__PI_MR22_DATA_F1_3

6797

6798

#define LPDDR4__DENALI_PI_415__PI_MR23_DATA_F1_3_MASK 0xFF000000U

6799

#define LPDDR4__DENALI_PI_415__PI_MR23_DATA_F1_3_SHIFT 24U

6800

#define LPDDR4__DENALI_PI_415__PI_MR23_DATA_F1_3_WIDTH 8U

6801

#define LPDDR4__PI_MR23_DATA_F1_3__REG DENALI_PI_415

6802

#define LPDDR4__PI_MR23_DATA_F1_3__FLD LPDDR4__DENALI_PI_415__PI_MR23_DATA_F1_3

6803

6804

#define LPDDR4__DENALI_PI_416_READ_MASK 0x0001FFFFU

6805

#define LPDDR4__DENALI_PI_416_WRITE_MASK 0x0001FFFFU

6806

#define LPDDR4__DENALI_PI_416__PI_MR0_DATA_F2_3_MASK 0x0001FFFFU

6807

#define LPDDR4__DENALI_PI_416__PI_MR0_DATA_F2_3_SHIFT 0U

6808

#define LPDDR4__DENALI_PI_416__PI_MR0_DATA_F2_3_WIDTH 17U

6809

#define LPDDR4__PI_MR0_DATA_F2_3__REG DENALI_PI_416

6810

#define LPDDR4__PI_MR0_DATA_F2_3__FLD LPDDR4__DENALI_PI_416__PI_MR0_DATA_F2_3

6811

6812

#define LPDDR4__DENALI_PI_417_READ_MASK 0x0001FFFFU

6813

#define LPDDR4__DENALI_PI_417_WRITE_MASK 0x0001FFFFU

6814

#define LPDDR4__DENALI_PI_417__PI_MR1_DATA_F2_3_MASK 0x0001FFFFU

6815

#define LPDDR4__DENALI_PI_417__PI_MR1_DATA_F2_3_SHIFT 0U

6816

#define LPDDR4__DENALI_PI_417__PI_MR1_DATA_F2_3_WIDTH 17U

6817

#define LPDDR4__PI_MR1_DATA_F2_3__REG DENALI_PI_417

6818

#define LPDDR4__PI_MR1_DATA_F2_3__FLD LPDDR4__DENALI_PI_417__PI_MR1_DATA_F2_3

6819

6820

#define LPDDR4__DENALI_PI_418_READ_MASK 0x0001FFFFU

6821

#define LPDDR4__DENALI_PI_418_WRITE_MASK 0x0001FFFFU

6822

#define LPDDR4__DENALI_PI_418__PI_MR2_DATA_F2_3_MASK 0x0001FFFFU

6823

#define LPDDR4__DENALI_PI_418__PI_MR2_DATA_F2_3_SHIFT 0U

6824

#define LPDDR4__DENALI_PI_418__PI_MR2_DATA_F2_3_WIDTH 17U

6825

#define LPDDR4__PI_MR2_DATA_F2_3__REG DENALI_PI_418

6826

#define LPDDR4__PI_MR2_DATA_F2_3__FLD LPDDR4__DENALI_PI_418__PI_MR2_DATA_F2_3

6827

6828

#define LPDDR4__DENALI_PI_419_READ_MASK 0x0001FFFFU

6829

#define LPDDR4__DENALI_PI_419_WRITE_MASK 0x0001FFFFU

6830

#define LPDDR4__DENALI_PI_419__PI_MR3_DATA_F2_3_MASK 0x0001FFFFU

6831

#define LPDDR4__DENALI_PI_419__PI_MR3_DATA_F2_3_SHIFT 0U

6832

#define LPDDR4__DENALI_PI_419__PI_MR3_DATA_F2_3_WIDTH 17U

6833

#define LPDDR4__PI_MR3_DATA_F2_3__REG DENALI_PI_419

6834

#define LPDDR4__PI_MR3_DATA_F2_3__FLD LPDDR4__DENALI_PI_419__PI_MR3_DATA_F2_3

6835

6836

#define LPDDR4__DENALI_PI_420_READ_MASK 0x0001FFFFU

6837

#define LPDDR4__DENALI_PI_420_WRITE_MASK 0x0001FFFFU

6838

#define LPDDR4__DENALI_PI_420__PI_MR4_DATA_F2_3_MASK 0x0001FFFFU

6839

#define LPDDR4__DENALI_PI_420__PI_MR4_DATA_F2_3_SHIFT 0U

6840

#define LPDDR4__DENALI_PI_420__PI_MR4_DATA_F2_3_WIDTH 17U

6841

#define LPDDR4__PI_MR4_DATA_F2_3__REG DENALI_PI_420

6842

#define LPDDR4__PI_MR4_DATA_F2_3__FLD LPDDR4__DENALI_PI_420__PI_MR4_DATA_F2_3

6843

6844

#define LPDDR4__DENALI_PI_421_READ_MASK 0x0001FFFFU

6845

#define LPDDR4__DENALI_PI_421_WRITE_MASK 0x0001FFFFU

6846

#define LPDDR4__DENALI_PI_421__PI_MR5_DATA_F2_3_MASK 0x0001FFFFU

6847

#define LPDDR4__DENALI_PI_421__PI_MR5_DATA_F2_3_SHIFT 0U

6848

#define LPDDR4__DENALI_PI_421__PI_MR5_DATA_F2_3_WIDTH 17U

6849

#define LPDDR4__PI_MR5_DATA_F2_3__REG DENALI_PI_421

6850

#define LPDDR4__PI_MR5_DATA_F2_3__FLD LPDDR4__DENALI_PI_421__PI_MR5_DATA_F2_3

6851

6852

#define LPDDR4__DENALI_PI_422_READ_MASK 0xFF01FFFFU

6853

#define LPDDR4__DENALI_PI_422_WRITE_MASK 0xFF01FFFFU

6854

#define LPDDR4__DENALI_PI_422__PI_MR6_DATA_F2_3_MASK 0x0001FFFFU

6855

#define LPDDR4__DENALI_PI_422__PI_MR6_DATA_F2_3_SHIFT 0U

6856

#define LPDDR4__DENALI_PI_422__PI_MR6_DATA_F2_3_WIDTH 17U

6857

#define LPDDR4__PI_MR6_DATA_F2_3__REG DENALI_PI_422

6858

#define LPDDR4__PI_MR6_DATA_F2_3__FLD LPDDR4__DENALI_PI_422__PI_MR6_DATA_F2_3

6859

6860

#define LPDDR4__DENALI_PI_422__PI_MR11_DATA_F2_3_MASK 0xFF000000U

6861

#define LPDDR4__DENALI_PI_422__PI_MR11_DATA_F2_3_SHIFT 24U

6862

#define LPDDR4__DENALI_PI_422__PI_MR11_DATA_F2_3_WIDTH 8U

6863

#define LPDDR4__PI_MR11_DATA_F2_3__REG DENALI_PI_422

6864

#define LPDDR4__PI_MR11_DATA_F2_3__FLD LPDDR4__DENALI_PI_422__PI_MR11_DATA_F2_3

6865

6866

#define LPDDR4__DENALI_PI_423_READ_MASK 0xFFFFFFFFU

6867

#define LPDDR4__DENALI_PI_423_WRITE_MASK 0xFFFFFFFFU

6868

#define LPDDR4__DENALI_PI_423__PI_MR12_DATA_F2_3_MASK 0x000000FFU

6869

#define LPDDR4__DENALI_PI_423__PI_MR12_DATA_F2_3_SHIFT 0U

6870

#define LPDDR4__DENALI_PI_423__PI_MR12_DATA_F2_3_WIDTH 8U

6871

#define LPDDR4__PI_MR12_DATA_F2_3__REG DENALI_PI_423

6872

#define LPDDR4__PI_MR12_DATA_F2_3__FLD LPDDR4__DENALI_PI_423__PI_MR12_DATA_F2_3

6873

6874

#define LPDDR4__DENALI_PI_423__PI_MR14_DATA_F2_3_MASK 0x0000FF00U

6875

#define LPDDR4__DENALI_PI_423__PI_MR14_DATA_F2_3_SHIFT 8U

6876

#define LPDDR4__DENALI_PI_423__PI_MR14_DATA_F2_3_WIDTH 8U

6877

#define LPDDR4__PI_MR14_DATA_F2_3__REG DENALI_PI_423

6878

#define LPDDR4__PI_MR14_DATA_F2_3__FLD LPDDR4__DENALI_PI_423__PI_MR14_DATA_F2_3

6879

6880

#define LPDDR4__DENALI_PI_423__PI_MR22_DATA_F2_3_MASK 0x00FF0000U

6881

#define LPDDR4__DENALI_PI_423__PI_MR22_DATA_F2_3_SHIFT 16U

6882

#define LPDDR4__DENALI_PI_423__PI_MR22_DATA_F2_3_WIDTH 8U

6883

#define LPDDR4__PI_MR22_DATA_F2_3__REG DENALI_PI_423

6884

#define LPDDR4__PI_MR22_DATA_F2_3__FLD LPDDR4__DENALI_PI_423__PI_MR22_DATA_F2_3

6885

6886

#define LPDDR4__DENALI_PI_423__PI_MR23_DATA_F2_3_MASK 0xFF000000U

6887

#define LPDDR4__DENALI_PI_423__PI_MR23_DATA_F2_3_SHIFT 24U

6888

#define LPDDR4__DENALI_PI_423__PI_MR23_DATA_F2_3_WIDTH 8U

6889

#define LPDDR4__PI_MR23_DATA_F2_3__REG DENALI_PI_423

6890

#define LPDDR4__PI_MR23_DATA_F2_3__FLD LPDDR4__DENALI_PI_423__PI_MR23_DATA_F2_3

6891

6892

#endif /* REG_LPDDR4_PI_MACROS_H_ */