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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
TsiChung Liewb354aef2009-06-12 11:29:00 +00002/*
3 * Configuation settings for the Freescale MCF5208EVBe.
4 *
5 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
TsiChung Liewb354aef2009-06-12 11:29:00 +00007 */
8
9#ifndef _M5208EVBE_H
10#define _M5208EVBE_H
11
12/*
13 * High Level Configuration Options
14 * (easy to change)
15 */
Tom Rini6a5dccc2022-11-16 13:10:41 -050016#define CFG_SYS_UART_PORT (0)
TsiChung Liewb354aef2009-06-12 11:29:00 +000017
TsiChung Liewb354aef2009-06-12 11:29:00 +000018#define CONFIG_WATCHDOG_TIMEOUT 5000
19
TsiChung Liewb354aef2009-06-12 11:29:00 +000020/* I2C */
TsiChung Liewb354aef2009-06-12 11:29:00 +000021
TsiChung Liewb354aef2009-06-12 11:29:00 +000022#ifdef CONFIG_MCFFEC
TsiChung Liewb354aef2009-06-12 11:29:00 +000023# define CONFIG_IPADDR 192.162.1.2
24# define CONFIG_NETMASK 255.255.255.0
25# define CONFIG_SERVERIP 192.162.1.1
26# define CONFIG_GATEWAYIP 192.162.1.1
TsiChung Liewb354aef2009-06-12 11:29:00 +000027#endif /* CONFIG_MCFFEC */
28
Mario Six790d8442018-03-28 14:38:20 +020029#define CONFIG_HOSTNAME "M5208EVBe"
TsiChung Liewb354aef2009-06-12 11:29:00 +000030#define CONFIG_EXTRA_ENV_SETTINGS \
31 "netdev=eth0\0" \
32 "loadaddr=40010000\0" \
33 "u-boot=u-boot.bin\0" \
34 "load=tftp ${loadaddr) ${u-boot}\0" \
35 "upd=run load; run prog\0" \
36 "prog=prot off 0 3ffff;" \
37 "era 0 3ffff;" \
38 "cp.b ${loadaddr} 0 ${filesize};" \
39 "save\0" \
40 ""
41
42#define CONFIG_PRAM 512 /* 512 KB */
TsiChung Liewb354aef2009-06-12 11:29:00 +000043
Tom Rini6a5dccc2022-11-16 13:10:41 -050044#define CFG_SYS_CLK 166666666 /* CPU Core Clock */
45#define CFG_SYS_PLL_ODR 0x36
46#define CFG_SYS_PLL_FDR 0x7D
TsiChung Liewb354aef2009-06-12 11:29:00 +000047
Tom Rini6a5dccc2022-11-16 13:10:41 -050048#define CFG_SYS_MBAR 0xFC000000
TsiChung Liewb354aef2009-06-12 11:29:00 +000049
50/*
51 * Low Level Configuration Settings
52 * (address mappings, register initial values, etc.)
53 * You should know what you are doing if you make changes here.
54 */
55/* Definitions for initial stack pointer and data area (in DPRAM) */
Tom Rini6a5dccc2022-11-16 13:10:41 -050056#define CFG_SYS_INIT_RAM_ADDR 0x80000000
57#define CFG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */
58#define CFG_SYS_INIT_RAM_CTRL 0x221
TsiChung Liewb354aef2009-06-12 11:29:00 +000059
60/*
61 * Start addresses for the final memory configuration
62 * (Set up by the startup code)
Tom Rinibb4dd962022-11-16 13:10:37 -050063 * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
TsiChung Liewb354aef2009-06-12 11:29:00 +000064 */
Tom Rinibb4dd962022-11-16 13:10:37 -050065#define CFG_SYS_SDRAM_BASE 0x40000000
66#define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
67#define CFG_SYS_SDRAM_CFG1 0x43711630
68#define CFG_SYS_SDRAM_CFG2 0x56670000
69#define CFG_SYS_SDRAM_CTRL 0xE1002000
70#define CFG_SYS_SDRAM_EMOD 0x80010000
71#define CFG_SYS_SDRAM_MODE 0x00CD0000
TsiChung Liewb354aef2009-06-12 11:29:00 +000072
TsiChung Liewb354aef2009-06-12 11:29:00 +000073/*
74 * For booting Linux, the board info and command line data
75 * have to be in the first 8 MB of memory, since this is
76 * the maximum mapped by the Linux kernel during initialization ??
77 */
Tom Rini6a5dccc2022-11-16 13:10:41 -050078#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
TsiChung Liewb354aef2009-06-12 11:29:00 +000079
80/* FLASH organization */
TsiChung Liewb354aef2009-06-12 11:29:00 +000081#ifdef CONFIG_SYS_FLASH_CFI
Tom Rini6a5dccc2022-11-16 13:10:41 -050082# define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
TsiChung Liewb354aef2009-06-12 11:29:00 +000083#endif
84
Tom Rini6a5dccc2022-11-16 13:10:41 -050085#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE
TsiChung Liewb354aef2009-06-12 11:29:00 +000086
87/*
88 * Configuration for environment
89 * Environment is embedded in u-boot in the second sector of the flash
90 */
TsiChung Liewb354aef2009-06-12 11:29:00 +000091
angelo@sysam.it6312a952015-03-29 22:54:16 +020092#define LDS_BOARD_TEXT \
Simon Glass547cb402017-08-03 12:21:49 -060093 . = DEFINED(env_offset) ? env_offset : .; \
94 env/embedded.o(.text*);
angelo@sysam.it6312a952015-03-29 22:54:16 +020095
TsiChung Liewb354aef2009-06-12 11:29:00 +000096/* Cache Configuration */
TsiChung Liewb354aef2009-06-12 11:29:00 +000097
Tom Rini6a5dccc2022-11-16 13:10:41 -050098#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
99 CFG_SYS_INIT_RAM_SIZE - 8)
100#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
101 CFG_SYS_INIT_RAM_SIZE - 4)
102#define CFG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
103#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
Tom Rinibb4dd962022-11-16 13:10:37 -0500104 CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600105 CF_ACR_EN | CF_ACR_SM_ALL)
Tom Rini6a5dccc2022-11-16 13:10:41 -0500106#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600107 CF_CACR_DISD | CF_CACR_INVI | \
108 CF_CACR_CEIB | CF_CACR_DCM | \
109 CF_CACR_EUSP)
110
TsiChung Liewb354aef2009-06-12 11:29:00 +0000111/* Chipselect bank definitions */
112/*
113 * CS0 - NOR Flash
114 * CS1 - Available
115 * CS2 - Available
116 * CS3 - Available
117 * CS4 - Available
118 * CS5 - Available
119 */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500120#define CFG_SYS_CS0_BASE 0
121#define CFG_SYS_CS0_MASK 0x007F0001
122#define CFG_SYS_CS0_CTRL 0x00001FA0
TsiChung Liewb354aef2009-06-12 11:29:00 +0000123
124#endif /* _M5208EVBE_H */