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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0 */
Paul Burtonf5de32a2016-09-08 07:47:39 +01002/*
3 * Copyright (C) 2016 Imagination Technologies
Paul Burtonf5de32a2016-09-08 07:47:39 +01004 */
5
6#ifndef __CONFIGS_BOSTON_H__
7#define __CONFIGS_BOSTON_H__
8
9/*
Paul Burtonfc9d3bf2017-04-30 21:22:43 +020010 * General board configuration
11 */
12#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024)
13
14/*
Paul Burtonf5de32a2016-09-08 07:47:39 +010015 * CPU
16 */
17#define CONFIG_SYS_MIPS_TIMER_FREQ 30000000
18
19/*
20 * PCI
21 */
Paul Burtonf5de32a2016-09-08 07:47:39 +010022
23/*
24 * Memory map
25 */
26#ifdef CONFIG_64BIT
27# define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000
28#else
29# define CONFIG_SYS_SDRAM_BASE 0x80000000
30#endif
31
32#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
33
34#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
35
Paul Burton6f9e8d22017-11-21 12:35:31 -080036#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x08000000)
Paul Burtonf5de32a2016-09-08 07:47:39 +010037
38#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0)
39#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x10000000)
40
41#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
42
43/*
44 * Console
45 */
Paul Burtonf5de32a2016-09-08 07:47:39 +010046
47/*
48 * Flash
49 */
Paul Burtonf5de32a2016-09-08 07:47:39 +010050#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
51#define CONFIG_SYS_MAX_FLASH_SECT 1024
52
53/*
54 * Environment
55 */
Paul Burtonf5de32a2016-09-08 07:47:39 +010056
57#endif /* __CONFIGS_BOSTON_H__ */