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git01.mediatek.com / filogic / uboot / c42ad3009d1d7048651314a03980abd61dd8df19 / . / arch / sandbox / dts / test.dts
blob: fff175d1b7a2da54a1d636b02c51a36571e55275 [file] [log] [blame]
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]1/dts-v1/;
2
3/ {
4 model = "sandbox";
5 compatible = "sandbox";
6 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]7 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]8
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]9 aliases {
10 console = &uart0;
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]11 eth0 = "/eth@10002000";
Bin Meng04a11cb2015-08-27 22:25:53 -0700[diff] [blame]12 eth3 = &eth_3;
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]13 eth5 = &eth_5;
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]14 i2c0 = "/i2c@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +0200[diff] [blame]15 pci0 = &pci;
Nishanth Menonedf85812015-09-17 15:42:41 -0500[diff] [blame]16 remoteproc1 = &rproc_1;
17 remoteproc2 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -0600[diff] [blame]18 rtc0 = &rtc_0;
19 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]20 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +0200[diff] [blame]21 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]22 testbus3 = "/some-bus";
23 testfdt0 = "/some-bus/c-test@0";
24 testfdt1 = "/some-bus/c-test@1";
25 testfdt3 = "/b-test";
26 testfdt5 = "/some-bus/c-test@5";
27 testfdt8 = "/a-test";
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]28 usb0 = &usb_0;
29 usb1 = &usb_1;
30 usb2 = &usb_2;
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]31 };
32
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]33 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]34 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]35 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]36 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]37 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]38 u-boot,dm-pre-reloc;
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]39 test-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 5 0 3 2 1>,
40 <0>, <&gpio_a 12>;
41 test2-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 6 1 3 2 1>,
42 <&gpio_b 7 2 3 2 1>, <&gpio_b 8 4 3 2 1>,
43 <&gpio_b 9 0xc 3 2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]44 };
45
46 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]47 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]48 compatible = "not,compatible";
49 };
50
51 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]52 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]53 };
54
55 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]56 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]57 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]58 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]59 ping-add = <3>;
60 };
61
62 some-bus {
63 #address-cells = <1>;
64 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]65 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]66 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]67 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]68 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]69 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]70 compatible = "denx,u-boot-fdt-test";
71 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]72 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]73 ping-add = <5>;
74 };
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]75 c-test@0 {
76 compatible = "denx,u-boot-fdt-test";
77 reg = <0>;
78 ping-expect = <6>;
79 ping-add = <6>;
80 };
81 c-test@1 {
82 compatible = "denx,u-boot-fdt-test";
83 reg = <1>;
84 ping-expect = <7>;
85 ping-add = <7>;
86 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]87 };
88
89 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]90 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600[diff] [blame]91 ping-expect = <6>;
92 ping-add = <6>;
93 compatible = "google,another-fdt-test";
94 };
95
96 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]97 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]98 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]99 ping-add = <6>;
100 compatible = "google,another-fdt-test";
101 };
102
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]103 f-test {
104 compatible = "denx,u-boot-fdt-test";
105 };
106
107 g-test {
108 compatible = "denx,u-boot-fdt-test";
109 };
110
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]111 clk_fixed: clk-fixed {
112 compatible = "fixed-clock";
113 #clock-cells = <0>;
114 clock-frequency = <1234>;
115 };
116
117 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]118 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]119 #clock-cells = <1>;
120 };
121
122 clk-test {
123 compatible = "sandbox,clk-test";
124 clocks = <&clk_fixed>,
125 <&clk_sandbox 1>,
126 <&clk_sandbox 0>;
127 clock-names = "fixed", "i2c", "spi";
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]128 };
129
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]130 eth@10002000 {
131 compatible = "sandbox,eth";
132 reg = <0x10002000 0x1000>;
133 fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x00>;
134 };
135
136 eth_5: eth@10003000 {
137 compatible = "sandbox,eth";
138 reg = <0x10003000 0x1000>;
139 fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x11>;
140 };
141
Bin Meng04a11cb2015-08-27 22:25:53 -0700[diff] [blame]142 eth_3: sbe5 {
143 compatible = "sandbox,eth";
144 reg = <0x10005000 0x1000>;
145 fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x33>;
146 };
147
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]148 eth@10004000 {
149 compatible = "sandbox,eth";
150 reg = <0x10004000 0x1000>;
151 fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x22>;
152 };
153
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]154 gpio_a: base-gpios {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]155 compatible = "sandbox,gpio";
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]156 gpio-controller;
157 #gpio-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]158 gpio-bank-name = "a";
159 num-gpios = <20>;
160 };
161
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]162 gpio_b: extra-gpios {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]163 compatible = "sandbox,gpio";
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]164 gpio-controller;
165 #gpio-cells = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]166 gpio-bank-name = "b";
167 num-gpios = <10>;
168 };
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]169
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]170 i2c@0 {
171 #address-cells = <1>;
172 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]173 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]174 compatible = "sandbox,i2c";
175 clock-frequency = <100000>;
176 eeprom@2c {
177 reg = <0x2c>;
178 compatible = "i2c-eeprom";
179 emul {
180 compatible = "sandbox,i2c-eeprom";
181 sandbox,filename = "i2c.bin";
182 sandbox,size = <256>;
183 };
184 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]185
Simon Glass336b2952015-05-22 15:42:17 -0600[diff] [blame]186 rtc_0: rtc@43 {
187 reg = <0x43>;
188 compatible = "sandbox-rtc";
189 emul {
190 compatible = "sandbox,i2c-rtc";
191 };
192 };
193
194 rtc_1: rtc@61 {
195 reg = <0x61>;
196 compatible = "sandbox-rtc";
197 emul {
198 compatible = "sandbox,i2c-rtc";
199 };
200 };
201
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]202 sandbox_pmic: sandbox_pmic {
203 reg = <0x40>;
204 };
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]205 };
206
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100[diff] [blame]207 adc@0 {
208 compatible = "sandbox,adc";
209 vdd-supply = <&buck2>;
210 vss-microvolts = <0>;
211 };
212
Simon Glass90b6fef2016-01-18 19:52:26 -0700[diff] [blame]213 lcd {
214 u-boot,dm-pre-reloc;
215 compatible = "sandbox,lcd-sdl";
216 xres = <1366>;
217 yres = <768>;
218 };
219
Simon Glassd783eb32015-07-06 12:54:34 -0600[diff] [blame]220 leds {
221 compatible = "gpio-leds";
222
223 iracibble {
224 gpios = <&gpio_a 1 0>;
225 label = "sandbox:red";
226 };
227
228 martinet {
229 gpios = <&gpio_a 2 0>;
230 label = "sandbox:green";
231 };
232 };
233
Stephen Warren62f2c902016-05-16 17:41:37 -0600[diff] [blame]234 mbox: mbox {
235 compatible = "sandbox,mbox";
236 #mbox-cells = <1>;
237 };
238
239 mbox-test {
240 compatible = "sandbox,mbox-test";
241 mboxes = <&mbox 100>, <&mbox 1>;
242 mbox-names = "other", "test";
243 };
244
Simon Glassd3e58e42015-07-06 12:54:32 -0600[diff] [blame]245 mmc {
246 compatible = "sandbox,mmc";
247 };
248
Simon Glass3a6eae62015-03-05 12:25:34 -0700[diff] [blame]249 pci: pci-controller {
250 compatible = "sandbox,pci";
251 device_type = "pci";
252 #address-cells = <3>;
253 #size-cells = <2>;
254 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000
255 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
256 pci@1f,0 {
257 compatible = "pci-generic";
258 reg = <0xf800 0 0 0 0>;
259 emul@1f,0 {
260 compatible = "sandbox,swap-case";
261 };
262 };
263 };
264
Stephen Warren92c67fa2016-07-13 13:45:31 -0600[diff] [blame]265 pwrdom: power-domain {
266 compatible = "sandbox,power-domain";
267 #power-domain-cells = <1>;
268 };
269
270 power-domain-test {
271 compatible = "sandbox,power-domain-test";
272 power-domains = <&pwrdom 2>;
273 };
274
Simon Glass3d355e62015-07-06 12:54:31 -0600[diff] [blame]275 ram {
276 compatible = "sandbox,ram";
277 };
278
Simon Glassd860f222015-07-06 12:54:29 -0600[diff] [blame]279 reset@0 {
280 compatible = "sandbox,warm-reset";
281 };
282
283 reset@1 {
284 compatible = "sandbox,reset";
285 };
286
Stephen Warren6488e642016-06-17 09:43:59 -0600[diff] [blame]287 resetc: reset-ctl {
288 compatible = "sandbox,reset-ctl";
289 #reset-cells = <1>;
290 };
291
292 reset-ctl-test {
293 compatible = "sandbox,reset-ctl-test";
294 resets = <&resetc 100>, <&resetc 2>;
295 reset-names = "other", "test";
296 };
297
Nishanth Menonedf85812015-09-17 15:42:41 -0500[diff] [blame]298 rproc_1: rproc@1 {
299 compatible = "sandbox,test-processor";
300 remoteproc-name = "remoteproc-test-dev1";
301 };
302
303 rproc_2: rproc@2 {
304 compatible = "sandbox,test-processor";
305 internal-memory-mapped;
306 remoteproc-name = "remoteproc-test-dev2";
307 };
308
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]309 spi@0 {
310 #address-cells = <1>;
311 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]312 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]313 compatible = "sandbox,spi";
314 cs-gpios = <0>, <&gpio_a 0>;
315 spi.bin@0 {
316 reg = <0>;
317 compatible = "spansion,m25p16", "spi-flash";
318 spi-max-frequency = <40000000>;
319 sandbox,filename = "spi.bin";
320 };
321 };
322
Simon Glasscd556522015-07-06 12:54:35 -0600[diff] [blame]323 syscon@0 {
324 compatible = "sandbox,syscon0";
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]325 reg = <0x10 4>;
Simon Glasscd556522015-07-06 12:54:35 -0600[diff] [blame]326 };
327
328 syscon@1 {
329 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]330 reg = <0x20 5
331 0x28 6
332 0x30 7
333 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -0600[diff] [blame]334 };
335
Thomas Chou6f2cfbf2015-12-11 16:27:34 +0800[diff] [blame]336 timer {
337 compatible = "sandbox,timer";
338 clock-frequency = <1000000>;
339 };
340
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]341 uart0: serial {
342 compatible = "sandbox,serial";
343 u-boot,dm-pre-reloc;
Joe Hershberger4c197242015-03-22 17:09:15 -0500[diff] [blame]344 };
345
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]346 usb_0: usb@0 {
347 compatible = "sandbox,usb";
348 status = "disabled";
349 hub {
350 compatible = "sandbox,usb-hub";
351 #address-cells = <1>;
352 #size-cells = <0>;
353 flash-stick {
354 reg = <0>;
355 compatible = "sandbox,usb-flash";
356 };
357 };
358 };
359
360 usb_1: usb@1 {
361 compatible = "sandbox,usb";
362 hub {
363 compatible = "usb-hub";
364 usb,device-class = <9>;
365 hub-emul {
366 compatible = "sandbox,usb-hub";
367 #address-cells = <1>;
368 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -0700[diff] [blame]369 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]370 reg = <0>;
371 compatible = "sandbox,usb-flash";
372 sandbox,filepath = "testflash.bin";
373 };
374
Simon Glass4700fe52015-11-08 23:48:01 -0700[diff] [blame]375 flash-stick@1 {
376 reg = <1>;
377 compatible = "sandbox,usb-flash";
378 sandbox,filepath = "testflash1.bin";
379 };
380
381 flash-stick@2 {
382 reg = <2>;
383 compatible = "sandbox,usb-flash";
384 sandbox,filepath = "testflash2.bin";
385 };
386
Simon Glassc0ccc722015-11-08 23:48:08 -0700[diff] [blame]387 keyb@3 {
388 reg = <3>;
389 compatible = "sandbox,usb-keyb";
390 };
391
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]392 };
393 };
394 };
395
396 usb_2: usb@2 {
397 compatible = "sandbox,usb";
398 status = "disabled";
399 };
400
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +0200[diff] [blame]401 spmi: spmi@0 {
402 compatible = "sandbox,spmi";
403 #address-cells = <0x1>;
404 #size-cells = <0x1>;
405 pm8916@0 {
406 compatible = "qcom,spmi-pmic";
407 reg = <0x0 0x1>;
408 #address-cells = <0x1>;
409 #size-cells = <0x1>;
410
411 spmi_gpios: gpios@c000 {
412 compatible = "qcom,pm8916-gpio";
413 reg = <0xc000 0x400>;
414 gpio-controller;
415 gpio-count = <4>;
416 #gpio-cells = <2>;
417 gpio-bank-name="spmi";
418 };
419 };
420 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]421};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]422
423#include "sandbox_pmic.dtsi"