arch/arm/dts/an7581-u-boot.dtsi

// SPDX-License-Identifier: GPL-2.0+

#include <dt-bindings/reset/airoha,en7581-reset.h>

/ {
	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		atf-reserved-memory@80000000 {
			no-map;
			reg = <0x0 0x80000000 0x0 0x40000>;
		};
	};

	clk25m: oscillator {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <25000000>;
		clock-output-names = "clkxtal";
	};

	vmmc_3v3: regulator-vmmc-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "vmmc";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	soc {
		chip_scu: syscon@1fa20000 {
			compatible = "airoha,en7581-chip-scu", "syscon";
			reg = <0x0 0x1fa20000 0x0 0x388>;
		};

		eth: ethernet@1fb50000 {
			compatible = "airoha,en7581-eth";
			reg = <0 0x1fb50000 0 0x2600>,
				<0 0x1fb54000 0 0x2000>,
				<0 0x1fb56000 0 0x2000>;
			reg-names = "fe", "qdma0", "qdma1";

			resets = <&scuclk EN7581_FE_RST>,
				 <&scuclk EN7581_FE_PDMA_RST>,
				 <&scuclk EN7581_FE_QDMA_RST>,
				 <&scuclk EN7581_DUAL_HSI0_MAC_RST>,
				 <&scuclk EN7581_DUAL_HSI1_MAC_RST>,
				 <&scuclk EN7581_HSI_MAC_RST>,
				 <&scuclk EN7581_XFP_MAC_RST>;
			reset-names = "fe", "pdma", "qdma",
				      "hsi0-mac", "hsi1-mac", "hsi-mac",
				      "xfp-mac";
		};

		switch: switch@1fb58000 {
			compatible = "airoha,en7581-switch";
			reg = <0 0x1fb58000 0 0x8000>;
		};

		mmc0: mmc@1fa0e000 {
			compatible = "mediatek,mt7622-mmc";
			reg = <0x0 0x1fa0e000 0x0 0x1000>,
				<0x0 0x1fa0c000 0x0 0x60>;
			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&scuclk EN7581_CLK_EMMC>, <&clk25m>;
			clock-names = "source", "hclk";
			bus-width = <4>;
			max-frequency = <52000000>;
			vmmc-supply = <&vmmc_3v3>;
			disable-wp;
			cap-mmc-highspeed;
			non-removable;

			assigned-clocks = <&scuclk EN7581_CLK_EMMC>;
			assigned-clock-rates = <200000000>;
		};
	};
};

&scuclk {
	compatible = "airoha,en7581-scu", "syscon";
};

&uart1 {
	bootph-all;
};