Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 1 | /* |
| 2 | * File: include/asm-blackfin/arch-bf533/anomaly.h |
| 3 | * Based on: |
| 4 | * Author: |
| 5 | * |
| 6 | * Created: |
| 7 | * Description: |
| 8 | * |
| 9 | * Rev: |
| 10 | * |
| 11 | * Modified: |
| 12 | * |
| 13 | * |
| 14 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ |
| 15 | * |
| 16 | * This program is free software; you can redistribute it and/or modify |
| 17 | * it under the terms of the GNU General Public License as published by |
| 18 | * the Free Software Foundation; either version 2, or (at your option) |
| 19 | * any later version. |
| 20 | * |
| 21 | * This program is distributed in the hope that it will be useful, |
| 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 24 | * GNU General Public License for more details. |
| 25 | * |
| 26 | * You should have received a copy of the GNU General Public License |
| 27 | * along with this program; see the file COPYING. |
| 28 | * If not, write to the Free Software Foundation, |
| 29 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| 30 | */ |
| 31 | |
| 32 | /* This file shoule be up to date with: |
| 33 | * - Revision U, May 17, 2006; ADSP-BF533 Blackfin Processor Anomaly List |
| 34 | * - Revision Y, May 17, 2006; ADSP-BF532 Blackfin Processor Anomaly List |
| 35 | * - Revision T, May 17, 2006; ADSP-BF531 Blackfin Processor Anomaly List |
| 36 | */ |
| 37 | |
| 38 | #ifndef _MACH_ANOMALY_H_ |
| 39 | #define _MACH_ANOMALY_H_ |
| 40 | |
| 41 | /* We do not support 0.1 or 0.2 silicon - sorry */ |
| 42 | #if (defined(CONFIG_BF_REV_0_1) || defined(CONFIG_BF_REV_0_2)) |
| 43 | #error Kernel will not work on BF533 Version 0.1 or 0.2 |
| 44 | #endif |
| 45 | |
| 46 | /* Issues that are common to 0.5, 0.4, and 0.3 silicon */ |
| 47 | #if (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3)) |
| 48 | #define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 49 | slot1 and store of a P register in slot 2 is not |
| 50 | supported */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 51 | #define ANOMALY_05000105 /* Watchpoint Status Register (WPSTAT) bits are set on |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 52 | every corresponding match */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 53 | #define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 54 | Channel DMA stops */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 55 | #define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 56 | registers. */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 57 | #define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 58 | upper bits*/ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 59 | #define ANOMALY_05000167 /* Turning Serial Ports on With External Frame Syncs */ |
| 60 | #define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 61 | syncs */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 62 | #define ANOMALY_05000208 /* VSTAT status bit in PLL_STAT register is not |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 63 | functional */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 64 | #define ANOMALY_05000219 /* NMI event at boot time results in unpredictable |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 65 | state */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 66 | #define ANOMALY_05000229 /* SPI Slave Boot Mode modifies registers */ |
| 67 | #define ANOMALY_05000272 /* Certain data cache write through modes fail for |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 68 | VDDint <=0.9V */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 69 | #define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */ |
| 70 | #define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 71 | an edge is detected may clear interrupt */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 72 | #define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 73 | DMA system instability */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 74 | #define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 75 | not restored */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 76 | #define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 77 | control */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 78 | #define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 79 | killed in a particular stage*/ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 80 | #endif |
| 81 | |
| 82 | /* These issues only occur on 0.3 or 0.4 BF533 */ |
| 83 | #if (defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3)) |
| 84 | #define ANOMALY_05000099 /* UART Line Status Register (UART_LSR) bits are not |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 85 | updated at the same time. */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 86 | #define ANOMALY_05000158 /* Boot fails when data cache enabled: Data from a Data |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 87 | Cache Fill can be corrupted after or during |
| 88 | Instruction DMA if certain core stalls exist */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 89 | #define ANOMALY_05000179 /* PPI_COUNT cannot be programmed to 0 in General |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 90 | Purpose TX or RX modes */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 91 | #define ANOMALY_05000198 /* Failing SYSTEM MMR accesses when stalled by |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 92 | preceding memory read */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 93 | #define ANOMALY_05000200 /* SPORT TFS and DT are incorrectly driven during |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 94 | inactive channels in certain conditions */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 95 | #define ANOMALY_05000202 /* Possible infinite stall with specific dual dag |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 96 | situation */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 97 | #define ANOMALY_05000215 /* UART TX Interrupt masked erroneously */ |
| 98 | #define ANOMALY_05000225 /* Incorrect pulse-width of UART start-bit */ |
| 99 | #define ANOMALY_05000227 /* Scratchpad memory bank reads may return incorrect |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 100 | data*/ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 101 | #define ANOMALY_05000230 /* UART Receiver is less robust against Baudrate |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 102 | Differences in certain Conditions */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 103 | #define ANOMALY_05000231 /* UART STB bit incorrectly affects receiver setting */ |
| 104 | #define ANOMALY_05000242 /* DF bit in PLL_CTL register does not respond to |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 105 | hardware reset */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 106 | #define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 107 | IDLE around a Change of Control causes |
| 108 | unpredictable results */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 109 | #define ANOMALY_05000245 /* Spurious Hardware Error from an access in the |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 110 | shadow of a conditional branch */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 111 | #define ANOMALY_05000246 /* Data CPLB's should prevent spurious hardware |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 112 | errors */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 113 | #define ANOMALY_05000253 /* Maximum external clock speed for Timers */ |
| 114 | #define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 115 | interrupt not functional */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 116 | #define ANOMALY_05000257 /* An interrupt or exception during short Hardware |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 117 | loops may cause the instruction fetch unit to |
| 118 | malfunction */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 119 | #define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 120 | the ICPLB Data registers differ */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 121 | #define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */ |
| 122 | #define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */ |
| 123 | #define ANOMALY_05000262 /* Stores to data cache may be lost */ |
| 124 | #define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */ |
| 125 | #define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 126 | instruction will cause an infinite stall in the |
| 127 | second to last instruction in a hardware loop */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 128 | #define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 129 | SPORT external receive and transmit clocks. */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 130 | #define ANOMALY_05000269 /* High I/O activity causes the output voltage of the |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 131 | internal voltage regulator (VDDint) to increase. */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 132 | #define ANOMALY_05000270 /* High I/O activity causes the output voltage of the |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 133 | internal voltage regulator (VDDint) to decrease */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 134 | #endif |
| 135 | |
| 136 | /* These issues are only on 0.4 silicon */ |
| 137 | #if (defined(CONFIG_BF_REV_0_4)) |
| 138 | #define ANOMALY_05000234 /* Incorrect Revision Number in DSPID Register */ |
| 139 | #define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 140 | (TDM) */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 141 | #endif |
| 142 | |
| 143 | /* These issues are only on 0.3 silicon */ |
| 144 | #if defined(CONFIG_BF_REV_0_3) |
| 145 | #define ANOMALY_05000183 /* Timer Pin limitations for PPI TX Modes with |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 146 | External Frame Syncs */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 147 | #define ANOMALY_05000189 /* False Protection Exceptions caused by Speculative |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 148 | Instruction or Data Fetches, or by Fetches at the |
| 149 | boundary of reserved memory space */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 150 | #define ANOMALY_05000193 /* False Flag Pin Interrupts on Edge Sensitive Inputs |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 151 | when polarity setting is changed */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 152 | #define ANOMALY_05000194 /* Sport Restarting in specific modes may cause data |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 153 | corruption */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 154 | #define ANOMALY_05000199 /* DMA current address shows wrong value during carry |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 155 | fix */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 156 | #define ANOMALY_05000201 /* Receive frame sync not ignored during active |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 157 | frames in sport MCM */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 158 | #define ANOMALY_05000203 /* Specific sequence that can cause DMA error or DMA |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 159 | stopping */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 160 | #if defined(CONFIG_BF533) |
| 161 | #define ANOMALY_05000204 /* Incorrect data read with write-through cache and |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 162 | allocate cache lines on reads only mode */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 163 | #endif /* CONFIG_BF533 */ |
| 164 | #define ANOMALY_05000207 /* Recovery from "brown-out" condition */ |
| 165 | #define ANOMALY_05000209 /* Speed-Path in computational unit affects certain |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 166 | instructions */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 167 | #define ANOMALY_05000233 /* PPI_FS3 is not driven in 2 or 3 internal Frame |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 168 | Sync Transmit Mode */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 169 | #define ANOMALY_05000271 /* Spontaneous reset of Internal Voltage Regulator */ |
| 170 | #endif |
| 171 | |
| 172 | #endif /* _MACH_ANOMALY_H_ */ |