Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Stephan Linz | fc77d51 | 2012-07-29 00:25:35 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Xilinx SPI driver |
| 4 | * |
Jagan Teki | 48a0dbd | 2015-06-27 00:51:27 +0530 | [diff] [blame] | 5 | * Supports 8 bit SPI transfers only, with or w/o FIFO |
Stephan Linz | fc77d51 | 2012-07-29 00:25:35 +0200 | [diff] [blame] | 6 | * |
Jagan Teki | 48a0dbd | 2015-06-27 00:51:27 +0530 | [diff] [blame] | 7 | * Based on bfin_spi.c, by way of altera_spi.c |
Jagan Teki | fdc2b3d | 2015-06-29 13:15:18 +0530 | [diff] [blame] | 8 | * Copyright (c) 2015 Jagan Teki <jteki@openedev.com> |
Stephan Linz | fc77d51 | 2012-07-29 00:25:35 +0200 | [diff] [blame] | 9 | * Copyright (c) 2012 Stephan Linz <linz@li-pro.net> |
Jagan Teki | 48a0dbd | 2015-06-27 00:51:27 +0530 | [diff] [blame] | 10 | * Copyright (c) 2010 Graeme Smecher <graeme.smecher@mail.mcgill.ca> |
| 11 | * Copyright (c) 2010 Thomas Chou <thomas@wytron.com.tw> |
| 12 | * Copyright (c) 2005-2008 Analog Devices Inc. |
Stephan Linz | fc77d51 | 2012-07-29 00:25:35 +0200 | [diff] [blame] | 13 | */ |
Jagan Teki | 48a0dbd | 2015-06-27 00:51:27 +0530 | [diff] [blame] | 14 | |
Stephan Linz | fc77d51 | 2012-07-29 00:25:35 +0200 | [diff] [blame] | 15 | #include <config.h> |
| 16 | #include <common.h> |
Jagan Teki | fdc2b3d | 2015-06-29 13:15:18 +0530 | [diff] [blame] | 17 | #include <dm.h> |
| 18 | #include <errno.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 19 | #include <log.h> |
Stephan Linz | fc77d51 | 2012-07-29 00:25:35 +0200 | [diff] [blame] | 20 | #include <malloc.h> |
| 21 | #include <spi.h> |
Jagan Teki | 41fcbba | 2015-06-27 00:51:37 +0530 | [diff] [blame] | 22 | #include <asm/io.h> |
Vipul Kumar | 90098ba | 2018-06-30 08:15:18 +0530 | [diff] [blame] | 23 | #include <wait_bit.h> |
Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 24 | #include <linux/bitops.h> |
Stephan Linz | fc77d51 | 2012-07-29 00:25:35 +0200 | [diff] [blame] | 25 | |
Jagan Teki | 23e281d | 2015-06-27 00:51:26 +0530 | [diff] [blame] | 26 | /* |
Jagan Teki | 48a0dbd | 2015-06-27 00:51:27 +0530 | [diff] [blame] | 27 | * [0]: http://www.xilinx.com/support/documentation |
Jagan Teki | 23e281d | 2015-06-27 00:51:26 +0530 | [diff] [blame] | 28 | * |
Jagan Teki | 48a0dbd | 2015-06-27 00:51:27 +0530 | [diff] [blame] | 29 | * Xilinx SPI Register Definitions |
Jagan Teki | 23e281d | 2015-06-27 00:51:26 +0530 | [diff] [blame] | 30 | * [1]: [0]/ip_documentation/xps_spi.pdf |
| 31 | * page 8, Register Descriptions |
| 32 | * [2]: [0]/ip_documentation/axi_spi_ds742.pdf |
| 33 | * page 7, Register Overview Table |
| 34 | */ |
Jagan Teki | 23e281d | 2015-06-27 00:51:26 +0530 | [diff] [blame] | 35 | |
| 36 | /* SPI Control Register (spicr), [1] p9, [2] p8 */ |
Jagan Teki | f0a0141 | 2015-10-23 01:39:31 +0530 | [diff] [blame] | 37 | #define SPICR_LSB_FIRST BIT(9) |
| 38 | #define SPICR_MASTER_INHIBIT BIT(8) |
| 39 | #define SPICR_MANUAL_SS BIT(7) |
| 40 | #define SPICR_RXFIFO_RESEST BIT(6) |
| 41 | #define SPICR_TXFIFO_RESEST BIT(5) |
| 42 | #define SPICR_CPHA BIT(4) |
| 43 | #define SPICR_CPOL BIT(3) |
| 44 | #define SPICR_MASTER_MODE BIT(2) |
| 45 | #define SPICR_SPE BIT(1) |
| 46 | #define SPICR_LOOP BIT(0) |
Jagan Teki | 23e281d | 2015-06-27 00:51:26 +0530 | [diff] [blame] | 47 | |
| 48 | /* SPI Status Register (spisr), [1] p11, [2] p10 */ |
Jagan Teki | f0a0141 | 2015-10-23 01:39:31 +0530 | [diff] [blame] | 49 | #define SPISR_SLAVE_MODE_SELECT BIT(5) |
| 50 | #define SPISR_MODF BIT(4) |
| 51 | #define SPISR_TX_FULL BIT(3) |
| 52 | #define SPISR_TX_EMPTY BIT(2) |
| 53 | #define SPISR_RX_FULL BIT(1) |
| 54 | #define SPISR_RX_EMPTY BIT(0) |
Jagan Teki | 23e281d | 2015-06-27 00:51:26 +0530 | [diff] [blame] | 55 | |
| 56 | /* SPI Data Transmit Register (spidtr), [1] p12, [2] p12 */ |
Jagan Teki | a2888d0 | 2015-10-23 01:03:44 +0530 | [diff] [blame] | 57 | #define SPIDTR_8BIT_MASK GENMASK(7, 0) |
| 58 | #define SPIDTR_16BIT_MASK GENMASK(15, 0) |
| 59 | #define SPIDTR_32BIT_MASK GENMASK(31, 0) |
Jagan Teki | 23e281d | 2015-06-27 00:51:26 +0530 | [diff] [blame] | 60 | |
| 61 | /* SPI Data Receive Register (spidrr), [1] p12, [2] p12 */ |
Jagan Teki | a2888d0 | 2015-10-23 01:03:44 +0530 | [diff] [blame] | 62 | #define SPIDRR_8BIT_MASK GENMASK(7, 0) |
| 63 | #define SPIDRR_16BIT_MASK GENMASK(15, 0) |
| 64 | #define SPIDRR_32BIT_MASK GENMASK(31, 0) |
Jagan Teki | 23e281d | 2015-06-27 00:51:26 +0530 | [diff] [blame] | 65 | |
| 66 | /* SPI Slave Select Register (spissr), [1] p13, [2] p13 */ |
| 67 | #define SPISSR_MASK(cs) (1 << (cs)) |
| 68 | #define SPISSR_ACT(cs) ~SPISSR_MASK(cs) |
| 69 | #define SPISSR_OFF ~0UL |
| 70 | |
Jagan Teki | 23e281d | 2015-06-27 00:51:26 +0530 | [diff] [blame] | 71 | /* SPI Software Reset Register (ssr) */ |
| 72 | #define SPISSR_RESET_VALUE 0x0a |
| 73 | |
Jagan Teki | 48a0dbd | 2015-06-27 00:51:27 +0530 | [diff] [blame] | 74 | #define XILSPI_MAX_XFER_BITS 8 |
| 75 | #define XILSPI_SPICR_DFLT_ON (SPICR_MANUAL_SS | SPICR_MASTER_MODE | \ |
| 76 | SPICR_SPE) |
| 77 | #define XILSPI_SPICR_DFLT_OFF (SPICR_MASTER_INHIBIT | SPICR_MANUAL_SS) |
| 78 | |
| 79 | #ifndef CONFIG_XILINX_SPI_IDLE_VAL |
Jagan Teki | a2888d0 | 2015-10-23 01:03:44 +0530 | [diff] [blame] | 80 | #define CONFIG_XILINX_SPI_IDLE_VAL GENMASK(7, 0) |
Jagan Teki | 48a0dbd | 2015-06-27 00:51:27 +0530 | [diff] [blame] | 81 | #endif |
| 82 | |
Vipul Kumar | 90098ba | 2018-06-30 08:15:18 +0530 | [diff] [blame] | 83 | #define XILINX_SPISR_TIMEOUT 10000 /* in milliseconds */ |
| 84 | |
Jagan Teki | 48a0dbd | 2015-06-27 00:51:27 +0530 | [diff] [blame] | 85 | /* xilinx spi register set */ |
Jagan Teki | fdc2b3d | 2015-06-29 13:15:18 +0530 | [diff] [blame] | 86 | struct xilinx_spi_regs { |
Jagan Teki | 48a0dbd | 2015-06-27 00:51:27 +0530 | [diff] [blame] | 87 | u32 __space0__[7]; |
| 88 | u32 dgier; /* Device Global Interrupt Enable Register (DGIER) */ |
| 89 | u32 ipisr; /* IP Interrupt Status Register (IPISR) */ |
| 90 | u32 __space1__; |
| 91 | u32 ipier; /* IP Interrupt Enable Register (IPIER) */ |
| 92 | u32 __space2__[5]; |
| 93 | u32 srr; /* Softare Reset Register (SRR) */ |
| 94 | u32 __space3__[7]; |
| 95 | u32 spicr; /* SPI Control Register (SPICR) */ |
| 96 | u32 spisr; /* SPI Status Register (SPISR) */ |
| 97 | u32 spidtr; /* SPI Data Transmit Register (SPIDTR) */ |
| 98 | u32 spidrr; /* SPI Data Receive Register (SPIDRR) */ |
| 99 | u32 spissr; /* SPI Slave Select Register (SPISSR) */ |
| 100 | u32 spitfor; /* SPI Transmit FIFO Occupancy Register (SPITFOR) */ |
| 101 | u32 spirfor; /* SPI Receive FIFO Occupancy Register (SPIRFOR) */ |
| 102 | }; |
| 103 | |
Jagan Teki | fdc2b3d | 2015-06-29 13:15:18 +0530 | [diff] [blame] | 104 | /* xilinx spi priv */ |
| 105 | struct xilinx_spi_priv { |
| 106 | struct xilinx_spi_regs *regs; |
Jagan Teki | 23e281d | 2015-06-27 00:51:26 +0530 | [diff] [blame] | 107 | unsigned int freq; |
| 108 | unsigned int mode; |
Vipul Kumar | 90098ba | 2018-06-30 08:15:18 +0530 | [diff] [blame] | 109 | unsigned int fifo_depth; |
Vipul Kumar | c7e2aae | 2018-06-30 08:15:19 +0530 | [diff] [blame] | 110 | u8 startup; |
Jagan Teki | 23e281d | 2015-06-27 00:51:26 +0530 | [diff] [blame] | 111 | }; |
| 112 | |
Jagan Teki | fdc2b3d | 2015-06-29 13:15:18 +0530 | [diff] [blame] | 113 | static int xilinx_spi_probe(struct udevice *bus) |
Stephan Linz | fc77d51 | 2012-07-29 00:25:35 +0200 | [diff] [blame] | 114 | { |
Jagan Teki | fdc2b3d | 2015-06-29 13:15:18 +0530 | [diff] [blame] | 115 | struct xilinx_spi_priv *priv = dev_get_priv(bus); |
| 116 | struct xilinx_spi_regs *regs = priv->regs; |
Stephan Linz | fc77d51 | 2012-07-29 00:25:35 +0200 | [diff] [blame] | 117 | |
Vipul Kumar | 646b460 | 2018-06-30 08:15:20 +0530 | [diff] [blame] | 118 | priv->regs = (struct xilinx_spi_regs *)dev_read_addr(bus); |
Stephan Linz | fc77d51 | 2012-07-29 00:25:35 +0200 | [diff] [blame] | 119 | |
Vipul Kumar | 646b460 | 2018-06-30 08:15:20 +0530 | [diff] [blame] | 120 | priv->fifo_depth = dev_read_u32_default(bus, "fifo-size", 0); |
Vipul Kumar | 90098ba | 2018-06-30 08:15:18 +0530 | [diff] [blame] | 121 | |
Jagan Teki | fdc2b3d | 2015-06-29 13:15:18 +0530 | [diff] [blame] | 122 | writel(SPISSR_RESET_VALUE, ®s->srr); |
Stephan Linz | fc77d51 | 2012-07-29 00:25:35 +0200 | [diff] [blame] | 123 | |
Jagan Teki | fdc2b3d | 2015-06-29 13:15:18 +0530 | [diff] [blame] | 124 | return 0; |
Stephan Linz | fc77d51 | 2012-07-29 00:25:35 +0200 | [diff] [blame] | 125 | } |
| 126 | |
Jagan Teki | fdc2b3d | 2015-06-29 13:15:18 +0530 | [diff] [blame] | 127 | static void spi_cs_activate(struct udevice *dev, uint cs) |
Stephan Linz | fc77d51 | 2012-07-29 00:25:35 +0200 | [diff] [blame] | 128 | { |
Jagan Teki | fdc2b3d | 2015-06-29 13:15:18 +0530 | [diff] [blame] | 129 | struct udevice *bus = dev_get_parent(dev); |
| 130 | struct xilinx_spi_priv *priv = dev_get_priv(bus); |
| 131 | struct xilinx_spi_regs *regs = priv->regs; |
Stephan Linz | fc77d51 | 2012-07-29 00:25:35 +0200 | [diff] [blame] | 132 | |
Jagan Teki | fdc2b3d | 2015-06-29 13:15:18 +0530 | [diff] [blame] | 133 | writel(SPISSR_ACT(cs), ®s->spissr); |
Stephan Linz | fc77d51 | 2012-07-29 00:25:35 +0200 | [diff] [blame] | 134 | } |
| 135 | |
Jagan Teki | fdc2b3d | 2015-06-29 13:15:18 +0530 | [diff] [blame] | 136 | static void spi_cs_deactivate(struct udevice *dev) |
Stephan Linz | fc77d51 | 2012-07-29 00:25:35 +0200 | [diff] [blame] | 137 | { |
Jagan Teki | fdc2b3d | 2015-06-29 13:15:18 +0530 | [diff] [blame] | 138 | struct udevice *bus = dev_get_parent(dev); |
| 139 | struct xilinx_spi_priv *priv = dev_get_priv(bus); |
| 140 | struct xilinx_spi_regs *regs = priv->regs; |
Stephan Linz | fc77d51 | 2012-07-29 00:25:35 +0200 | [diff] [blame] | 141 | |
Jagan Teki | fdc2b3d | 2015-06-29 13:15:18 +0530 | [diff] [blame] | 142 | writel(SPISSR_OFF, ®s->spissr); |
Stephan Linz | fc77d51 | 2012-07-29 00:25:35 +0200 | [diff] [blame] | 143 | } |
| 144 | |
Jagan Teki | fdc2b3d | 2015-06-29 13:15:18 +0530 | [diff] [blame] | 145 | static int xilinx_spi_claim_bus(struct udevice *dev) |
Stephan Linz | fc77d51 | 2012-07-29 00:25:35 +0200 | [diff] [blame] | 146 | { |
Jagan Teki | fdc2b3d | 2015-06-29 13:15:18 +0530 | [diff] [blame] | 147 | struct udevice *bus = dev_get_parent(dev); |
| 148 | struct xilinx_spi_priv *priv = dev_get_priv(bus); |
| 149 | struct xilinx_spi_regs *regs = priv->regs; |
Stephan Linz | fc77d51 | 2012-07-29 00:25:35 +0200 | [diff] [blame] | 150 | |
Jagan Teki | fdc2b3d | 2015-06-29 13:15:18 +0530 | [diff] [blame] | 151 | writel(SPISSR_OFF, ®s->spissr); |
| 152 | writel(XILSPI_SPICR_DFLT_ON, ®s->spicr); |
Stephan Linz | fc77d51 | 2012-07-29 00:25:35 +0200 | [diff] [blame] | 153 | |
Stephan Linz | fc77d51 | 2012-07-29 00:25:35 +0200 | [diff] [blame] | 154 | return 0; |
| 155 | } |
| 156 | |
Jagan Teki | fdc2b3d | 2015-06-29 13:15:18 +0530 | [diff] [blame] | 157 | static int xilinx_spi_release_bus(struct udevice *dev) |
Stephan Linz | fc77d51 | 2012-07-29 00:25:35 +0200 | [diff] [blame] | 158 | { |
Jagan Teki | fdc2b3d | 2015-06-29 13:15:18 +0530 | [diff] [blame] | 159 | struct udevice *bus = dev_get_parent(dev); |
| 160 | struct xilinx_spi_priv *priv = dev_get_priv(bus); |
| 161 | struct xilinx_spi_regs *regs = priv->regs; |
Stephan Linz | fc77d51 | 2012-07-29 00:25:35 +0200 | [diff] [blame] | 162 | |
Jagan Teki | fdc2b3d | 2015-06-29 13:15:18 +0530 | [diff] [blame] | 163 | writel(SPISSR_OFF, ®s->spissr); |
| 164 | writel(XILSPI_SPICR_DFLT_OFF, ®s->spicr); |
| 165 | |
| 166 | return 0; |
Stephan Linz | fc77d51 | 2012-07-29 00:25:35 +0200 | [diff] [blame] | 167 | } |
| 168 | |
Vipul Kumar | 90098ba | 2018-06-30 08:15:18 +0530 | [diff] [blame] | 169 | static u32 xilinx_spi_fill_txfifo(struct udevice *bus, const u8 *txp, |
| 170 | u32 txbytes) |
| 171 | { |
| 172 | struct xilinx_spi_priv *priv = dev_get_priv(bus); |
| 173 | struct xilinx_spi_regs *regs = priv->regs; |
| 174 | unsigned char d; |
| 175 | u32 i = 0; |
| 176 | |
| 177 | while (txbytes && !(readl(®s->spisr) & SPISR_TX_FULL) && |
| 178 | i < priv->fifo_depth) { |
| 179 | d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL; |
| 180 | debug("spi_xfer: tx:%x ", d); |
| 181 | /* write out and wait for processing (receive data) */ |
| 182 | writel(d & SPIDTR_8BIT_MASK, ®s->spidtr); |
| 183 | txbytes--; |
| 184 | i++; |
| 185 | } |
| 186 | |
| 187 | return i; |
| 188 | } |
| 189 | |
| 190 | static u32 xilinx_spi_read_rxfifo(struct udevice *bus, u8 *rxp, u32 rxbytes) |
| 191 | { |
| 192 | struct xilinx_spi_priv *priv = dev_get_priv(bus); |
| 193 | struct xilinx_spi_regs *regs = priv->regs; |
| 194 | unsigned char d; |
| 195 | unsigned int i = 0; |
| 196 | |
| 197 | while (rxbytes && !(readl(®s->spisr) & SPISR_RX_EMPTY)) { |
| 198 | d = readl(®s->spidrr) & SPIDRR_8BIT_MASK; |
| 199 | if (rxp) |
| 200 | *rxp++ = d; |
| 201 | debug("spi_xfer: rx:%x\n", d); |
| 202 | rxbytes--; |
| 203 | i++; |
| 204 | } |
| 205 | debug("Rx_done\n"); |
| 206 | |
| 207 | return i; |
| 208 | } |
| 209 | |
Vipul Kumar | c7e2aae | 2018-06-30 08:15:19 +0530 | [diff] [blame] | 210 | static void xilinx_spi_startup_block(struct udevice *dev, unsigned int bytes, |
| 211 | const void *dout, void *din) |
| 212 | { |
| 213 | struct udevice *bus = dev_get_parent(dev); |
| 214 | struct xilinx_spi_priv *priv = dev_get_priv(bus); |
| 215 | struct xilinx_spi_regs *regs = priv->regs; |
| 216 | struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); |
| 217 | const unsigned char *txp = dout; |
| 218 | unsigned char *rxp = din; |
| 219 | u32 reg, count; |
| 220 | u32 txbytes = bytes; |
| 221 | u32 rxbytes = bytes; |
| 222 | |
| 223 | /* |
| 224 | * This loop runs two times. First time to send the command. |
| 225 | * Second time to transfer data. After transferring data, |
| 226 | * it sets txp to the initial value for the normal operation. |
| 227 | */ |
| 228 | for ( ; priv->startup < 2; priv->startup++) { |
| 229 | count = xilinx_spi_fill_txfifo(bus, txp, txbytes); |
| 230 | reg = readl(®s->spicr) & ~SPICR_MASTER_INHIBIT; |
| 231 | writel(reg, ®s->spicr); |
| 232 | count = xilinx_spi_read_rxfifo(bus, rxp, rxbytes); |
| 233 | txp = din; |
| 234 | |
| 235 | if (priv->startup) { |
| 236 | spi_cs_deactivate(dev); |
| 237 | spi_cs_activate(dev, slave_plat->cs); |
| 238 | txp = dout; |
| 239 | } |
| 240 | } |
| 241 | } |
| 242 | |
Jagan Teki | fdc2b3d | 2015-06-29 13:15:18 +0530 | [diff] [blame] | 243 | static int xilinx_spi_xfer(struct udevice *dev, unsigned int bitlen, |
| 244 | const void *dout, void *din, unsigned long flags) |
Stephan Linz | fc77d51 | 2012-07-29 00:25:35 +0200 | [diff] [blame] | 245 | { |
Jagan Teki | fdc2b3d | 2015-06-29 13:15:18 +0530 | [diff] [blame] | 246 | struct udevice *bus = dev_get_parent(dev); |
| 247 | struct xilinx_spi_priv *priv = dev_get_priv(bus); |
| 248 | struct xilinx_spi_regs *regs = priv->regs; |
| 249 | struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); |
Stephan Linz | fc77d51 | 2012-07-29 00:25:35 +0200 | [diff] [blame] | 250 | /* assume spi core configured to do 8 bit transfers */ |
| 251 | unsigned int bytes = bitlen / XILSPI_MAX_XFER_BITS; |
| 252 | const unsigned char *txp = dout; |
| 253 | unsigned char *rxp = din; |
Vipul Kumar | 90098ba | 2018-06-30 08:15:18 +0530 | [diff] [blame] | 254 | u32 txbytes = bytes; |
| 255 | u32 rxbytes = bytes; |
| 256 | u32 reg, count, timeout; |
| 257 | int ret; |
Stephan Linz | fc77d51 | 2012-07-29 00:25:35 +0200 | [diff] [blame] | 258 | |
Jagan Teki | 48a0dbd | 2015-06-27 00:51:27 +0530 | [diff] [blame] | 259 | debug("spi_xfer: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", |
Jagan Teki | fdc2b3d | 2015-06-29 13:15:18 +0530 | [diff] [blame] | 260 | bus->seq, slave_plat->cs, bitlen, bytes, flags); |
Jagan Teki | 48a0dbd | 2015-06-27 00:51:27 +0530 | [diff] [blame] | 261 | |
Stephan Linz | fc77d51 | 2012-07-29 00:25:35 +0200 | [diff] [blame] | 262 | if (bitlen == 0) |
| 263 | goto done; |
| 264 | |
| 265 | if (bitlen % XILSPI_MAX_XFER_BITS) { |
Jagan Teki | 48a0dbd | 2015-06-27 00:51:27 +0530 | [diff] [blame] | 266 | printf("XILSPI warning: Not a multiple of %d bits\n", |
| 267 | XILSPI_MAX_XFER_BITS); |
Stephan Linz | fc77d51 | 2012-07-29 00:25:35 +0200 | [diff] [blame] | 268 | flags |= SPI_XFER_END; |
| 269 | goto done; |
| 270 | } |
| 271 | |
Stephan Linz | fc77d51 | 2012-07-29 00:25:35 +0200 | [diff] [blame] | 272 | if (flags & SPI_XFER_BEGIN) |
Jagan Teki | fdc2b3d | 2015-06-29 13:15:18 +0530 | [diff] [blame] | 273 | spi_cs_activate(dev, slave_plat->cs); |
Stephan Linz | fc77d51 | 2012-07-29 00:25:35 +0200 | [diff] [blame] | 274 | |
Vipul Kumar | c7e2aae | 2018-06-30 08:15:19 +0530 | [diff] [blame] | 275 | /* |
| 276 | * This is the work around for the startup block issue in |
| 277 | * the spi controller. SPI clock is passing through STARTUP |
| 278 | * block to FLASH. STARTUP block don't provide clock as soon |
| 279 | * as QSPI provides command. So first command fails. |
| 280 | */ |
| 281 | xilinx_spi_startup_block(dev, bytes, dout, din); |
Stephan Linz | fc77d51 | 2012-07-29 00:25:35 +0200 | [diff] [blame] | 282 | |
Vipul Kumar | 90098ba | 2018-06-30 08:15:18 +0530 | [diff] [blame] | 283 | while (txbytes && rxbytes) { |
| 284 | count = xilinx_spi_fill_txfifo(bus, txp, txbytes); |
| 285 | reg = readl(®s->spicr) & ~SPICR_MASTER_INHIBIT; |
| 286 | writel(reg, ®s->spicr); |
| 287 | txbytes -= count; |
| 288 | if (txp) |
| 289 | txp += count; |
Stephan Linz | fc77d51 | 2012-07-29 00:25:35 +0200 | [diff] [blame] | 290 | |
Vipul Kumar | 90098ba | 2018-06-30 08:15:18 +0530 | [diff] [blame] | 291 | ret = wait_for_bit_le32(®s->spisr, SPISR_TX_EMPTY, true, |
| 292 | XILINX_SPISR_TIMEOUT, false); |
| 293 | if (ret < 0) { |
Jagan Teki | 48a0dbd | 2015-06-27 00:51:27 +0530 | [diff] [blame] | 294 | printf("XILSPI error: Xfer timeout\n"); |
Vipul Kumar | 90098ba | 2018-06-30 08:15:18 +0530 | [diff] [blame] | 295 | return ret; |
Stephan Linz | fc77d51 | 2012-07-29 00:25:35 +0200 | [diff] [blame] | 296 | } |
| 297 | |
Vipul Kumar | 90098ba | 2018-06-30 08:15:18 +0530 | [diff] [blame] | 298 | debug("txbytes:0x%x,txp:0x%p\n", txbytes, txp); |
| 299 | count = xilinx_spi_read_rxfifo(bus, rxp, rxbytes); |
| 300 | rxbytes -= count; |
Stephan Linz | fc77d51 | 2012-07-29 00:25:35 +0200 | [diff] [blame] | 301 | if (rxp) |
Vipul Kumar | 90098ba | 2018-06-30 08:15:18 +0530 | [diff] [blame] | 302 | rxp += count; |
| 303 | debug("rxbytes:0x%x rxp:0x%p\n", rxbytes, rxp); |
Stephan Linz | fc77d51 | 2012-07-29 00:25:35 +0200 | [diff] [blame] | 304 | } |
| 305 | |
| 306 | done: |
| 307 | if (flags & SPI_XFER_END) |
Jagan Teki | fdc2b3d | 2015-06-29 13:15:18 +0530 | [diff] [blame] | 308 | spi_cs_deactivate(dev); |
Stephan Linz | fc77d51 | 2012-07-29 00:25:35 +0200 | [diff] [blame] | 309 | |
| 310 | return 0; |
| 311 | } |
Jagan Teki | fdc2b3d | 2015-06-29 13:15:18 +0530 | [diff] [blame] | 312 | |
| 313 | static int xilinx_spi_set_speed(struct udevice *bus, uint speed) |
| 314 | { |
| 315 | struct xilinx_spi_priv *priv = dev_get_priv(bus); |
| 316 | |
| 317 | priv->freq = speed; |
| 318 | |
Jagan Teki | 0dc543f | 2015-09-08 01:26:29 +0530 | [diff] [blame] | 319 | debug("xilinx_spi_set_speed: regs=%p, speed=%d\n", priv->regs, |
Jagan Teki | fdc2b3d | 2015-06-29 13:15:18 +0530 | [diff] [blame] | 320 | priv->freq); |
| 321 | |
| 322 | return 0; |
| 323 | } |
| 324 | |
| 325 | static int xilinx_spi_set_mode(struct udevice *bus, uint mode) |
| 326 | { |
| 327 | struct xilinx_spi_priv *priv = dev_get_priv(bus); |
| 328 | struct xilinx_spi_regs *regs = priv->regs; |
| 329 | uint32_t spicr; |
| 330 | |
| 331 | spicr = readl(®s->spicr); |
Jagan Teki | 0dc543f | 2015-09-08 01:26:29 +0530 | [diff] [blame] | 332 | if (mode & SPI_LSB_FIRST) |
Jagan Teki | fdc2b3d | 2015-06-29 13:15:18 +0530 | [diff] [blame] | 333 | spicr |= SPICR_LSB_FIRST; |
Jagan Teki | 0dc543f | 2015-09-08 01:26:29 +0530 | [diff] [blame] | 334 | if (mode & SPI_CPHA) |
Jagan Teki | fdc2b3d | 2015-06-29 13:15:18 +0530 | [diff] [blame] | 335 | spicr |= SPICR_CPHA; |
Jagan Teki | 0dc543f | 2015-09-08 01:26:29 +0530 | [diff] [blame] | 336 | if (mode & SPI_CPOL) |
Jagan Teki | fdc2b3d | 2015-06-29 13:15:18 +0530 | [diff] [blame] | 337 | spicr |= SPICR_CPOL; |
Jagan Teki | 0dc543f | 2015-09-08 01:26:29 +0530 | [diff] [blame] | 338 | if (mode & SPI_LOOP) |
Jagan Teki | fdc2b3d | 2015-06-29 13:15:18 +0530 | [diff] [blame] | 339 | spicr |= SPICR_LOOP; |
| 340 | |
| 341 | writel(spicr, ®s->spicr); |
| 342 | priv->mode = mode; |
| 343 | |
| 344 | debug("xilinx_spi_set_mode: regs=%p, mode=%d\n", priv->regs, |
| 345 | priv->mode); |
| 346 | |
| 347 | return 0; |
| 348 | } |
| 349 | |
| 350 | static const struct dm_spi_ops xilinx_spi_ops = { |
| 351 | .claim_bus = xilinx_spi_claim_bus, |
| 352 | .release_bus = xilinx_spi_release_bus, |
| 353 | .xfer = xilinx_spi_xfer, |
| 354 | .set_speed = xilinx_spi_set_speed, |
| 355 | .set_mode = xilinx_spi_set_mode, |
| 356 | }; |
| 357 | |
| 358 | static const struct udevice_id xilinx_spi_ids[] = { |
Michal Simek | 7465f31 | 2015-12-11 12:41:14 +0100 | [diff] [blame] | 359 | { .compatible = "xlnx,xps-spi-2.00.a" }, |
| 360 | { .compatible = "xlnx,xps-spi-2.00.b" }, |
Jagan Teki | fdc2b3d | 2015-06-29 13:15:18 +0530 | [diff] [blame] | 361 | { } |
| 362 | }; |
| 363 | |
| 364 | U_BOOT_DRIVER(xilinx_spi) = { |
| 365 | .name = "xilinx_spi", |
| 366 | .id = UCLASS_SPI, |
| 367 | .of_match = xilinx_spi_ids, |
| 368 | .ops = &xilinx_spi_ops, |
| 369 | .priv_auto_alloc_size = sizeof(struct xilinx_spi_priv), |
| 370 | .probe = xilinx_spi_probe, |
| 371 | }; |