Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Marek Vasut | fefed7a | 2017-09-15 21:13:56 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com> |
Marek Vasut | fefed7a | 2017-09-15 21:13:56 +0200 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <common.h> |
| 7 | #include <clk.h> |
| 8 | #include <dm.h> |
Simon Glass | 9bc1564 | 2020-02-03 07:36:16 -0700 | [diff] [blame] | 9 | #include <malloc.h> |
| 10 | #include <dm/device_compat.h> |
Marek Vasut | f071c0a | 2019-04-21 22:46:25 +0200 | [diff] [blame] | 11 | #include <dm/pinctrl.h> |
Marek Vasut | fefed7a | 2017-09-15 21:13:56 +0200 | [diff] [blame] | 12 | #include <errno.h> |
| 13 | #include <asm/gpio.h> |
| 14 | #include <asm/io.h> |
Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 15 | #include <linux/bitops.h> |
Marek Vasut | f22c40a | 2017-11-26 18:08:53 +0100 | [diff] [blame] | 16 | #include "../pinctrl/renesas/sh_pfc.h" |
Marek Vasut | fefed7a | 2017-09-15 21:13:56 +0200 | [diff] [blame] | 17 | |
| 18 | #define GPIO_IOINTSEL 0x00 /* General IO/Interrupt Switching Register */ |
| 19 | #define GPIO_INOUTSEL 0x04 /* General Input/Output Switching Register */ |
| 20 | #define GPIO_OUTDT 0x08 /* General Output Register */ |
| 21 | #define GPIO_INDT 0x0c /* General Input Register */ |
| 22 | #define GPIO_INTDT 0x10 /* Interrupt Display Register */ |
| 23 | #define GPIO_INTCLR 0x14 /* Interrupt Clear Register */ |
| 24 | #define GPIO_INTMSK 0x18 /* Interrupt Mask Register */ |
| 25 | #define GPIO_MSKCLR 0x1c /* Interrupt Mask Clear Register */ |
| 26 | #define GPIO_POSNEG 0x20 /* Positive/Negative Logic Select Register */ |
| 27 | #define GPIO_EDGLEVEL 0x24 /* Edge/level Select Register */ |
| 28 | #define GPIO_FILONOFF 0x28 /* Chattering Prevention On/Off Register */ |
| 29 | #define GPIO_BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */ |
| 30 | |
| 31 | #define RCAR_MAX_GPIO_PER_BANK 32 |
| 32 | |
| 33 | DECLARE_GLOBAL_DATA_PTR; |
| 34 | |
| 35 | struct rcar_gpio_priv { |
Marek Vasut | f22c40a | 2017-11-26 18:08:53 +0100 | [diff] [blame] | 36 | void __iomem *regs; |
| 37 | int pfc_offset; |
Marek Vasut | fefed7a | 2017-09-15 21:13:56 +0200 | [diff] [blame] | 38 | }; |
| 39 | |
| 40 | static int rcar_gpio_get_value(struct udevice *dev, unsigned offset) |
| 41 | { |
| 42 | struct rcar_gpio_priv *priv = dev_get_priv(dev); |
| 43 | const u32 bit = BIT(offset); |
| 44 | |
| 45 | /* |
| 46 | * Testing on r8a7790 shows that INDT does not show correct pin state |
| 47 | * when configured as output, so use OUTDT in case of output pins. |
| 48 | */ |
| 49 | if (readl(priv->regs + GPIO_INOUTSEL) & bit) |
| 50 | return !!(readl(priv->regs + GPIO_OUTDT) & bit); |
| 51 | else |
| 52 | return !!(readl(priv->regs + GPIO_INDT) & bit); |
| 53 | } |
| 54 | |
| 55 | static int rcar_gpio_set_value(struct udevice *dev, unsigned offset, |
| 56 | int value) |
| 57 | { |
| 58 | struct rcar_gpio_priv *priv = dev_get_priv(dev); |
| 59 | |
| 60 | if (value) |
| 61 | setbits_le32(priv->regs + GPIO_OUTDT, BIT(offset)); |
| 62 | else |
| 63 | clrbits_le32(priv->regs + GPIO_OUTDT, BIT(offset)); |
| 64 | |
| 65 | return 0; |
| 66 | } |
| 67 | |
| 68 | static void rcar_gpio_set_direction(void __iomem *regs, unsigned offset, |
| 69 | bool output) |
| 70 | { |
| 71 | /* |
| 72 | * follow steps in the GPIO documentation for |
| 73 | * "Setting General Output Mode" and |
| 74 | * "Setting General Input Mode" |
| 75 | */ |
| 76 | |
| 77 | /* Configure postive logic in POSNEG */ |
| 78 | clrbits_le32(regs + GPIO_POSNEG, BIT(offset)); |
| 79 | |
| 80 | /* Select "General Input/Output Mode" in IOINTSEL */ |
| 81 | clrbits_le32(regs + GPIO_IOINTSEL, BIT(offset)); |
| 82 | |
| 83 | /* Select Input Mode or Output Mode in INOUTSEL */ |
| 84 | if (output) |
| 85 | setbits_le32(regs + GPIO_INOUTSEL, BIT(offset)); |
| 86 | else |
| 87 | clrbits_le32(regs + GPIO_INOUTSEL, BIT(offset)); |
| 88 | } |
| 89 | |
| 90 | static int rcar_gpio_direction_input(struct udevice *dev, unsigned offset) |
| 91 | { |
| 92 | struct rcar_gpio_priv *priv = dev_get_priv(dev); |
| 93 | |
| 94 | rcar_gpio_set_direction(priv->regs, offset, false); |
| 95 | |
| 96 | return 0; |
| 97 | } |
| 98 | |
| 99 | static int rcar_gpio_direction_output(struct udevice *dev, unsigned offset, |
| 100 | int value) |
| 101 | { |
| 102 | struct rcar_gpio_priv *priv = dev_get_priv(dev); |
| 103 | |
| 104 | /* write GPIO value to output before selecting output mode of pin */ |
| 105 | rcar_gpio_set_value(dev, offset, value); |
| 106 | rcar_gpio_set_direction(priv->regs, offset, true); |
| 107 | |
| 108 | return 0; |
| 109 | } |
| 110 | |
| 111 | static int rcar_gpio_get_function(struct udevice *dev, unsigned offset) |
| 112 | { |
| 113 | struct rcar_gpio_priv *priv = dev_get_priv(dev); |
| 114 | |
| 115 | if (readl(priv->regs + GPIO_INOUTSEL) & BIT(offset)) |
| 116 | return GPIOF_OUTPUT; |
| 117 | else |
| 118 | return GPIOF_INPUT; |
| 119 | } |
| 120 | |
Marek Vasut | f22c40a | 2017-11-26 18:08:53 +0100 | [diff] [blame] | 121 | static int rcar_gpio_request(struct udevice *dev, unsigned offset, |
| 122 | const char *label) |
| 123 | { |
Marek Vasut | f071c0a | 2019-04-21 22:46:25 +0200 | [diff] [blame] | 124 | return pinctrl_gpio_request(dev, offset); |
| 125 | } |
Marek Vasut | f22c40a | 2017-11-26 18:08:53 +0100 | [diff] [blame] | 126 | |
Marek Vasut | f071c0a | 2019-04-21 22:46:25 +0200 | [diff] [blame] | 127 | static int rcar_gpio_free(struct udevice *dev, unsigned offset) |
| 128 | { |
| 129 | return pinctrl_gpio_free(dev, offset); |
Marek Vasut | f22c40a | 2017-11-26 18:08:53 +0100 | [diff] [blame] | 130 | } |
| 131 | |
Marek Vasut | fefed7a | 2017-09-15 21:13:56 +0200 | [diff] [blame] | 132 | static const struct dm_gpio_ops rcar_gpio_ops = { |
Marek Vasut | f22c40a | 2017-11-26 18:08:53 +0100 | [diff] [blame] | 133 | .request = rcar_gpio_request, |
Simon Glass | b3a4754 | 2020-02-04 20:15:17 -0700 | [diff] [blame] | 134 | .rfree = rcar_gpio_free, |
Marek Vasut | fefed7a | 2017-09-15 21:13:56 +0200 | [diff] [blame] | 135 | .direction_input = rcar_gpio_direction_input, |
| 136 | .direction_output = rcar_gpio_direction_output, |
| 137 | .get_value = rcar_gpio_get_value, |
| 138 | .set_value = rcar_gpio_set_value, |
| 139 | .get_function = rcar_gpio_get_function, |
| 140 | }; |
| 141 | |
| 142 | static int rcar_gpio_probe(struct udevice *dev) |
| 143 | { |
| 144 | struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); |
| 145 | struct rcar_gpio_priv *priv = dev_get_priv(dev); |
| 146 | struct fdtdec_phandle_args args; |
| 147 | struct clk clk; |
| 148 | int node = dev_of_offset(dev); |
| 149 | int ret; |
| 150 | |
| 151 | priv->regs = (void __iomem *)devfdt_get_addr(dev); |
| 152 | uc_priv->bank_name = dev->name; |
| 153 | |
| 154 | ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, node, "gpio-ranges", |
| 155 | NULL, 3, 0, &args); |
Marek Vasut | f22c40a | 2017-11-26 18:08:53 +0100 | [diff] [blame] | 156 | priv->pfc_offset = ret == 0 ? args.args[1] : -1; |
Marek Vasut | fefed7a | 2017-09-15 21:13:56 +0200 | [diff] [blame] | 157 | uc_priv->gpio_count = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK; |
| 158 | |
| 159 | ret = clk_get_by_index(dev, 0, &clk); |
| 160 | if (ret < 0) { |
| 161 | dev_err(dev, "Failed to get GPIO bank clock\n"); |
| 162 | return ret; |
| 163 | } |
| 164 | |
| 165 | ret = clk_enable(&clk); |
| 166 | clk_free(&clk); |
| 167 | if (ret) { |
| 168 | dev_err(dev, "Failed to enable GPIO bank clock\n"); |
| 169 | return ret; |
| 170 | } |
| 171 | |
| 172 | return 0; |
| 173 | } |
| 174 | |
| 175 | static const struct udevice_id rcar_gpio_ids[] = { |
| 176 | { .compatible = "renesas,gpio-r8a7795" }, |
| 177 | { .compatible = "renesas,gpio-r8a7796" }, |
Marek Vasut | 87f22c2 | 2018-02-26 10:35:15 +0100 | [diff] [blame] | 178 | { .compatible = "renesas,gpio-r8a77965" }, |
Marek Vasut | 6403ab8 | 2017-10-21 11:27:04 +0200 | [diff] [blame] | 179 | { .compatible = "renesas,gpio-r8a77970" }, |
Marek Vasut | ca4b4eb | 2018-04-26 13:18:45 +0200 | [diff] [blame] | 180 | { .compatible = "renesas,gpio-r8a77990" }, |
Marek Vasut | c129f2b | 2017-10-21 11:28:06 +0200 | [diff] [blame] | 181 | { .compatible = "renesas,gpio-r8a77995" }, |
Marek Vasut | e4f6e9b | 2018-01-18 00:52:15 +0100 | [diff] [blame] | 182 | { .compatible = "renesas,rcar-gen2-gpio" }, |
Marek Vasut | 54a34ed | 2017-10-21 11:30:41 +0200 | [diff] [blame] | 183 | { .compatible = "renesas,rcar-gen3-gpio" }, |
Marek Vasut | fefed7a | 2017-09-15 21:13:56 +0200 | [diff] [blame] | 184 | { /* sentinel */ } |
| 185 | }; |
| 186 | |
| 187 | U_BOOT_DRIVER(rcar_gpio) = { |
| 188 | .name = "rcar-gpio", |
| 189 | .id = UCLASS_GPIO, |
| 190 | .of_match = rcar_gpio_ids, |
| 191 | .ops = &rcar_gpio_ops, |
| 192 | .priv_auto_alloc_size = sizeof(struct rcar_gpio_priv), |
| 193 | .probe = rcar_gpio_probe, |
| 194 | }; |