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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Chander Kashyapbfef54d2011-05-24 20:02:56 +00002/*
3 * Copyright (C) 2011 Samsung Electronics
Chander Kashyapbfef54d2011-05-24 20:02:56 +00004 */
5
6#include <common.h>
Simon Glass8e16b1e2019-12-28 10:45:05 -07007#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -06008#include <log.h>
Simon Glass274e0b02020-05-10 11:39:56 -06009#include <net.h>
Simon Glass37f11622014-10-20 19:48:37 -060010#include <asm/gpio.h>
Chander Kashyapbfef54d2011-05-24 20:02:56 +000011#include <asm/io.h>
12#include <netdev.h>
13#include <asm/arch/cpu.h>
Chander Kashyapbfef54d2011-05-24 20:02:56 +000014#include <asm/arch/mmc.h>
Rajeshwari Shinde99ae9b82013-07-04 12:29:16 +053015#include <asm/arch/periph.h>
16#include <asm/arch/pinmux.h>
Chander Kashyapbfef54d2011-05-24 20:02:56 +000017#include <asm/arch/sromc.h>
18
19DECLARE_GLOBAL_DATA_PTR;
Chander Kashyapbfef54d2011-05-24 20:02:56 +000020
21static void smc9115_pre_init(void)
22{
23 u32 smc_bw_conf, smc_bc_conf;
24
25 /* gpio configuration GPK0CON */
Akshay Saraswat1376cdd2014-05-13 10:30:14 +053026 gpio_cfg_pin(EXYNOS4_GPIO_Y00 + CONFIG_ENV_SROM_BANK, S5P_GPIO_FUNC(2));
Chander Kashyapbfef54d2011-05-24 20:02:56 +000027
28 /* Ethernet needs bus width of 16 bits */
29 smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK);
30 smc_bc_conf = SROMC_BC_TACS(0x0F) | SROMC_BC_TCOS(0x0F)
31 | SROMC_BC_TACC(0x0F) | SROMC_BC_TCOH(0x0F)
32 | SROMC_BC_TAH(0x0F) | SROMC_BC_TACP(0x0F)
33 | SROMC_BC_PMC(0x0F);
34
35 /* Select and configure the SROMC bank */
36 s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
37}
38
39int board_init(void)
40{
Chander Kashyapbfef54d2011-05-24 20:02:56 +000041 smc9115_pre_init();
42
Chander Kashyapbfef54d2011-05-24 20:02:56 +000043 gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
44 return 0;
45}
46
47int dram_init(void)
48{
49 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
50 + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
51 + get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
52 + get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE);
53
54 return 0;
55}
56
Simon Glass2f949c32017-03-31 08:40:32 -060057int dram_init_banksize(void)
Chander Kashyapbfef54d2011-05-24 20:02:56 +000058{
59 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
Minkyu Kangd4e645b2015-10-23 15:59:37 +090060 gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
Chander Kashyapf5ed2952011-09-20 21:25:02 +000061 PHYS_SDRAM_1_SIZE);
Chander Kashyapbfef54d2011-05-24 20:02:56 +000062 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
Minkyu Kangd4e645b2015-10-23 15:59:37 +090063 gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
Chander Kashyapf5ed2952011-09-20 21:25:02 +000064 PHYS_SDRAM_2_SIZE);
Chander Kashyapbfef54d2011-05-24 20:02:56 +000065 gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
Minkyu Kangd4e645b2015-10-23 15:59:37 +090066 gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3,
Chander Kashyapf5ed2952011-09-20 21:25:02 +000067 PHYS_SDRAM_3_SIZE);
Chander Kashyapbfef54d2011-05-24 20:02:56 +000068 gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
Minkyu Kangd4e645b2015-10-23 15:59:37 +090069 gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4,
Chander Kashyapf5ed2952011-09-20 21:25:02 +000070 PHYS_SDRAM_4_SIZE);
Simon Glass2f949c32017-03-31 08:40:32 -060071
72 return 0;
Chander Kashyapbfef54d2011-05-24 20:02:56 +000073}
74
75int board_eth_init(bd_t *bis)
76{
77 int rc = 0;
78#ifdef CONFIG_SMC911X
79 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
80#endif
81 return rc;
82}
83
84#ifdef CONFIG_DISPLAY_BOARDINFO
85int checkboard(void)
86{
87 printf("\nBoard: SMDKV310\n");
88 return 0;
89}
90#endif
91
Masahiro Yamada0a780172017-05-09 20:31:39 +090092#ifdef CONFIG_MMC
Chander Kashyapbfef54d2011-05-24 20:02:56 +000093int board_mmc_init(bd_t *bis)
94{
95 int i, err;
96
97 /*
98 * MMC2 SD card GPIO:
99 *
100 * GPK2[0] SD_2_CLK(2)
101 * GPK2[1] SD_2_CMD(2)
102 * GPK2[2] SD_2_CDn
103 * GPK2[3:6] SD_2_DATA[0:3](2)
104 */
Akshay Saraswat1376cdd2014-05-13 10:30:14 +0530105 for (i = EXYNOS4_GPIO_K20; i < EXYNOS4_GPIO_K27; i++) {
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000106 /* GPK2[0:6] special function 2 */
Akshay Saraswat1376cdd2014-05-13 10:30:14 +0530107 gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000108
109 /* GPK2[0:6] drv 4x */
Akshay Saraswat1376cdd2014-05-13 10:30:14 +0530110 gpio_set_drv(i, S5P_GPIO_DRV_4X);
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000111
112 /* GPK2[0:1] pull disable */
Akshay Saraswat1376cdd2014-05-13 10:30:14 +0530113 if (i == EXYNOS4_GPIO_K20 || i == EXYNOS4_GPIO_K21) {
114 gpio_set_pull(i, S5P_GPIO_PULL_NONE);
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000115 continue;
116 }
117
118 /* GPK2[2:6] pull up */
Akshay Saraswat1376cdd2014-05-13 10:30:14 +0530119 gpio_set_pull(i, S5P_GPIO_PULL_UP);
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000120 }
121 err = s5p_mmc_init(2, 4);
122 return err;
123}
124#endif
Rajeshwari Shinde99ae9b82013-07-04 12:29:16 +0530125
126static int board_uart_init(void)
127{
128 int err;
129
130 err = exynos_pinmux_config(PERIPH_ID_UART0, PINMUX_FLAG_NONE);
131 if (err) {
132 debug("UART0 not configured\n");
133 return err;
134 }
135
136 err = exynos_pinmux_config(PERIPH_ID_UART1, PINMUX_FLAG_NONE);
137 if (err) {
138 debug("UART1 not configured\n");
139 return err;
140 }
141
142 err = exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE);
143 if (err) {
144 debug("UART2 not configured\n");
145 return err;
146 }
147
148 err = exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
149 if (err) {
150 debug("UART3 not configured\n");
151 return err;
152 }
153
154 return 0;
155}
156
157#ifdef CONFIG_BOARD_EARLY_INIT_F
158int board_early_init_f(void)
159{
160 int err;
161 err = board_uart_init();
162 if (err) {
163 debug("UART init failed\n");
164 return err;
165 }
166 return err;
167}
168#endif