blob: 6870674f7a4144a6fd29eada5274519a69018ca5 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Prabhakar Kushwaha422e2ab2013-01-14 18:26:57 +00002/*
3 * Copyright 2013 Freescale Semiconductor, Inc.
Prabhakar Kushwaha422e2ab2013-01-14 18:26:57 +00004 */
5
6#include <common.h>
Simon Glass2dc9c342020-05-10 11:40:01 -06007#include <image.h>
Simon Glassa7b51302019-11-14 12:57:46 -07008#include <init.h>
Simon Glass274e0b02020-05-10 11:39:56 -06009#include <net.h>
Prabhakar Kushwaha422e2ab2013-01-14 18:26:57 +000010#include <asm/processor.h>
11#include <asm/mmu.h>
12#include <asm/cache.h>
13#include <asm/immap_85xx.h>
14#include <asm/io.h>
Simon Glass0af6e2d2019-08-01 09:46:52 -060015#include <env.h>
Prabhakar Kushwaha422e2ab2013-01-14 18:26:57 +000016#include <miiphy.h>
Masahiro Yamada75f82d02018-03-05 01:20:11 +090017#include <linux/libfdt.h>
Prabhakar Kushwaha422e2ab2013-01-14 18:26:57 +000018#include <fdt_support.h>
19#include <fsl_mdio.h>
20#include <tsec.h>
21#include <mmc.h>
22#include <netdev.h>
York Sun37562f62013-10-22 12:39:02 -070023#include <fsl_ifc.h>
Prabhakar Kushwaha422e2ab2013-01-14 18:26:57 +000024#include <hwconfig.h>
25#include <i2c.h>
York Sunf0626592013-09-30 09:22:09 -070026#include <fsl_ddr_sdram.h>
Ashish Kumar4fbbfaa2014-10-06 18:24:56 +053027#include <jffs2/load_kernel.h>
28#include <mtd_node.h>
29#include <flash.h>
Prabhakar Kushwaha422e2ab2013-01-14 18:26:57 +000030
31#ifdef CONFIG_PCI
32#include <pci.h>
33#include <asm/fsl_pci.h>
34#endif
35
36#include "../common/qixis.h"
37DECLARE_GLOBAL_DATA_PTR;
38
39
40int board_early_init_f(void)
41{
Jaiprakash Singhdd888062015-03-20 19:28:27 -070042 struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
Prabhakar Kushwaha422e2ab2013-01-14 18:26:57 +000043
Jaiprakash Singhdd888062015-03-20 19:28:27 -070044 setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
Prabhakar Kushwaha422e2ab2013-01-14 18:26:57 +000045
46 return 0;
47}
48
49void board_config_serdes_mux(void)
50{
51 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
52 u32 pordevsr = in_be32(&gur->pordevsr);
53 u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
54 MPC85xx_PORDEVSR_IO_SEL_SHIFT;
55
56 switch (srds_cfg) {
57 /* PEX(1) PEX(2) CPRI 2 CPRI 1 */
58 case 1:
59 case 2:
60 case 3:
61 case 4:
62 case 5:
63 case 22:
64 case 23:
65 case 24:
66 case 25:
67 case 26:
68 QIXIS_WRITE_I2C(brdcfg[4], 0x03);
69 break;
70
71 /* PEX(1) PEX(2) SGMII1 CPRI 1 */
72 case 6:
73 case 7:
74 case 8:
75 case 9:
76 case 10:
77 case 27:
78 case 28:
79 case 29:
80 case 30:
81 case 31:
82 QIXIS_WRITE_I2C(brdcfg[4], 0x01);
83 break;
84
85 /* PEX(1) PEX(2) SGMII1 SGMII2 */
86 case 11:
87 case 32:
88 QIXIS_WRITE_I2C(brdcfg[4], 0x00);
89 break;
90
91 /* PEX(1) SGMII2 CPRI 2 CPRI 1 */
92 case 12:
93 case 13:
94 case 14:
95 case 15:
96 case 16:
97 case 33:
98 case 34:
99 case 35:
100 case 36:
101 case 37:
102 QIXIS_WRITE_I2C(brdcfg[4], 0x07);
103 break;
104
105 /* PEX(1) SGMII2 SGMII1 CPRI 1 */
106 case 17:
107 case 18:
108 case 19:
109 case 20:
110 case 21:
111 case 38:
112 case 39:
113 case 40:
114 case 41:
115 case 42:
116 QIXIS_WRITE_I2C(brdcfg[4], 0x05);
117 break;
118
119 /* SGMII1 SGMII2 CPRI 2 CPRI 1 */
120 case 43:
121 case 44:
122 case 45:
123 case 46:
124 case 47:
125 QIXIS_WRITE_I2C(brdcfg[4], 0x0F);
126 break;
127
128
129 default:
130 break;
131 }
132}
133
Priyanka Jain3a502992013-07-02 09:22:23 +0530134/* Configure DSP DDR controller */
135void dsp_ddr_configure(void)
136{
137 /*
138 *There are separate DDR-controllers for DSP and PowerPC side DDR.
139 *copy the ddr controller settings from PowerPC side DDR controller
140 *to the DSP DDR controller as connected DDR memories are similar.
141 */
York Suna21803d2013-11-18 10:29:32 -0800142 struct ccsr_ddr __iomem *pa_ddr =
143 (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
144 struct ccsr_ddr temp_ddr;
145 struct ccsr_ddr __iomem *dsp_ddr =
146 (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR;
Priyanka Jain3a502992013-07-02 09:22:23 +0530147
York Suna21803d2013-11-18 10:29:32 -0800148 memcpy(&temp_ddr, pa_ddr, sizeof(struct ccsr_ddr));
Priyanka Jain3a502992013-07-02 09:22:23 +0530149 temp_ddr.cs0_bnds = CONFIG_SYS_DDR1_CS0_BNDS;
150 temp_ddr.sdram_cfg &= ~SDRAM_CFG_MEM_EN;
York Suna21803d2013-11-18 10:29:32 -0800151 memcpy(dsp_ddr, &temp_ddr, sizeof(struct ccsr_ddr));
Priyanka Jain3a502992013-07-02 09:22:23 +0530152 dsp_ddr->sdram_cfg |= SDRAM_CFG_MEM_EN;
153}
154
Prabhakar Kushwaha422e2ab2013-01-14 18:26:57 +0000155int board_early_init_r(void)
156{
Masahiro Yamada8cea9b52017-02-11 22:43:54 +0900157#ifdef CONFIG_MTD_NOR_FLASH
Prabhakar Kushwaha422e2ab2013-01-14 18:26:57 +0000158 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
York Sun220c3462014-06-24 21:16:20 -0700159 int flash_esel = find_tlb_idx((void *)flashbase, 1);
Prabhakar Kushwaha422e2ab2013-01-14 18:26:57 +0000160
161 /*
162 * Remap Boot flash region to caching-inhibited
163 * so that flash can be erased properly.
164 */
165
166 /* Flush d-cache and invalidate i-cache of any FLASH data */
167 flush_dcache();
168 invalidate_icache();
169
York Sun220c3462014-06-24 21:16:20 -0700170 if (flash_esel == -1) {
171 /* very unlikely unless something is messed up */
172 puts("Error: Could not find TLB for FLASH BASE\n");
173 flash_esel = 2; /* give our best effort to continue */
174 } else {
175 /* invalidate existing TLB entry for flash */
176 disable_tlb(flash_esel);
177 }
Prabhakar Kushwaha422e2ab2013-01-14 18:26:57 +0000178
179 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
180 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
181 0, flash_esel, BOOKE_PAGESZ_64M, 1);
182
183 set_tlb(1, flashbase + 0x4000000,
184 CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000,
185 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
186 0, flash_esel+1, BOOKE_PAGESZ_64M, 1);
187#endif
188 board_config_serdes_mux();
Priyanka Jain3a502992013-07-02 09:22:23 +0530189 dsp_ddr_configure();
Prabhakar Kushwaha422e2ab2013-01-14 18:26:57 +0000190 return 0;
191}
192
193#ifdef CONFIG_PCI
194void pci_init_board(void)
195{
196 fsl_pcie_init_board(0);
197}
198#endif /* ifdef CONFIG_PCI */
199
200int checkboard(void)
201{
202 struct cpu_type *cpu;
203 u8 sw;
204
Simon Glassa8b57392012-12-13 20:48:48 +0000205 cpu = gd->arch.cpu;
Prabhakar Kushwaha422e2ab2013-01-14 18:26:57 +0000206 printf("Board: %sQDS\n", cpu->name);
207
208 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x,\n",
209 QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver));
210
211 sw = QIXIS_READ(brdcfg[0]);
212 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
213
214 printf("IFC chip select:");
215 switch (sw) {
216 case 0:
217 printf("NOR\n");
218 break;
219 case 2:
220 printf("Promjet\n");
221 break;
222 case 4:
223 printf("NAND\n");
224 break;
225 default:
226 printf("Invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
227 break;
228 }
229
230 return 0;
231}
232
Prabhakar Kushwaha422e2ab2013-01-14 18:26:57 +0000233int board_eth_init(bd_t *bis)
234{
Bin Meng1e0e00a2016-01-11 22:41:12 -0800235#ifdef CONFIG_TSEC_ENET
Prabhakar Kushwaha422e2ab2013-01-14 18:26:57 +0000236 struct fsl_pq_mdio_info mdio_info;
237 struct tsec_info_struct tsec_info[4];
238 int num = 0;
239
240#ifdef CONFIG_TSEC1
241 SET_STD_TSEC_INFO(tsec_info[num], 1);
242 num++;
243
244#endif
245
246#ifdef CONFIG_TSEC2
247 SET_STD_TSEC_INFO(tsec_info[num], 2);
248 num++;
249#endif
250
251 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
252 mdio_info.name = DEFAULT_MII_NAME;
253
254 fsl_pq_mdio_init(bis, &mdio_info);
255 tsec_eth_init(bis, tsec_info, num);
Bin Meng1e0e00a2016-01-11 22:41:12 -0800256#endif
Prabhakar Kushwaha422e2ab2013-01-14 18:26:57 +0000257
258 #ifdef CONFIG_PCI
259 pci_eth_init(bis);
260 #endif
261
262 return 0;
263}
Prabhakar Kushwaha422e2ab2013-01-14 18:26:57 +0000264
265#define USBMUX_SEL_MASK 0xc0
266#define USBMUX_SEL_UART2 0xc0
267#define USBMUX_SEL_USB 0x40
268#define SPIMUX_SEL_UART3 0x80
269#define GPS_MUX_SEL_GPS 0x40
270
271#define TSEC_1588_CLKIN_MASK 0x03
272#define CON_XCVR_REF_CLK 0x00
273
274int misc_init_r(void)
275{
276 u8 val;
277 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
278 u32 porbmsr = in_be32(&gur->porbmsr);
Andy Fleming7cc7b772013-06-20 14:54:33 -0500279 u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
Prabhakar Kushwaha422e2ab2013-01-14 18:26:57 +0000280
281 /*Configure 1588 clock-in source from RF Card*/
282 val = QIXIS_READ_I2C(brdcfg[5]);
283 QIXIS_WRITE_I2C(brdcfg[5],
284 (val & ~(TSEC_1588_CLKIN_MASK)) | CON_XCVR_REF_CLK);
285
286 if (hwconfig("uart2") && hwconfig("usb1")) {
287 printf("UART2 and USB cannot work together on the board\n");
288 printf("Remove one from hwconfig and reset\n");
289 } else {
290 if (hwconfig("uart2")) {
291 val = QIXIS_READ_I2C(brdcfg[5]);
292 QIXIS_WRITE_I2C(brdcfg[5],
293 (val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_UART2);
294 clrbits_be32(&gur->pmuxcr3,
295 MPC85xx_PMUXCR3_USB_SEL_MASK);
296 setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART2_SEL);
297 } else {
298 /* By default USB should be selected.
299 * Programming FPGA to select USB. */
300 val = QIXIS_READ_I2C(brdcfg[5]);
301 QIXIS_WRITE_I2C(brdcfg[5],
302 (val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_USB);
303 }
304
305 }
306
307 if (hwconfig("sim")) {
308 if (romloc == PORBMSR_ROMLOC_NAND_2K ||
309 romloc == PORBMSR_ROMLOC_NOR ||
310 romloc == PORBMSR_ROMLOC_SPI) {
311
312 val = QIXIS_READ_I2C(brdcfg[3]);
313 QIXIS_WRITE_I2C(brdcfg[3], val|0x10);
314 clrbits_be32(&gur->pmuxcr,
315 MPC85xx_PMUXCR0_SIM_SEL_MASK);
316 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR0_SIM_SEL);
317 }
318 }
319
320 if (hwconfig("uart3")) {
321 if (romloc == PORBMSR_ROMLOC_NAND_2K ||
322 romloc == PORBMSR_ROMLOC_NOR ||
323 romloc == PORBMSR_ROMLOC_SDHC) {
324
325 /* UART3 and SPI1 (Flashes) are muxed together */
326 val = QIXIS_READ_I2C(brdcfg[3]);
327 QIXIS_WRITE_I2C(brdcfg[3], (val | SPIMUX_SEL_UART3));
328 clrbits_be32(&gur->pmuxcr3,
329 MPC85xx_PMUXCR3_UART3_SEL_MASK);
330 setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART3_SEL);
331
332 /* MUX to select UART3 connection to J24 header
333 * or to GPS */
334 val = QIXIS_READ_I2C(brdcfg[6]);
335 if (hwconfig("gps"))
336 QIXIS_WRITE_I2C(brdcfg[6],
337 (val | GPS_MUX_SEL_GPS));
338 else
339 QIXIS_WRITE_I2C(brdcfg[6],
340 (val & ~(GPS_MUX_SEL_GPS)));
341 }
342 }
343 return 0;
344}
345
346void fdt_del_node_compat(void *blob, const char *compatible)
347{
348 int err;
349 int off = fdt_node_offset_by_compatible(blob, -1, compatible);
350 if (off < 0) {
351 printf("WARNING: could not find compatible node %s: %s.\n",
352 compatible, fdt_strerror(off));
353 return;
354 }
355 err = fdt_del_node(blob, off);
356 if (err < 0) {
357 printf("WARNING: could not remove %s: %s.\n",
358 compatible, fdt_strerror(err));
359 }
360}
361
362#if defined(CONFIG_OF_BOARD_SETUP)
Ashish Kumar4fbbfaa2014-10-06 18:24:56 +0530363#ifdef CONFIG_FDT_FIXUP_PARTITIONS
Masahiro Yamada20ead6f2018-07-19 16:28:23 +0900364static const struct node_info nodes[] = {
Ashish Kumar4fbbfaa2014-10-06 18:24:56 +0530365 { "cfi-flash", MTD_DEV_TYPE_NOR, },
366 { "fsl,ifc-nand", MTD_DEV_TYPE_NAND, },
367};
368#endif
Simon Glass2aec3cc2014-10-23 18:58:47 -0600369int ft_board_setup(void *blob, bd_t *bd)
Prabhakar Kushwaha422e2ab2013-01-14 18:26:57 +0000370{
371 phys_addr_t base;
372 phys_size_t size;
373
374 ft_cpu_setup(blob, bd);
375
Simon Glassda1a1342017-08-03 12:22:15 -0600376 base = env_get_bootm_low();
377 size = env_get_bootm_size();
Prabhakar Kushwaha422e2ab2013-01-14 18:26:57 +0000378
379 #if defined(CONFIG_PCI)
380 FT_FSL_PCI_SETUP;
381 #endif
382
383 fdt_fixup_memory(blob, (u64)base, (u64)size);
Ashish Kumar4fbbfaa2014-10-06 18:24:56 +0530384#ifdef CONFIG_FDT_FIXUP_PARTITIONS
385 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
386#endif
Prabhakar Kushwaha422e2ab2013-01-14 18:26:57 +0000387
388 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
389 u32 porbmsr = in_be32(&gur->porbmsr);
Andy Fleming7cc7b772013-06-20 14:54:33 -0500390 u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
Prabhakar Kushwaha422e2ab2013-01-14 18:26:57 +0000391
392 if (!(hwconfig("uart2") && hwconfig("usb1"))) {
393 /* If uart2 is there in hwconfig remove usb node from
394 * device tree */
395
396 if (hwconfig("uart2")) {
397 /* remove dts usb node */
398 fdt_del_node_compat(blob, "fsl-usb2-dr");
399 } else {
Sriram Dash9fd465c2016-09-16 17:12:15 +0530400 fsl_fdt_fixup_dr_usb(blob, bd);
Prabhakar Kushwaha422e2ab2013-01-14 18:26:57 +0000401 fdt_del_node_and_alias(blob, "serial2");
402 }
403 }
404
405 if (hwconfig("uart3")) {
406 if (romloc == PORBMSR_ROMLOC_NAND_2K ||
407 romloc == PORBMSR_ROMLOC_NOR ||
408 romloc == PORBMSR_ROMLOC_SDHC)
409 /* Delete SPI node from the device tree */
410 fdt_del_node_and_alias(blob, "spi1");
411 } else
412 fdt_del_node_and_alias(blob, "serial3");
413
414 if (hwconfig("sim")) {
415 if (romloc == PORBMSR_ROMLOC_NAND_2K ||
416 romloc == PORBMSR_ROMLOC_NOR ||
417 romloc == PORBMSR_ROMLOC_SPI) {
418
419 /* remove dts sdhc node */
420 fdt_del_node_compat(blob, "fsl,esdhc");
421 } else if (romloc == PORBMSR_ROMLOC_SDHC) {
422
423 /* remove dts sim node */
424 fdt_del_node_compat(blob, "fsl,sim-v1.0");
425 printf("SIM & SDHC can't work together on the board");
426 printf("\nRemove sim from hwconfig and reset\n");
427 }
428 }
Simon Glass2aec3cc2014-10-23 18:58:47 -0600429
430 return 0;
Prabhakar Kushwaha422e2ab2013-01-14 18:26:57 +0000431}
432#endif