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git01.mediatek.com / filogic / uboot / c3dc99f2cd71c948a14f1baf6ee347ede220c525 / . / board / alliedtelesis / SBx81LIFXCAT / sbx81lifxcat.c
blob: e4bf507cc3f096871c2b93fb53c1b712285e166d [file] [log] [blame]
Chris Packhamc6408d12018-06-25 22:34:57 +1200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2010, 2018
4 * Allied Telesis <www.alliedtelesis.com>
5 */
6
7#include <common.h>
Simon Glass97589732020-05-10 11:40:02 -0600[diff] [blame]8#include <init.h>
Chris Packhamc6408d12018-06-25 22:34:57 +1200[diff] [blame]9#include <miiphy.h>
Simon Glass0c364412019-12-28 10:44:48 -0700[diff] [blame]10#include <net.h>
Chris Packhamc6408d12018-06-25 22:34:57 +1200[diff] [blame]11#include <netdev.h>
12#include <led.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -0600[diff] [blame]13#include <linux/bitops.h>
Chris Packhamc6408d12018-06-25 22:34:57 +1200[diff] [blame]14#include <linux/io.h>
15#include <asm/arch/cpu.h>
16#include <asm/arch/soc.h>
17#include <asm/arch/mpp.h>
18#include <asm/arch/gpio.h>
19
20#define SBX81LIFXCAT_OE_LOW (~0)
21#define SBX81LIFXCAT_OE_HIGH (~BIT(11))
22#define SBX81LIFXCAT_OE_VAL_LOW (0)
23#define SBX81LIFXCAT_OE_VAL_HIGH (BIT(11))
24
25DECLARE_GLOBAL_DATA_PTR;
26
27int board_early_init_f(void)
28{
29 /*
30 * default gpio configuration
31 * There are maximum 64 gpios controlled through 2 sets of registers
32 * the below configuration configures mainly initial LED status
33 */
34 mvebu_config_gpio(SBX81LIFXCAT_OE_VAL_LOW,
35 SBX81LIFXCAT_OE_VAL_HIGH,
36 SBX81LIFXCAT_OE_LOW, SBX81LIFXCAT_OE_HIGH);
37
38 /* Multi-Purpose Pins Functionality configuration */
39 static const u32 kwmpp_config[] = {
40 MPP0_SPI_SCn,
41 MPP1_SPI_MOSI,
42 MPP2_SPI_SCK,
43 MPP3_SPI_MISO,
44 MPP4_NF_IO6,
45 MPP5_NF_IO7,
46 MPP6_SYSRST_OUTn,
47 MPP7_GPO,
48 MPP8_TW_SDA,
49 MPP9_TW_SCK,
50 MPP10_UART0_TXD,
51 MPP11_UART0_RXD,
52 MPP12_GPO,
53 MPP13_UART1_TXD,
54 MPP14_UART1_RXD,
55 MPP15_GPIO,
56 MPP16_GPIO,
57 MPP17_GPIO,
58 MPP18_NF_IO0,
59 MPP19_NF_IO1,
60 MPP20_GE1_0,
61 MPP21_GE1_1,
62 MPP22_GE1_2,
63 MPP23_GE1_3,
64 MPP24_GE1_4,
65 MPP25_GE1_5,
66 MPP26_GE1_6,
67 MPP27_GE1_7,
68 MPP28_GE1_8,
69 MPP29_GE1_9,
70 MPP30_GE1_10,
71 MPP31_GE1_11,
72 MPP32_GE1_12,
73 MPP33_GE1_13,
74 MPP34_GPIO,
75 MPP35_GPIO,
76 MPP36_GPIO,
77 MPP37_GPIO,
78 MPP38_GPIO,
79 MPP39_GPIO,
80 MPP40_GPIO,
81 MPP41_GPIO,
82 MPP42_GPIO,
83 MPP43_GPIO,
84 MPP44_GPIO,
85 MPP45_GPIO,
86 MPP46_GPIO,
87 MPP47_GPIO,
88 MPP48_GPIO,
89 MPP49_GPIO,
90 0
91 };
92
93 kirkwood_mpp_conf(kwmpp_config, NULL);
94 return 0;
95}
96
97int board_init(void)
98{
99 /* address of boot parameters */
100 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
101
102 return 0;
103}
104
105#ifdef CONFIG_RESET_PHY_R
106/* automatically defined by kirkwood config.h */
107void reset_phy(void)
108{
109}
110#endif
111
112#ifdef CONFIG_MV88E61XX_SWITCH
113int mv88e61xx_hw_reset(struct phy_device *phydev)
114{
115 phydev->advertising = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
116
117 return 0;
118}
119#endif
120
121#ifdef CONFIG_MISC_INIT_R
122int misc_init_r(void)
123{
124 struct udevice *dev;
125 int ret;
126
127 ret = led_get_by_label("status:ledp", &dev);
128 if (!ret)
129 led_set_state(dev, LEDST_ON);
130
131 ret = led_get_by_label("status:ledn", &dev);
132 if (!ret)
133 led_set_state(dev, LEDST_OFF);
134
135 return 0;
136}
137#endif