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git01.mediatek.com / filogic / uboot / c3dc99f2cd71c948a14f1baf6ee347ede220c525 / . / arch / arm / dts / imx8mm-verdin.dts
blob: b86f46e03eb4287d1e9c92e532dc51d49936df15 [file] [log] [blame]
Igor Opaniuk309e65b2020-01-28 14:42:25 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2/*
3 * Copyright 2020 Toradex
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/usb/pd.h>
9#include "imx8mm.dtsi"
10
11/ {
12 model = "Toradex Verdin iMX8M Mini Quad/DualLite";
13 compatible = "toradex,verdin-imx8mm", "fsl,imx8mm";
14
15 chosen {
16 stdout-path = &uart1;
17 };
18
19 /* fixed clock dedicated to SPI CAN controller */
20 clk20m: oscillator {
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
23 clock-frequency = <20000000>;
24 };
25
26 reg_ethphy: regulator-ethphy {
27 compatible = "regulator-fixed";
28 enable-active-high;
29 gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>;
30 off-on-delay = <500000>;
31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_reg_eth>;
33 regulator-boot-on;
34 regulator-max-microvolt = <3300000>;
35 regulator-min-microvolt = <3300000>;
36 regulator-name = "V3.3_ETH";
37 startup-delay-us = <200000>;
38 };
39
40 reg_usb_otg1_vbus: regulator-usb-otg1 {
41 compatible = "regulator-fixed";
42 enable-active-high;
43 /* Verdin USB1_EN */
44 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
45 pinctrl-names = "default";
46 pinctrl-0 = <&pinctrl_reg_usb1_en>;
47 regulator-name = "usb_otg1_vbus";
48 regulator-min-microvolt = <5000000>;
49 regulator-max-microvolt = <5000000>;
50 };
51
52 reg_usb_otg2_vbus: regulator-usb-otg2 {
53 compatible = "regulator-fixed";
54 enable-active-high;
55 /* Verdin USB2_EN */
56 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
57 pinctrl-names = "default";
58 pinctrl-0 = <&pinctrl_reg_usb2_en>;
59 regulator-name = "usb_otg2_vbus";
60 regulator-min-microvolt = <5000000>;
61 regulator-max-microvolt = <5000000>;
62 };
63
64 reg_usdhc2_vmmc: regulator-usdhc2 {
65 compatible = "regulator-fixed";
66 enable-active-high;
67 gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
68 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
70 regulator-name = "V3.3_SD";
71 regulator-min-microvolt = <3300000>;
72 regulator-max-microvolt = <3300000>;
73 startup-delay-us = <2000>;
74 };
75
76 reg_wifi_en: regulator-wifi-en {
77 compatible = "regulator-fixed";
78 enable-active-high;
79 gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>;
80 pinctrl-names = "default";
81 pinctrl-0 = <&pinctrl_wifi_pwr_en>;
82 regulator-name = "V3.3_WI-FI";
83 regulator-min-microvolt = <3300000>;
84 regulator-max-microvolt = <3300000>;
85 startup-delay-us = <2000>;
86 };
87};
88
89&A53_0 {
90 arm-supply = <&buck2_reg>;
91};
92
93&clk {
94 assigned-clocks = <&clk IMX8MM_AUDIO_PLL1>, <&clk IMX8MM_AUDIO_PLL2>;
95 assigned-clock-rates = <786432000>, <722534400>;
96};
97
98/* Verdin SPI_1 */
99&ecspi2 {
100 #address-cells = <1>;
101 #size-cells = <0>;
102 pinctrl-names = "default";
103 pinctrl-0 = <&pinctrl_ecspi2>;
104 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
105 status = "okay";
106
107 spidev20: spidev@0 {
108 compatible = "toradex,evalspi";
109 reg = <0>;
110 spi-max-frequency = <10000000>;
111 status = "okay";
112 };
113};
114
115/* On-module CAN controller 1 & 2 */
116&ecspi3 {
117 #address-cells = <1>;
118 #size-cells = <0>;
119 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>,
120 <&gpio1 5 GPIO_ACTIVE_LOW>;
121 /* This property is required, even if marked as obsolete in the doku */
122 fsl,spi-num-chipselects = <2>;
123 pinctrl-names = "default";
124 pinctrl-0 = <&pinctrl_ecspi3>;
125 status = "okay";
126
127 can1: can@0 {
128 compatible = "microchip,mcp2517fd";
129 clocks = <&clk20m>;
130 gpio-controller;
131 interrupt-parent = <&gpio1>;
132 interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
133 microchip,clock-allways-on;
134 microchip,clock-out-div = <1>;
135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_can1_int>;
137 reg = <0>;
138 spi-max-frequency = <2000000>;
139 };
140
141 can2: can@1 {
142 compatible = "microchip,mcp2517fd";
143 clocks = <&clk20m>;
144 gpio-controller;
145 interrupt-parent = <&gpio1>;
146 interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
147 pinctrl-names = "default";
148 pinctrl-0 = <&pinctrl_can2_int>;
149 reg = <1>;
150 spi-max-frequency = <2000000>;
151 };
152};
153
154&fec1 {
155 fsl,magic-packet;
Igor Opaniuk309e65b2020-01-28 14:42:25 +0100[diff] [blame]156 phy-handle = <&ethphy0>;
157 phy-mode = "rgmii";
158 phy-supply = <&reg_ethphy>;
159 pinctrl-names = "default", "sleep";
160 pinctrl-0 = <&pinctrl_fec1>;
161 pinctrl-1 = <&pinctrl_fec1_sleep>;
162 status = "okay";
163
164 mdio {
165 #address-cells = <1>;
166 #size-cells = <0>;
167
168 ethphy0: ethernet-phy@7 {
169 compatible = "ethernet-phy-ieee802.3-c22";
170 interrupt-parent = <&gpio1>;
171 interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
172 micrel,led-mode = <0>;
173 reg = <7>;
174 };
175 };
176};
177
178&gpio4 {
179 /*
180 * The SE050 security element may be driven via I2C from user space.
181 * The element itself is enabled here as it has no kernel driver.
182 */
183 se050_ena {
184 gpio-hog;
185 gpios = <19 GPIO_ACTIVE_HIGH>;
186 line-name = "SE050_ENABLE";
187 output-high;
188 pinctrl-names = "default";
189 pinctrl-0 = <&pinctrl_se050_ena>;
190 };
191};
192
193/* On-module I2C */
194&i2c1 {
195 clock-frequency = <400000>;
196 pinctrl-names = "default";
197 pinctrl-0 = <&pinctrl_i2c1>;
198 status = "okay";
199
200 pmic@4b {
201 compatible = "rohm,bd71840", "rohm,bd71837";
202 bd71837,pmic-buck2-uses-i2c-dvs;
203 bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */
204 gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
205 /* PMIC BD71837 PMIC_nINT GPIO1_IO3 */
206 pinctrl-0 = <&pinctrl_pmic>;
207 reg = <0x4b>;
208
209 gpo {
210 rohm,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */
211 };
212
213 regulators {
214 buck1_reg: BUCK1 {
215 regulator-always-on;
216 regulator-boot-on;
217 regulator-compatible = "buck1";
218 regulator-max-microvolt = <1300000>;
219 regulator-min-microvolt = <700000>;
220 regulator-ramp-delay = <1250>;
221 };
222
223 buck2_reg: BUCK2 {
224 regulator-always-on;
225 regulator-boot-on;
226 regulator-compatible = "buck2";
227 regulator-max-microvolt = <1300000>;
228 regulator-min-microvolt = <700000>;
229 regulator-ramp-delay = <1250>;
230 };
231
232 buck5_reg: BUCK5 {
233 regulator-always-on;
234 regulator-boot-on;
235 regulator-compatible = "buck5";
236 regulator-max-microvolt = <1350000>;
237 regulator-min-microvolt = <700000>;
238 };
239
240 buck6_reg: BUCK6 {
241 regulator-always-on;
242 regulator-boot-on;
243 regulator-compatible = "buck6";
244 regulator-max-microvolt = <3300000>;
245 regulator-min-microvolt = <3000000>;
246 };
247
248 buck7_reg: BUCK7 {
249 regulator-always-on;
250 regulator-boot-on;
251 regulator-compatible = "buck7";
252 regulator-max-microvolt = <1995000>;
253 regulator-min-microvolt = <1605000>;
254 };
255
256 buck8_reg: BUCK8 {
257 regulator-always-on;
258 regulator-boot-on;
259 regulator-compatible = "buck8";
260 regulator-max-microvolt = <1400000>;
261 regulator-min-microvolt = <800000>;
262 };
263
264 ldo1_reg: LDO1 {
265 regulator-always-on;
266 regulator-boot-on;
267 regulator-compatible = "ldo1";
268 regulator-max-microvolt = <3300000>;
269 regulator-min-microvolt = <3000000>;
270 };
271
272 ldo2_reg: LDO2 {
273 regulator-always-on;
274 regulator-boot-on;
275 regulator-compatible = "ldo2";
276 regulator-max-microvolt = <900000>;
277 regulator-min-microvolt = <900000>;
278 };
279
280 ldo3_reg: LDO3 {
281 regulator-always-on;
282 regulator-boot-on;
283 regulator-compatible = "ldo3";
284 regulator-max-microvolt = <3300000>;
285 regulator-min-microvolt = <1800000>;
286 };
287
288 ldo4_reg: LDO4 {
289 regulator-always-on;
290 regulator-boot-on;
291 regulator-compatible = "ldo4";
292 regulator-max-microvolt = <1800000>;
293 regulator-min-microvolt = <900000>;
294 };
295
296 ldo5_reg: LDO5 {
297 regulator-compatible = "ldo5";
298 regulator-max-microvolt = <3300000>;
299 regulator-min-microvolt = <3300000>;
300 };
301
302 ldo6_reg: LDO6 {
303 regulator-always-on;
304 regulator-boot-on;
305 regulator-compatible = "ldo6";
306 regulator-max-microvolt = <1800000>;
307 regulator-min-microvolt = <900000>;
308 };
309 };
310 };
311
312 /* Epson RX8130 real time clock on carrier board */
313 rtc@32 {
314 compatible = "epson,rx8130";
315 reg = <0x32>;
316 };
317
318 adc@34 {
319 compatible = "maxim,max11607";
320 reg = <0x34>;
321 vcc-supply = <&ldo5_reg>;
322 };
323
324 eeprom@50 {
325 compatible = "st,24c02";
326 pagesize = <16>;
327 reg = <0x50>;
328 };
329};
330
331/* Verdin I2C_2_DSI */
332&i2c2 {
333 clock-frequency = <10000>;
334 pinctrl-names = "default";
335 pinctrl-0 = <&pinctrl_i2c2>;
336 status = "okay";
337};
338
339/* Verdin I2C_3_HDMI N/A */
340
341/* Verdin I2C_4_CSI */
342&i2c3 {
343 clock-frequency = <400000>;
344 pinctrl-names = "default";
345 pinctrl-0 = <&pinctrl_i2c3>;
346 status = "okay";
347};
348
349/* Verdin I2C_1 */
350&i2c4 {
351 clock-frequency = <400000>;
352 pinctrl-names = "default";
353 pinctrl-0 = <&pinctrl_i2c4>;
354 status = "okay";
355
356 /* Audio Codec */
357 wm8904_1a: codec@1a {
358 compatible = "wlf,wm8904";
359 #sound-dai-cells = <0>;
360 clocks = <&clk IMX8MM_CLK_SAI2_ROOT>;
361 clock-names = "mclk";
362 reg = <0x1a>;
363 };
364
365 gpio_expander_21: gpio-expander@21 {
366 compatible = "nxp,pcal6416";
367 #gpio-cells = <2>;
368 gpio-controller;
369 reg = <0x21>;
370 };
371
372 /* Current measurement into module VCC */
373 hwmon@40 {
374 compatible = "ti,ina219";
375 reg = <0x40>;
376 shunt-resistor = <10000>;
377 status = "okay";
378 };
379
380 /* EEPROM on MIPI-DSI to HDMI adapter */
381 eeprom_50: eeprom@50 {
382 compatible = "st,24c02";
383 pagesize = <16>;
384 reg = <0x50>;
385 };
386
387 /* EEPROM on Verdin Development board */
388 eeprom_57: eeprom@57 {
389 compatible = "st,24c02";
390 pagesize = <16>;
391 reg = <0x57>;
392 };
393};
394
395/* Verdin PWM_3_DSI */
396&pwm1 {
397 pinctrl-names = "default";
398 pinctrl-0 = <&pinctrl_pwm_1>;
399 #pwm-cells = <3>;
400 status = "okay";
401};
402
403/* Verdin PWM_1 */
404&pwm2 {
405 pinctrl-names = "default";
406 pinctrl-0 = <&pinctrl_pwm_2>;
407 #pwm-cells = <3>;
408 status = "okay";
409};
410
411/* Verdin PWM_2 */
412&pwm3 {
413 pinctrl-names = "default";
414 pinctrl-0 = <&pinctrl_pwm_3>;
415 #pwm-cells = <3>;
416 status = "okay";
417};
418
419/* Verdin UART_3, Console/Debug UART */
420&uart1 {
421 fsl,uart-has-rtscts;
422 pinctrl-names = "default";
423 pinctrl-0 = <&pinctrl_uart1>;
424 status = "okay";
425};
426
427/* Verdin UART_1 */
428&uart2 {
429 pinctrl-names = "default";
430 pinctrl-0 = <&pinctrl_uart2>;
431 fsl,uart-has-rtscts;
432 status = "okay";
433};
434
435/* Verdin UART_2 */
436&uart3 {
437 pinctrl-names = "default";
438 pinctrl-0 = <&pinctrl_uart3>;
439 fsl,uart-has-rtscts;
440 status = "okay";
441};
442
443/* Verdin UART_4 */
444/*
445 * resource allocated to M4 by default, must not be accessed from A-35 or you
446 * get an OOPS
447 */
448&uart4 {
449 pinctrl-names = "default";
450 pinctrl-0 = <&pinctrl_uart4>;
451 status = "disabled";
452};
453
454/* Verdin USB_1 */
455&usbotg1 {
456 dr_mode = "otg";
457 picophy,dc-vol-level-adjust = <7>;
458 picophy,pre-emp-curr-control = <3>;
459 vbus-supply = <&reg_usb_otg1_vbus>;
460 status = "okay";
461};
462
463/* Verdin USB_2 */
464&usbotg2 {
465 dr_mode = "host";
466 picophy,dc-vol-level-adjust = <7>;
467 picophy,pre-emp-curr-control = <3>;
468 vbus-supply = <&reg_usb_otg2_vbus>;
469 status = "okay";
470};
471
472/* On-module eMMC */
473&usdhc1 {
474 bus-width = <8>;
475 keep-power-in-suspend;
476 non-removable;
477 pinctrl-names = "default", "state_100mhz", "state_200mhz";
478 pinctrl-0 = <&pinctrl_usdhc1>;
479 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
480 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
481 pm-ignore-notify;
482 status = "okay";
483 /* TODO Strobe */
484};
485
486/* Verdin SD_1 */
487&usdhc2 {
488 bus-width = <4>;
489 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
490 pinctrl-names = "default", "state_100mhz", "state_200mhz";
491 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;
492 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
493 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
494 vmmc-supply = <&reg_usdhc2_vmmc>;
495 status = "okay";
496};
497
498/* On-module Wi-Fi */
499&usdhc3 {
500 bus-width = <4>;
501 non-removable;
502 pinctrl-names = "default", "state_100mhz", "state_200mhz";
503 pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_wifi_ctrl>;
504 pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_wifi_ctrl>;
505 pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_wifi_ctrl>;
506 vmmc-supply = <&reg_wifi_en>;
507 status = "okay";
508};
509
510&wdog1 {
511 fsl,ext-reset-output;
512 pinctrl-names = "default";
513 pinctrl-0 = <&pinctrl_wdog>;
514 status = "okay";
515};
516
517&iomuxc {
518 pinctrl-names = "default";
519 pinctrl-0 = <&pinctrl_dsi_bkl_en>, <&pinctrl_gpio1>, <&pinctrl_gpio2>,
520 <&pinctrl_gpio3>, <&pinctrl_gpio4>, <&pinctrl_gpio5>,
521 <&pinctrl_gpio6>, <&pinctrl_gpio7>, <&pinctrl_gpio8>,
522 <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>,
523 <&pinctrl_gpio_hog3>, <&pinctrl_gpio_hpd>;
524
525 pinctrl_can1_int: can1intgrp {
526 fsl,pins = <
527 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x1c4
528 >;
529 };
530
531 pinctrl_can2_int: can2intgrp {
532 fsl,pins = <
533 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x1c4
534 >;
535 };
536
537 pinctrl_ctrl_force_off_moci: ctrlforceoffgrp {
538 fsl,pins = <
539 MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x1c4 /* SODIMM 250 */
540 >;
541 };
542
543 pinctrl_dsi_bkl_en: dsi_bkl_en {
544 fsl,pins = <
545 MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x1c4 /* SODIMM 21 */
546 >;
547 };
548
549 pinctrl_ecspi2: ecspi2grp {
550 fsl,pins = <
551 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x1c4 /* SODIMM 198 */
552 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x4 /* SODIMM 200 */
553 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x4 /* SODIMM 196 */
554 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x1c4 /* SODIMM 202 */
555 >;
556 };
557
558 pinctrl_ecspi3: ecspi3grp {
559 fsl,pins = <
560 MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x1c4
561 MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x4
562 MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x4
563 MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x1c4
564 MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x1c4
565 >;
566 };
567
568 pinctrl_fec1: fec1grp {
569 fsl,pins = <
570 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
571 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
572 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
573 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
574 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
575 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
576 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
577 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
578 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
579 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
580 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
581 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
582 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
583 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
584 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x1c4
585 >;
586 };
587
588 pinctrl_fec1_sleep: fec1-sleepgrp {
589 fsl,pins = <
590 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
591 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
592 MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x1f
593 MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x1f
594 MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x1f
595 MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x1f
596 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
597 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
598 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
599 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
600 MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x1f
601 MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x1f
602 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
603 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
604 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x184
605 >;
606 };
607
608 pinctrl_flexspi0: flexspi0grp {
609 fsl,pins = <
610 MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 /* SODIMM 52 */
611 MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 /* SODIMM 54 */
612 MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x82 /* SODIMM 64 */
613 MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 /* SODIMM 56 */
614 MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 /* SODIMM 58 */
615 MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 /* SODIMM 60 */
616 MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 /* SODIMM 62 */
617 MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x82 /* SODIMM 66 */
618 >;
619 };
620
621 /* (MEZ_)GPIO_1 shared with (MEZ_)DSI_1_INT# on Verdin Development Board */
622 pinctrl_gpio1: gpio1grp {
623 fsl,pins = <
624 MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x184 /* SODIMM 206 */
625 >;
626 };
627
628 pinctrl_gpio2: gpio2grp {
629 fsl,pins = <
630 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x184 /* SODIMM 208 */
631 >;
632 };
633
634 pinctrl_gpio3: gpio3grp {
635 fsl,pins = <
636 MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x184 /* SODIMM 210 */
637 >;
638 };
639
640 pinctrl_gpio4: gpio4grp {
641 fsl,pins = <
642 MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x184 /* SODIMM 212 */
643 >;
644 };
645
646 pinctrl_gpio5: gpio5grp {
647 fsl,pins = <
648 MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x184 /* SODIMM 216 */
649 >;
650 };
651
652 pinctrl_gpio6: gpio6grp {
653 fsl,pins = <
654 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x184 /* SODIMM 218 */
655 >;
656 };
657
658 pinctrl_gpio7: gpio7grp {
659 fsl,pins = <
660 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x184 /* SODIMM 220 */
661 >;
662 };
663
664 pinctrl_gpio8: gpio8grp {
665 fsl,pins = <
666 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x184 /* SODIMM 222 */
667 >;
668 };
669
670 pinctrl_gpio_hog1: gpiohog1grp {
671 fsl,pins = <
672 MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1c4 /* SODIMM 88 */
673 MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x1c4 /* SODIMM 90 */
674 MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x1c4 /* SODIMM 92 */
675 MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x1c4 /* SODIMM 94 */
676 MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x1c4 /* SODIMM 96 */
677 MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x1c4 /* SODIMM 100 */
678 MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x1c4 /* SODIMM 102 */
679 MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x1c4 /* SODIMM 104 */
680 MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x1c4 /* SODIMM 106 */
681 MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x1c4 /* SODIMM 108 */
682 MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x1c4 /* SODIMM 112 */
683 MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x1c4 /* SODIMM 114 */
684 MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x1c4 /* SODIMM 116 */
685 MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1c4 /* SODIMM 118 */
686 MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x1c4 /* SODIMM 120 */
687 >;
688 };
689
690 pinctrl_gpio_hog2: gpiohog2grp {
691 fsl,pins = <
692 MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1c4 /* SODIMM 91 */
693 >;
694 };
695
696 pinctrl_gpio_hog3: gpiohog3grp {
697 fsl,pins = <
698 MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x1c4 /* SODIMM 157 */
699 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 /* SODIMM 187 */
700 >;
701 };
702
703 /* (MEZ_)DSI_1_INT# shared with (MEZ_)GPIO_1 on Verdin Development Board */
704 pinctrl_gpio_hpd: gpiohpdgrp {
705 fsl,pins = <
706 MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x184 /* SODIMM 17 */
707 >;
708 };
709
710 /* On-module I2C */
711 pinctrl_i2c1: i2c1grp {
712 fsl,pins = <
713 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c6
714 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c6
715 >;
716 };
717
718 /* Verdin I2C_4_CSI */
719 pinctrl_i2c2: i2c2grp {
720 fsl,pins = <
721 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c6 /* SODIMM 55 */
722 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c6 /* SODIMM 53 */
723 >;
724 };
725
726 /* Verdin I2C_2_DSI */
727 pinctrl_i2c3: i2c3grp {
728 fsl,pins = <
729 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c6 /* SODIMM 95 */
730 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c6 /* SODIMM 93 */
731 >;
732 };
733
734 /* Verdin I2C_1 */
735 pinctrl_i2c4: i2c4grp {
736 fsl,pins = <
737 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c6 /* SODIMM 14 */
738 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c6 /* SODIMM 12 */
739 >;
740 };
741
742 pinctrl_pcie0: pcie0grp {
743 fsl,pins = <
744 MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x6 /* SODIMM 244 */
745 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x6 /* PMIC_EN_PCIe_CLK */
746 >;
747 };
748
749 pinctrl_pmic: pmicirqgrp {
750 fsl,pins = <
751 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
752 >;
753 };
754
755 pinctrl_pwm_1: pwm1grp {
756 fsl,pins = <
757 MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6 /* SODIMM 19 */
758 >;
759 };
760
761 pinctrl_pwm_2: pwm2grp {
762 fsl,pins = <
763 MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x6 /* SODIMM 15 */
764 >;
765 };
766
767 pinctrl_pwm_3: pwm3grp {
768 fsl,pins = <
769 MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x6 /* SODIMM 16 */
770 >;
771 };
772
773 pinctrl_reg_eth: regethgrp {
774 fsl,pins = <
775 MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x184
776 >;
777 };
778
779 pinctrl_reg_usb1_en: regusb1engrp {
780 fsl,pins = <
781 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x184 /* SODIMM 155 */
782 >;
783 };
784
785 pinctrl_reg_usb2_en: regusb2engrp {
786 fsl,pins = <
787 MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x184 /* SODIMM 185 */
788 >;
789 };
790
791 pinctrl_sai2: sai2grp {
792 fsl,pins = <
793 MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 /* SODIMM 38 */
794 MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 /* SODIMM 36 */
795 MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 /* SODIMM 30 */
796 MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 /* SODIMM 34 */
797 MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 /* SODIMM 32 */
798 >;
799 };
800
801 pinctrl_sai5: sai5grp {
802 fsl,pins = <
803 MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 /* SODIMM 48 */
804 MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6 /* SODIMM 44 */
805 MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6 /* SODIMM 42 */
806 MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6 /* SODIMM 46 */
807 >;
808 };
809
810 pinctrl_se050_ena: se050enagrp {
811 fsl,pins = <
812 MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x184
813 >;
814 };
815
816 pinctrl_uart1: uart1grp {
817 fsl,pins = <
818 MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x1c4 /* SODIMM 147 */
819 MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x1c4 /* SODIMM 149 */
820 >;
821 };
822
823 pinctrl_uart2: uart2grp {
824 fsl,pins = <
825 MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x1c4 /* SODIMM 133 */
826 MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x1c4 /* SODIMM 135 */
827 MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x1c4 /* SODIMM 131 */
828 MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x1c4 /* SODIMM 129 */
829 >;
830 };
831
832 pinctrl_uart3: uart3grp {
833 fsl,pins = <
834 MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1c4 /* SODIMM 141 */
835 MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1c4 /* SODIMM 139 */
836 MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1c4 /* SODIMM 137 */
837 MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x1c4 /* SODIMM 143 */
838 >;
839 };
840
841 pinctrl_uart4: uart4grp {
842 fsl,pins = <
843 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x1c4 /* SODIMM 151 */
844 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x1c4 /* SODIMM 153 */
845 >;
846 };
847
848 pinctrl_usdhc1: usdhc1grp {
849 fsl,pins = <
850 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
851 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
852 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
853 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
854 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
855 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
856 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0
857 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0
858 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0
859 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0
860 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190
861 >;
862 };
863
864 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
865 fsl,pins = <
866 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
867 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
868 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
869 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
870 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
871 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
872 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4
873 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4
874 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4
875 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4
876 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194
877 >;
878 };
879
880 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
881 fsl,pins = <
882 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
883 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
884 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
885 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
886 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
887 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
888 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6
889 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6
890 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6
891 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6
892 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196
893 >;
894 };
895
896 pinctrl_usdhc2_cd: usdhc2cdgrp {
897 fsl,pins = <
898 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 /* SODIMM 84 */
899 >;
900 };
901
902 pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {
903 fsl,pins = <
904 MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x184 /* SODIMM 76 */
905 >;
906 };
907
908 pinctrl_usdhc2: usdhc2grp {
909 fsl,pins = <
910 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
911 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 /* SODIMM 78 */
912 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 /* SODIMM 74 */
913 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 /* SODIMM 80 */
914 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 /* SODIMM 82 */
915 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 /* SODIMM 70 */
916 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 /* SODIMM 72 */
917 >;
918 };
919
920 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
921 fsl,pins = <
922 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
923 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
924 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
925 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
926 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
927 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
928 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
929 >;
930 };
931
932 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
933 fsl,pins = <
934 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
935 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
936 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
937 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
938 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
939 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
940 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
941 >;
942 };
943
944 pinctrl_usdhc3: usdhc3grp {
945 fsl,pins = <
946 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
947 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
948 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
949 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
950 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
951 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
952 >;
953 };
954
955 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
956 fsl,pins = <
957 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
958 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
959 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
960 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
961 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
962 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
963 >;
964 };
965
966 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
967 fsl,pins = <
968 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
969 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
970 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
971 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
972 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
973 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
974 >;
975 };
976
977 pinctrl_wdog: wdoggrp {
978 fsl,pins = <
979 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
980 >;
981 };
982
983 pinctrl_wifi_ctrl: wifictrlgrp {
984 fsl,pins = <
985 MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x1c4 /* WIFI_WKUP_BT */
986 MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x1c4 /* WIFI_W_WKUP_HOST */
987 MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x1c4 /* WIFI_WKUP_WLAN */
988 >;
989 };
990
991 pinctrl_wifi_i2s: wifii2sgrp {
992 fsl,pins = <
993 MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0xd6
994 MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0xd6
995 MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0xd6
996 MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0xd6
997 >;
998 };
999
1000 pinctrl_wifi_pwr_en: wifipwrengrp {
1001 fsl,pins = <
1002 MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x184 /* PMIC_EN_WIFI */
1003 >;
1004 };
1005};