| Suman Anna | 7e0cfeb | 2022-05-25 13:38:46 +0530 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Device Tree Source for AM625 SoC family in Quad core configuration |
| 4 | * |
| 5 | * TRM: https://www.ti.com/lit/pdf/spruiv7 |
| 6 | * |
| 7 | * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ |
| 8 | */ |
| 9 | |
| 10 | /dts-v1/; |
| 11 | |
| 12 | #include "k3-am62.dtsi" |
| 13 | |
| 14 | / { |
| 15 | cpus { |
| 16 | #address-cells = <1>; |
| 17 | #size-cells = <0>; |
| 18 | |
| 19 | cpu-map { |
| 20 | cluster0: cluster0 { |
| 21 | core0 { |
| 22 | cpu = <&cpu0>; |
| 23 | }; |
| 24 | |
| 25 | core1 { |
| 26 | cpu = <&cpu1>; |
| 27 | }; |
| 28 | |
| 29 | core2 { |
| 30 | cpu = <&cpu2>; |
| 31 | }; |
| 32 | |
| 33 | core3 { |
| 34 | cpu = <&cpu3>; |
| 35 | }; |
| 36 | }; |
| 37 | }; |
| 38 | |
| 39 | cpu0: cpu@0 { |
| 40 | compatible = "arm,cortex-a53"; |
| 41 | reg = <0x000>; |
| 42 | device_type = "cpu"; |
| 43 | enable-method = "psci"; |
| 44 | i-cache-size = <0x8000>; |
| 45 | i-cache-line-size = <64>; |
| 46 | i-cache-sets = <256>; |
| 47 | d-cache-size = <0x8000>; |
| 48 | d-cache-line-size = <64>; |
| 49 | d-cache-sets = <128>; |
| 50 | next-level-cache = <&L2_0>; |
| 51 | }; |
| 52 | |
| 53 | cpu1: cpu@1 { |
| 54 | compatible = "arm,cortex-a53"; |
| 55 | reg = <0x001>; |
| 56 | device_type = "cpu"; |
| 57 | enable-method = "psci"; |
| 58 | i-cache-size = <0x8000>; |
| 59 | i-cache-line-size = <64>; |
| 60 | i-cache-sets = <256>; |
| 61 | d-cache-size = <0x8000>; |
| 62 | d-cache-line-size = <64>; |
| 63 | d-cache-sets = <128>; |
| 64 | next-level-cache = <&L2_0>; |
| 65 | }; |
| 66 | |
| 67 | cpu2: cpu@2 { |
| 68 | compatible = "arm,cortex-a53"; |
| 69 | reg = <0x002>; |
| 70 | device_type = "cpu"; |
| 71 | enable-method = "psci"; |
| 72 | i-cache-size = <0x8000>; |
| 73 | i-cache-line-size = <64>; |
| 74 | i-cache-sets = <256>; |
| 75 | d-cache-size = <0x8000>; |
| 76 | d-cache-line-size = <64>; |
| 77 | d-cache-sets = <128>; |
| 78 | next-level-cache = <&L2_0>; |
| 79 | }; |
| 80 | |
| 81 | cpu3: cpu@3 { |
| 82 | compatible = "arm,cortex-a53"; |
| 83 | reg = <0x003>; |
| 84 | device_type = "cpu"; |
| 85 | enable-method = "psci"; |
| 86 | i-cache-size = <0x8000>; |
| 87 | i-cache-line-size = <64>; |
| 88 | i-cache-sets = <256>; |
| 89 | d-cache-size = <0x8000>; |
| 90 | d-cache-line-size = <64>; |
| 91 | d-cache-sets = <128>; |
| 92 | next-level-cache = <&L2_0>; |
| 93 | }; |
| 94 | }; |
| 95 | |
| 96 | L2_0: l2-cache0 { |
| 97 | compatible = "cache"; |
| 98 | cache-level = <2>; |
| 99 | cache-size = <0x40000>; |
| 100 | cache-line-size = <64>; |
| 101 | cache-sets = <512>; |
| 102 | }; |
| 103 | }; |