blob: 244ef8d6cc688ccd0211820df60bf65e4b1320ce [file] [log] [blame]
Tim Harvey5fe2ef02021-03-02 14:00:20 -08001// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2020 Gateworks Corporation
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/leds/common.h>
Marcel Ziswilerca453f22022-07-21 15:27:40 +02008#include <dt-bindings/phy/phy-imx8-pcie.h>
Tim Harvey5fe2ef02021-03-02 14:00:20 -08009
10/ {
11 aliases {
Marcel Ziswilerca453f22022-07-21 15:27:40 +020012 ethernet1 = &eth1;
Tim Harvey5fe2ef02021-03-02 14:00:20 -080013 usb0 = &usbotg1;
14 usb1 = &usbotg2;
15 };
16
17 led-controller {
18 compatible = "gpio-leds";
19 pinctrl-names = "default";
20 pinctrl-0 = <&pinctrl_gpio_leds>;
21
22 led-0 {
23 function = LED_FUNCTION_STATUS;
24 color = <LED_COLOR_ID_GREEN>;
25 gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
26 default-state = "on";
27 linux,default-trigger = "heartbeat";
28 };
29
30 led-1 {
31 function = LED_FUNCTION_STATUS;
32 color = <LED_COLOR_ID_RED>;
33 gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
34 default-state = "off";
35 };
36 };
37
Marcel Ziswilerca453f22022-07-21 15:27:40 +020038 pcie0_refclk: pcie0-refclk {
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
41 clock-frequency = <100000000>;
42 };
43
Tim Harvey5fe2ef02021-03-02 14:00:20 -080044 pps {
45 compatible = "pps-gpio";
46 pinctrl-names = "default";
47 pinctrl-0 = <&pinctrl_pps>;
48 gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
49 status = "okay";
50 };
51
52 reg_1p8v: regulator-1p8v {
53 compatible = "regulator-fixed";
54 regulator-name = "1P8V";
55 regulator-min-microvolt = <1800000>;
56 regulator-max-microvolt = <1800000>;
57 regulator-always-on;
58 };
59
60 reg_3p3v: regulator-3p3v {
61 compatible = "regulator-fixed";
62 regulator-name = "3P3V";
63 regulator-min-microvolt = <3300000>;
64 regulator-max-microvolt = <3300000>;
65 regulator-always-on;
66 };
67
68 reg_usb_otg1_vbus: regulator-usb-otg1 {
69 pinctrl-names = "default";
70 pinctrl-0 = <&pinctrl_reg_usb1_en>;
71 compatible = "regulator-fixed";
72 regulator-name = "usb_otg1_vbus";
73 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
74 enable-active-high;
75 regulator-min-microvolt = <5000000>;
76 regulator-max-microvolt = <5000000>;
77 };
78
79 reg_usb_otg2_vbus: regulator-usb-otg2 {
80 pinctrl-names = "default";
81 pinctrl-0 = <&pinctrl_reg_usb2_en>;
82 compatible = "regulator-fixed";
83 regulator-name = "usb_otg2_vbus";
84 gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
85 enable-active-high;
86 regulator-min-microvolt = <5000000>;
87 regulator-max-microvolt = <5000000>;
88 };
89
90 reg_wifi_en: regulator-wifi-en {
91 pinctrl-names = "default";
92 pinctrl-0 = <&pinctrl_reg_wl>;
93 compatible = "regulator-fixed";
94 regulator-name = "wl";
95 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
96 startup-delay-us = <100>;
97 enable-active-high;
98 regulator-min-microvolt = <3300000>;
99 regulator-max-microvolt = <3300000>;
100 };
101};
102
103/* off-board header */
104&ecspi2 {
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_spi2>;
Marcel Ziswilerca453f22022-07-21 15:27:40 +0200107 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
Tim Harvey5fe2ef02021-03-02 14:00:20 -0800108 status = "okay";
109};
110
Marcel Ziswilerca453f22022-07-21 15:27:40 +0200111&gpio1 {
112 gpio-line-names = "rs485_term", "mipi_gpio4", "", "",
113 "", "", "pci_usb_sel", "dio0",
114 "", "dio1", "", "", "", "", "", "",
115 "", "", "", "", "", "", "", "",
116 "", "", "", "", "", "", "", "";
117};
118
119&gpio4 {
120 gpio-line-names = "rs485_en", "mipi_gpio3", "rs485_hd", "mipi_gpio2",
121 "mipi_gpio1", "", "", "pci_wdis#",
122 "", "", "", "", "", "", "", "",
123 "", "", "", "", "", "", "", "",
124 "", "", "", "", "", "", "", "";
125};
126
Tim Harvey5fe2ef02021-03-02 14:00:20 -0800127&i2c2 {
128 clock-frequency = <400000>;
129 pinctrl-names = "default";
130 pinctrl-0 = <&pinctrl_i2c2>;
131 status = "okay";
132
133 accelerometer@19 {
134 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_accel>;
136 compatible = "st,lis2de12";
137 reg = <0x19>;
138 st,drdy-int-pin = <1>;
139 interrupt-parent = <&gpio4>;
140 interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
141 interrupt-names = "INT1";
142 };
143};
144
145/* off-board header */
146&i2c3 {
147 clock-frequency = <400000>;
148 pinctrl-names = "default";
149 pinctrl-0 = <&pinctrl_i2c3>;
150 status = "okay";
151};
152
Marcel Ziswilerca453f22022-07-21 15:27:40 +0200153&pcie_phy {
154 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
155 fsl,clkreq-unsupported;
156 clocks = <&pcie0_refclk>;
157 clock-names = "ref";
158 status = "okay";
159};
160
161&pcie0 {
162 pinctrl-names = "default";
163 pinctrl-0 = <&pinctrl_pcie0>;
164 reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
165 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
166 <&pcie0_refclk>;
167 clock-names = "pcie", "pcie_aux", "pcie_bus";
168 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
169 <&clk IMX8MM_CLK_PCIE1_CTRL>;
170 assigned-clock-rates = <10000000>, <250000000>;
171 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
172 <&clk IMX8MM_SYS_PLL2_250M>;
173 status = "okay";
174
175 pcie@0,0 {
176 reg = <0x0000 0 0 0 0>;
177 #address-cells = <1>;
178 #size-cells = <0>;
179
180 pcie@1,0 {
181 reg = <0x0000 0 0 0 0>;
182 #address-cells = <1>;
183 #size-cells = <0>;
184
185 pcie@2,4 {
186 reg = <0x2000 0 0 0 0>;
187 #address-cells = <1>;
188 #size-cells = <0>;
189
190 eth1: pcie@6,0 {
191 reg = <0x0000 0 0 0 0>;
192 #address-cells = <1>;
193 #size-cells = <0>;
194
195 local-mac-address = [00 00 00 00 00 00];
196 };
197 };
198 };
199 };
200};
201
Tim Harvey5fe2ef02021-03-02 14:00:20 -0800202/* off-board header */
203&sai3 {
204 pinctrl-names = "default";
205 pinctrl-0 = <&pinctrl_sai3>;
206 assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
207 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
208 assigned-clock-rates = <24576000>;
209 status = "okay";
210};
211
212/* GPS */
213&uart1 {
214 pinctrl-names = "default";
215 pinctrl-0 = <&pinctrl_uart1>;
216 status = "okay";
217};
218
219/* bluetooth HCI */
220&uart3 {
221 pinctrl-names = "default";
222 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_bten>;
223 cts-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
224 rts-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
Marcel Ziswilerca453f22022-07-21 15:27:40 +0200225 uart-has-rtscts;
Tim Harvey5fe2ef02021-03-02 14:00:20 -0800226 status = "okay";
227
228 bluetooth {
229 compatible = "brcm,bcm4330-bt";
230 shutdown-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
231 };
232};
233
234/* RS232 */
235&uart4 {
236 pinctrl-names = "default";
237 pinctrl-0 = <&pinctrl_uart4>;
238 status = "okay";
239};
240
241&usbotg1 {
242 dr_mode = "otg";
Marcel Ziswilerca453f22022-07-21 15:27:40 +0200243 over-current-active-low;
Tim Harvey5fe2ef02021-03-02 14:00:20 -0800244 vbus-supply = <&reg_usb_otg1_vbus>;
245 status = "okay";
246};
247
248&usbotg2 {
249 dr_mode = "host";
Marcel Ziswilerca453f22022-07-21 15:27:40 +0200250 disable-over-current;
Tim Harvey5fe2ef02021-03-02 14:00:20 -0800251 vbus-supply = <&reg_usb_otg2_vbus>;
252 status = "okay";
253};
254
255/* SDIO WiFi */
256&usdhc1 {
257 pinctrl-names = "default";
258 pinctrl-0 = <&pinctrl_usdhc1>;
259 bus-width = <4>;
260 non-removable;
261 vmmc-supply = <&reg_wifi_en>;
262 status = "okay";
263};
264
265/* microSD */
266&usdhc2 {
267 pinctrl-names = "default", "state_100mhz", "state_200mhz";
268 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
269 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
270 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
271 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
272 bus-width = <4>;
273 vmmc-supply = <&reg_3p3v>;
274 status = "okay";
275};
276
277&iomuxc {
278 pinctrl-names = "default";
279 pinctrl-0 = <&pinctrl_hog>;
280
281 pinctrl_hog: hoggrp {
282 fsl,pins = <
283 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */
284 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */
285 MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */
286 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */
287 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */
288 MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000104 /* RS485_TERM */
289 MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x40000104 /* RS485 */
290 MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x40000104 /* RS485_HALF */
291 >;
292 };
293
294 pinctrl_accel: accelgrp {
295 fsl,pins = <
296 MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159
297 >;
298 };
299
300 pinctrl_bten: btengrp {
301 fsl,pins = <
302 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
303 >;
304 };
305
306 pinctrl_gpio_leds: gpioledgrp {
307 fsl,pins = <
308 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19
309 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19
310 >;
311 };
312
313 pinctrl_i2c3: i2c3grp {
314 fsl,pins = <
315 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
316 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
317 >;
318 };
319
Marcel Ziswilerca453f22022-07-21 15:27:40 +0200320 pinctrl_pcie0: pcie0grp {
321 fsl,pins = <
322 MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x41
323 >;
324 };
325
Tim Harvey5fe2ef02021-03-02 14:00:20 -0800326 pinctrl_pps: ppsgrp {
327 fsl,pins = <
328 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41
329 >;
330 };
331
332 pinctrl_reg_wl: regwlgrp {
333 fsl,pins = <
334 MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41
335 >;
336 };
337
338 pinctrl_reg_usb1_en: regusb1grp {
339 fsl,pins = <
340 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x41
341 MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41
342 >;
343 };
344
345 pinctrl_reg_usb2_en: regusb2grp {
346 fsl,pins = <
347 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x41
348 >;
349 };
350
351 pinctrl_sai3: sai3grp {
352 fsl,pins = <
353 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
354 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
355 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
356 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
357 MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
358 >;
359 };
360
361 pinctrl_spi2: spi2grp {
362 fsl,pins = <
363 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
364 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
Marcel Ziswilerca453f22022-07-21 15:27:40 +0200365 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6
Tim Harvey5fe2ef02021-03-02 14:00:20 -0800366 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
367 >;
368 };
369
370 pinctrl_uart1: uart1grp {
371 fsl,pins = <
372 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
373 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
374 >;
375 };
376
377 pinctrl_uart3: uart3grp {
378 fsl,pins = <
379 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
380 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
381 MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x140
382 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140
383 >;
384 };
385
386 pinctrl_uart4: uart4grp {
387 fsl,pins = <
388 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
389 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
390 >;
391 };
392
393 pinctrl_usdhc1: usdhc1grp {
394 fsl,pins = <
395 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
396 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
397 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
398 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
399 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
400 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
401 >;
402 };
403
404 pinctrl_usdhc2: usdhc2grp {
405 fsl,pins = <
406 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
407 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
408 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
409 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
410 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
411 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
412 >;
413 };
414
415 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
416 fsl,pins = <
417 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
418 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
419 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
420 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
421 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
422 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
423 >;
424 };
425
426 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
427 fsl,pins = <
428 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
429 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
430 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
431 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
432 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
433 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
434 >;
435 };
436
437 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
438 fsl,pins = <
439 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
440 MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x1d0
441 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
442 >;
443 };
444};