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git01.mediatek.com / filogic / uboot / c3d9e3d79d6a275fb964ae8a68cfbefeccc5d638 / . / arch / arm / dts / fsl-ls1012a-qds.dtsi
blob: 910d2a5c778e59c5eeefc57fd95cdfcff2479ef2 [file] [log] [blame]
Tom Rini8b0c8a12018-05-06 18:27:01 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR X11
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]2/*
3 * Copyright 2016 Freescale Semiconductor
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]4 */
5
6/include/ "fsl-ls1012a.dtsi"
7
8/ {
9 model = "LS1012A QDS Board";
10 aliases {
11 spi0 = &qspi;
12 spi1 = &dspi0;
13 };
14};
15
16&dspi0 {
17 bus-num = <0>;
18 status = "okay";
19
20 dflash0: n25q128a {
21 #address-cells = <1>;
22 #size-cells = <1>;
Neil Armstronga009fa72019-02-10 10:16:20 +0000[diff] [blame]23 compatible = "jedec,spi-nor";
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]24 reg = <0>;
25 spi-max-frequency = <1000000>; /* input clock */
26 };
27
28 dflash1: sst25wf040b {
29 #address-cells = <1>;
30 #size-cells = <1>;
Neil Armstronga009fa72019-02-10 10:16:20 +0000[diff] [blame]31 compatible = "jedec,spi-nor";
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]32 spi-max-frequency = <3500000>;
33 reg = <1>;
34 };
35
36 dflash2: en25s64 {
37 #address-cells = <1>;
38 #size-cells = <1>;
Neil Armstronga009fa72019-02-10 10:16:20 +0000[diff] [blame]39 compatible = "jedec,spi-nor";
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]40 spi-max-frequency = <3500000>;
41 reg = <2>;
42 };
43};
44
45&qspi {
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]46 status = "okay";
47
Kuldeep Singh4c380872019-12-12 11:49:24 +0530[diff] [blame]48 s25fs512s0: flash@0 {
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]49 #address-cells = <1>;
50 #size-cells = <1>;
Neil Armstronga009fa72019-02-10 10:16:20 +0000[diff] [blame]51 compatible = "jedec,spi-nor";
Kuldeep Singh4c380872019-12-12 11:49:24 +0530[diff] [blame]52 spi-max-frequency = <50000000>;
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]53 reg = <0>;
54 };
55};
56
57&i2c0 {
58 status = "okay";
59 pca9547@77 {
60 compatible = "philips,pca9547";
61 reg = <0x77>;
62 #address-cells = <1>;
63 #size-cells = <0>;
64
65 i2c@0 {
66 #address-cells = <1>;
67 #size-cells = <0>;
68 reg = <0x0>;
69
70 rtc@68 {
71 compatible = "dallas,ds3232";
72 reg = <0x68>;
73 /* IRQ10_B */
74 interrupts = <0 150 0x4>;
75 };
76 };
77
78 i2c@2 {
79 #address-cells = <1>;
80 #size-cells = <0>;
81 reg = <0x2>;
82
83 ina220@40 {
84 compatible = "ti,ina220";
85 reg = <0x40>;
86 shunt-resistor = <1000>;
87 };
88
89 ina220@41 {
90 compatible = "ti,ina220";
91 reg = <0x41>;
92 shunt-resistor = <1000>;
93 };
94 };
95
96 i2c@3 {
97 #address-cells = <1>;
98 #size-cells = <0>;
99 reg = <0x3>;
100
101 eeprom@56 {
102 compatible = "at24,24c512";
103 reg = <0x56>;
104 };
105
106 eeprom@57 {
107 compatible = "at24,24c512";
108 reg = <0x57>;
109 };
110
111 adt7461a@4c {
112 compatible = "adt7461a";
113 reg = <0x4c>;
114 };
115 };
116 };
117};
118
119&duart0 {
120 status = "okay";
121};
Ran Wangf12db5b2017-12-20 10:34:18 +0800[diff] [blame]122
123&usb0 {
124 status = "okay";
125 phy_type = "ulpi";
126};
Yuantian Tang019e6e02018-07-13 17:25:29 +0800[diff] [blame]127
128&sata {
129 status = "okay";
130};