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git01.mediatek.com / filogic / uboot / c3d57d2ae4567b17fe762cfafc14c5159bcc24a5 / . / drivers / clk / adi / clk-adi-sc594.c
blob: c80bbf9728d2faa85313d5f01de56679bd9be957 [file] [log] [blame]
Tom Rinidec7ea02024-05-20 13:35:03 -0600[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * (C) Copyright 2022 - Analog Devices, Inc.
4 *
5 * Written and/or maintained by Timesys Corporation
6 *
7 * Author: Greg Malysa <greg.malysa@timesys.com>
8 *
9 * Ported from Linux: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
10 */
11
12#include <clk.h>
13#include <clk-uclass.h>
14#include <dm.h>
15#include <dt-bindings/clock/adi-sc5xx-clock.h>
16#include <linux/compiler_types.h>
17#include <linux/clk-provider.h>
18#include <linux/io.h>
19#include <linux/ioport.h>
20#include <linux/printk.h>
21#include <linux/types.h>
22
23#include "clk.h"
24
25static const char * const cgu1_in_sels[] = {"sys_clkin0", "sys_clkin1"};
26static const char * const cgu0_s1sels[] = {"cgu0_s1seldiv", "cgu0_s1selexdiv"};
27static const char * const cgu1_s1sels[] = {"cgu1_s1seldiv", "cgu1_s1selexdiv"};
28static const char * const sharc0_sels[] = {"cclk0_0", "dummy", "dummy", "dummy"};
29static const char * const sharc1_sels[] = {"cclk0_0", "dummy", "dummy", "dummy"};
30static const char * const arm_sels[] = {"cclk1_0", "dummy", "dummy", "dummy"};
31static const char * const cdu_ddr_sels[] = {"dclk_0", "dclk_1", "dummy", "dummy"};
32static const char * const can_sels[] = {"oclk_0", "oclk_1", "dummy", "dummy"};
33static const char * const spdif_sels[] = {"sclk1_0", "dummy", "dummy", "dummy"};
34static const char * const spi_sels[] = {"sclk0_0", "oclk_0", "dummy", "dummy"};
35static const char * const gige_sels[] = {"sclk0_0", "sclk0_1", "cclk0_1", "dummy"};
36static const char * const lp_sels[] = {"oclk_0", "sclk0_0", "cclk0_1", "dummy"};
37static const char * const lpddr_sels[] = {"oclk_0", "dclk_0", "sysclkin_1", "dummy"};
38static const char * const ospi_sels[] = {"sysclk_0", "sclk0_0", "sclk1_1", "dummy"};
39static const char * const trace_sels[] = {"sclk0_0", "dummy", "dummy", "dummy"};
40
41static int sc594_clock_probe(struct udevice *dev)
42{
43 void __iomem *cgu0;
44 void __iomem *cgu1;
45 void __iomem *cdu;
46 int ret;
47 struct resource res;
48
49 struct clk *clks[ADSP_SC594_CLK_END];
50 struct clk dummy, clkin0, clkin1;
51
52 ret = dev_read_resource_byname(dev, "cgu0", &res);
53 if (ret)
54 return ret;
55 cgu0 = devm_ioremap(dev, res.start, resource_size(&res));
56
57 ret = dev_read_resource_byname(dev, "cgu1", &res);
58 if (ret)
59 return ret;
60 cgu1 = devm_ioremap(dev, res.start, resource_size(&res));
61
62 ret = dev_read_resource_byname(dev, "cdu", &res);
63 if (ret)
64 return ret;
65 cdu = devm_ioremap(dev, res.start, resource_size(&res));
66
67 // Input clock configuration
68 clk_get_by_name(dev, "dummy", &dummy);
69 clk_get_by_name(dev, "sys_clkin0", &clkin0);
70 clk_get_by_name(dev, "sys_clkin1", &clkin1);
71
72 clks[ADSP_SC594_CLK_DUMMY] = &dummy;
73 clks[ADSP_SC594_CLK_SYS_CLKIN0] = &clkin0;
74 clks[ADSP_SC594_CLK_SYS_CLKIN1] = &clkin1;
75 clks[ADSP_SC594_CLK_CGU1_IN] = clk_register_mux(NULL, "cgu1_in_sel", cgu1_in_sels,
76 2, CLK_SET_RATE_PARENT,
77 cdu + CDU_CLKINSEL, 0, 1, 0);
78
79 // CGU configuration and internal clocks
80 clks[ADSP_SC594_CLK_CGU0_PLL_IN] = clk_register_divider(NULL, "cgu0_df",
81 "sys_clkin0",
82 CLK_SET_RATE_PARENT,
83 cgu0 + CGU_CTL, 0, 1, 0);
84 clks[ADSP_SC594_CLK_CGU1_PLL_IN] = clk_register_divider(NULL, "cgu1_df",
85 "cgu1_in_sel",
86 CLK_SET_RATE_PARENT,
87 cgu1 + CGU_CTL, 0, 1, 0);
88
89 // VCO output inside PLL
90 clks[ADSP_SC594_CLK_CGU0_VCO_OUT] = sc5xx_cgu_pll("cgu0_vco", "cgu0_df",
91 cgu0 + CGU_CTL, CGU_MSEL_SHIFT,
92 CGU_MSEL_WIDTH, 0, false);
93 clks[ADSP_SC594_CLK_CGU1_VCO_OUT] = sc5xx_cgu_pll("cgu1_vco", "cgu1_df",
94 cgu1 + CGU_CTL, CGU_MSEL_SHIFT,
95 CGU_MSEL_WIDTH, 0, false);
96
97 // Final PLL output
98 clks[ADSP_SC594_CLK_CGU0_PLLCLK] = clk_register_fixed_factor(NULL, "cgu0_pllclk",
99 "cgu0_vco",
100 CLK_SET_RATE_PARENT,
101 1, 1);
102 clks[ADSP_SC594_CLK_CGU1_PLLCLK] = clk_register_fixed_factor(NULL, "cgu1_pllclk",
103 "cgu1_vco",
104 CLK_SET_RATE_PARENT,
105 1, 1);
106
107 // Dividers from pll output
108 clks[ADSP_SC594_CLK_CGU0_CDIV] = cgu_divider("cgu0_cdiv", "cgu0_pllclk",
109 cgu0 + CGU_DIV, 0, 5, 0);
110 clks[ADSP_SC594_CLK_CGU0_SYSCLK] = cgu_divider("sysclk_0", "cgu0_pllclk",
111 cgu0 + CGU_DIV, 8, 5, 0);
112 clks[ADSP_SC594_CLK_CGU0_DDIV] = cgu_divider("cgu0_ddiv", "cgu0_pllclk",
113 cgu0 + CGU_DIV, 16, 5, 0);
114 clks[ADSP_SC594_CLK_CGU0_ODIV] = cgu_divider("cgu0_odiv", "cgu0_pllclk",
115 cgu0 + CGU_DIV, 22, 7, 0);
116 clks[ADSP_SC594_CLK_CGU0_S0SELDIV] = cgu_divider("cgu0_s0seldiv", "sysclk_0",
117 cgu0 + CGU_DIV, 5, 3, 0);
118 clks[ADSP_SC594_CLK_CGU0_S1SELDIV] = cgu_divider("cgu0_s1seldiv", "sysclk_0",
119 cgu0 + CGU_DIV, 13, 3, 0);
120 clks[ADSP_SC594_CLK_CGU0_S1SELEXDIV] = cgu_divider("cgu0_s1selexdiv",
121 "cgu0_pllclk",
122 cgu0 + CGU_DIVEX, 16, 8, 0);
123 clks[ADSP_SC594_CLK_CGU0_S1SEL] = clk_register_mux(NULL, "cgu0_sclk1sel",
124 cgu0_s1sels, 2,
125 CLK_SET_RATE_PARENT,
126 cgu0 + CGU_CTL, 17, 1, 0);
127
128 clks[ADSP_SC594_CLK_CGU1_CDIV] = cgu_divider("cgu1_cdiv", "cgu1_pllclk",
129 cgu1 + CGU_DIV, 0, 5, 0);
130 clks[ADSP_SC594_CLK_CGU1_SYSCLK] = cgu_divider("sysclk_1", "cgu1_pllclk",
131 cgu1 + CGU_DIV, 8, 5, 0);
132 clks[ADSP_SC594_CLK_CGU1_DDIV] = cgu_divider("cgu1_ddiv", "cgu1_pllclk",
133 cgu1 + CGU_DIV, 16, 5, 0);
134 clks[ADSP_SC594_CLK_CGU1_ODIV] = cgu_divider("cgu1_odiv", "cgu1_pllclk",
135 cgu1 + CGU_DIV, 22, 7, 0);
136 clks[ADSP_SC594_CLK_CGU1_S0SELDIV] = cgu_divider("cgu1_s0seldiv", "sysclk_1",
137 cgu1 + CGU_DIV, 5, 3, 0);
138 clks[ADSP_SC594_CLK_CGU1_S1SELDIV] = cgu_divider("cgu1_s1seldiv", "sysclk_1",
139 cgu1 + CGU_DIV, 13, 3, 0);
140 clks[ADSP_SC594_CLK_CGU1_S1SELEXDIV] = cgu_divider("cgu1_s1selexdiv",
141 "cgu1_pllclk",
142 cgu1 + CGU_DIVEX, 16, 8, 0);
143 clks[ADSP_SC594_CLK_CGU1_S1SEL] = clk_register_mux(NULL, "cgu1_sclk1sel",
144 cgu1_s1sels, 2,
145 CLK_SET_RATE_PARENT,
146 cgu1 + CGU_CTL, 17, 1, 0);
147
148 // Gates to enable CGU outputs
149 clks[ADSP_SC594_CLK_CGU0_CCLK0] = cgu_gate("cclk0_0", "cgu0_cdiv",
150 cgu0 + CGU_CCBF_DIS, 0);
151 clks[ADSP_SC594_CLK_CGU0_CCLK1] = cgu_gate("cclk1_0", "cgu0_cdiv",
152 cgu1 + CGU_CCBF_DIS, 1);
153 clks[ADSP_SC594_CLK_CGU0_OCLK] = cgu_gate("oclk_0", "cgu0_odiv",
154 cgu0 + CGU_SCBF_DIS, 3);
155 clks[ADSP_SC594_CLK_CGU0_DCLK] = cgu_gate("dclk_0", "cgu0_ddiv",
156 cgu0 + CGU_SCBF_DIS, 2);
157 clks[ADSP_SC594_CLK_CGU0_SCLK1] = cgu_gate("sclk1_0", "cgu0_sclk1sel",
158 cgu0 + CGU_SCBF_DIS, 1);
159 clks[ADSP_SC594_CLK_CGU0_SCLK0] = cgu_gate("sclk0_0", "cgu0_s0seldiv",
160 cgu0 + CGU_SCBF_DIS, 0);
161
162 clks[ADSP_SC594_CLK_CGU1_CCLK0] = cgu_gate("cclk0_1", "cgu1_cdiv",
163 cgu1 + CGU_CCBF_DIS, 0);
164 clks[ADSP_SC594_CLK_CGU1_CCLK1] = cgu_gate("cclk1_1", "cgu1_cdiv",
165 cgu1 + CGU_CCBF_DIS, 1);
166 clks[ADSP_SC594_CLK_CGU1_OCLK] = cgu_gate("oclk_1", "cgu1_odiv",
167 cgu1 + CGU_SCBF_DIS, 3);
168 clks[ADSP_SC594_CLK_CGU1_DCLK] = cgu_gate("dclk_1", "cgu1_ddiv",
169 cgu1 + CGU_SCBF_DIS, 2);
170 clks[ADSP_SC594_CLK_CGU1_SCLK1] = cgu_gate("sclk1_1", "cgu1_sclk1sel",
171 cgu1 + CGU_SCBF_DIS, 1);
172 clks[ADSP_SC594_CLK_CGU1_SCLK0] = cgu_gate("sclk0_1", "cgu1_s0seldiv",
173 cgu1 + CGU_SCBF_DIS, 0);
174
175 // CDU output muxes
176 clks[ADSP_SC594_CLK_SHARC0_SEL] = cdu_mux("sharc0_sel", cdu + CDU_CFG0,
177 sharc0_sels);
178 clks[ADSP_SC594_CLK_SHARC1_SEL] = cdu_mux("sharc1_sel", cdu + CDU_CFG1,
179 sharc1_sels);
180 clks[ADSP_SC594_CLK_ARM_SEL] = cdu_mux("arm_sel", cdu + CDU_CFG2, arm_sels);
181 clks[ADSP_SC594_CLK_CDU_DDR_SEL] = cdu_mux("cdu_ddr_sel", cdu + CDU_CFG3,
182 cdu_ddr_sels);
183 clks[ADSP_SC594_CLK_CAN_SEL] = cdu_mux("can_sel", cdu + CDU_CFG4, can_sels);
184 clks[ADSP_SC594_CLK_SPDIF_SEL] = cdu_mux("spdif_sel", cdu + CDU_CFG5, spdif_sels);
185 clks[ADSP_SC594_CLK_RESERVED_SEL] = cdu_mux("spi_sel", cdu + CDU_CFG6, spi_sels);
186 clks[ADSP_SC594_CLK_GIGE_SEL] = cdu_mux("gige_sel", cdu + CDU_CFG7, gige_sels);
187 clks[ADSP_SC594_CLK_LP_SEL] = cdu_mux("lp_sel", cdu + CDU_CFG8, lp_sels);
188 clks[ADSP_SC594_CLK_LPDDR_SEL] = cdu_mux("lpddr_sel", cdu + CDU_CFG9, lpddr_sels);
189 clks[ADSP_SC594_CLK_OSPI_SEL] = cdu_mux("ospi_sel", cdu + CDU_CFG10,
190 ospi_sels);
191 clks[ADSP_SC594_CLK_TRACE_SEL] = cdu_mux("trace_sel", cdu + CDU_CFG12,
192 trace_sels);
193
194 // CDU output enable gates
195 clks[ADSP_SC594_CLK_SHARC0] = cdu_gate("sharc0", "sharc0_sel",
196 cdu + CDU_CFG0, CLK_IS_CRITICAL);
197 clks[ADSP_SC594_CLK_SHARC1] = cdu_gate("sharc1", "sharc1_sel",
198 cdu + CDU_CFG1, CLK_IS_CRITICAL);
199 clks[ADSP_SC594_CLK_ARM] = cdu_gate("arm", "arm_sel", cdu + CDU_CFG2,
200 CLK_IS_CRITICAL);
201 clks[ADSP_SC594_CLK_CDU_DDR] = cdu_gate("cdu_ddr", "cdu_ddr_sel",
202 cdu + CDU_CFG3, CLK_IS_CRITICAL);
203 clks[ADSP_SC594_CLK_CAN] = cdu_gate("can", "can_sel", cdu + CDU_CFG4, 0);
204 clks[ADSP_SC594_CLK_SPDIF] = cdu_gate("spdif", "spdif_sel", cdu + CDU_CFG5, 0);
205 clks[ADSP_SC594_CLK_SPI] = cdu_gate("spi", "spi_sel", cdu + CDU_CFG6, 0);
206 clks[ADSP_SC594_CLK_GIGE] = cdu_gate("gige", "gige_sel", cdu + CDU_CFG7, 0);
207 clks[ADSP_SC594_CLK_LP] = cdu_gate("lp", "lp_sel", cdu + CDU_CFG8, 0);
208 clks[ADSP_SC594_CLK_LPDDR] = cdu_gate("lpddr", "lpddr_sel", cdu + CDU_CFG9, 0);
209 clks[ADSP_SC594_CLK_OSPI] = cdu_gate("ospi", "ospi_sel", cdu + CDU_CFG10, 0);
210 clks[ADSP_SC594_CLK_TRACE] = cdu_gate("trace", "trace_sel", cdu + CDU_CFG12, 0);
211
212 ret = cdu_check_clocks(clks, ARRAY_SIZE(clks));
213 if (ret)
214 pr_err("CDU error detected\n");
215
216 return ret;
217}
218
219static const struct udevice_id adi_sc594_clk_ids[] = {
220 { .compatible = "adi,sc594-clocks" },
221 { },
222};
223
224U_BOOT_DRIVER(adi_sc594_clk) = {
225 .name = "clk_adi_sc594",
226 .id = UCLASS_CLK,
227 .of_match = adi_sc594_clk_ids,
228 .ops = &adi_clk_ops,
229 .probe = sc594_clock_probe,
230 .flags = DM_FLAG_PRE_RELOC,
231};