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git01.mediatek.com / filogic / uboot / c3d054f6d30287aa66ee98fbb9d3ae0d6f7acfde / . / arch / powerpc / cpu / mpc85xx / p3041_serdes.c
blob: b1586f110e86842f809a29777239523c1bb96702 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Kumar Galae378ae12010-07-04 13:07:08 -0500[diff] [blame]2/*
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
Kumar Galae378ae12010-07-04 13:07:08 -0500[diff] [blame]4 */
5
Kumar Galae378ae12010-07-04 13:07:08 -0500[diff] [blame]6#include <asm/fsl_serdes.h>
7#include <asm/processor.h>
8#include <asm/io.h>
9#include "fsl_corenet_serdes.h"
10
11static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
12 [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
13 PCIE4, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
14 SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
15 [0x4] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
16 PCIE2, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
17 SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, },
18 [0xb] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1,
19 PCIE2, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
20 SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
21 [0x10] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1,
22 AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
23 NONE, NONE, SATA1, SATA2, },
24 [0x11] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
25 AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
26 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
27 [0x13] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
28 AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
29 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1,
30 XAUI_FM1, XAUI_FM1, },
31 [0x14] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
32 AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3,
33 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
34 SGMII_FM1_DTSEC4, },
35 [0x15] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
36 AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
37 NONE, NONE, SATA1, SATA2, },
38 [0x16] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
39 AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
40 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SRIO1, SRIO1, SRIO1,
41 SRIO1, },
42 [0x17] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
43 AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
44 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
45 [0x18] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
46 AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
47 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE,
48 NONE, NONE, },
49 [0x1b] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
50 AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
51 NONE, NONE, SATA1, SATA2, },
52 [0x1d] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
53 AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE,
54 SATA1, SATA2, },
55 [0x20] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
56 AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
57 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1,
58 XAUI_FM1, XAUI_FM1, },
59 [0x21] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
60 AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3,
61 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
62 SGMII_FM1_DTSEC4, },
63 [0x22] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
64 AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
65 NONE, NONE, SATA1, SATA2, },
66 [0x23] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1,
67 AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
68 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
69 [0x24] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1,
70 AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
71 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE,
72 NONE, NONE, },
73 [0x28] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
74 AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
75 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
76 [0x29] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
77 AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
78 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE,
79 NONE, NONE, },
80 [0x2a] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
81 AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
82 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1,
83 XAUI_FM1, XAUI_FM1, },
84 [0x2b] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
85 AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
86 NONE, NONE, SATA1, SATA2, },
87 [0x2f] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO2, SRIO2, SRIO1, SRIO1,
88 AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
89 NONE, NONE, SATA1, SATA2, },
90 [0x31] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1,
91 AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
92 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE,
93 NONE, NONE, },
94 [0x33] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1,
95 AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
96 NONE, NONE, SATA1, SATA2, },
97 [0x34] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM1_DTSEC1,
98 SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA,
99 AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE,
100 NONE, SATA1, SATA2, },
101 [0x35] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2,
102 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1,
103 XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2, },
104 [0x36] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM1_DTSEC1,
105 SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA,
106 AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE,
107 NONE, SATA1, SATA2, },
108 [0x37] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2,
109 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1,
110 XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2, },
111};
112
113enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
114{
115 if (!serdes_lane_enabled(lane))
116 return NONE;
117
118 return serdes_cfg_tbl[cfg][lane];
119}
120
121int is_serdes_prtcl_valid(u32 prtcl) {
122 int i;
123
Axel Linab95b092013-05-26 15:00:30 +0800[diff] [blame]124 if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
Kumar Galae378ae12010-07-04 13:07:08 -0500[diff] [blame]125 return 0;
126
127 for (i = 0; i < SRDS_MAX_LANES; i++) {
128 if (serdes_cfg_tbl[prtcl][i] != NONE)
129 return 1;
130 }
131
132 return 0;
133}