Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Marek Vasut | 926227e | 2011-11-08 23:18:21 +0000 | [diff] [blame] | 2 | /* |
| 3 | * armboot - Startup Code for ARM926EJS CPU-core |
| 4 | * |
| 5 | * Copyright (c) 2003 Texas Instruments |
| 6 | * |
| 7 | * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ |
| 8 | * |
| 9 | * Copyright (c) 2001 Marius Groger <mag@sysgo.de> |
| 10 | * Copyright (c) 2002 Alex Zupke <azu@sysgo.de> |
| 11 | * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> |
| 12 | * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> |
| 13 | * Copyright (c) 2003 Kshitij <kshitij@ti.com> |
| 14 | * Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net> |
| 15 | * |
| 16 | * Change to support call back into iMX28 bootrom |
| 17 | * Copyright (c) 2011 Marek Vasut <marek.vasut@gmail.com> |
| 18 | * on behalf of DENX Software Engineering GmbH |
Marek Vasut | 926227e | 2011-11-08 23:18:21 +0000 | [diff] [blame] | 19 | */ |
| 20 | |
| 21 | #include <asm-offsets.h> |
| 22 | #include <config.h> |
Tom Rini | 4ddbade | 2022-05-25 12:16:03 -0400 | [diff] [blame] | 23 | #include <system-constants.h> |
Marek Vasut | 926227e | 2011-11-08 23:18:21 +0000 | [diff] [blame] | 24 | |
Marek Vasut | 926227e | 2011-11-08 23:18:21 +0000 | [diff] [blame] | 25 | /* |
| 26 | ************************************************************************* |
| 27 | * |
Marek Vasut | 926227e | 2011-11-08 23:18:21 +0000 | [diff] [blame] | 28 | * Startup Code (reset vector) |
| 29 | * |
| 30 | * do important init only if we don't start from memory! |
| 31 | * setup Memory and board specific bits prior to relocation. |
| 32 | * relocate armboot to ram |
| 33 | * setup stack |
| 34 | * |
| 35 | ************************************************************************* |
| 36 | */ |
| 37 | |
Albert ARIBAUD | 9852cc6 | 2014-04-15 16:13:51 +0200 | [diff] [blame] | 38 | .globl reset |
| 39 | reset: |
Marek Vasut | 926227e | 2011-11-08 23:18:21 +0000 | [diff] [blame] | 40 | /* |
Marek Vasut | edc43b0 | 2013-09-20 01:36:44 +0200 | [diff] [blame] | 41 | * If the CPU is configured in "Wait JTAG connection mode", the stack |
| 42 | * pointer is not configured and is zero. This will cause crash when |
| 43 | * trying to push data onto stack right below here. Load the SP and make |
| 44 | * it point to the end of OCRAM if the SP is zero. |
| 45 | */ |
| 46 | cmp sp, #0x00000000 |
Tom Rini | 4ddbade | 2022-05-25 12:16:03 -0400 | [diff] [blame] | 47 | ldreq sp, =SYS_INIT_SP_ADDR |
Marek Vasut | edc43b0 | 2013-09-20 01:36:44 +0200 | [diff] [blame] | 48 | |
| 49 | /* |
Marek Vasut | 926227e | 2011-11-08 23:18:21 +0000 | [diff] [blame] | 50 | * Store all registers on old stack pointer, this will allow us later to |
| 51 | * return to the BootROM and let the BootROM load U-Boot into RAM. |
Marek Vasut | 0dc62ba | 2013-08-31 15:53:44 +0200 | [diff] [blame] | 52 | * |
| 53 | * WARNING: Register r0 and r1 are used by the BootROM to pass data |
| 54 | * to the called code. Register r0 will contain arbitrary |
| 55 | * data that are set in the BootStream. In case this code |
| 56 | * was started with CALL instruction, register r1 will contain |
| 57 | * pointer to the return value this function can then set. |
| 58 | * The code below MUST NOT CHANGE register r0 and r1 ! |
Marek Vasut | 926227e | 2011-11-08 23:18:21 +0000 | [diff] [blame] | 59 | */ |
| 60 | push {r0-r12,r14} |
| 61 | |
Marek Vasut | 0dc62ba | 2013-08-31 15:53:44 +0200 | [diff] [blame] | 62 | /* Save control register c1 */ |
| 63 | mrc p15, 0, r2, c1, c0, 0 |
| 64 | push {r2} |
Matthias Fuchs | dcb3a8a | 2012-02-06 23:32:42 +0000 | [diff] [blame] | 65 | |
Marek Vasut | 0dc62ba | 2013-08-31 15:53:44 +0200 | [diff] [blame] | 66 | /* Set the cpu to SVC32 mode and store old CPSR register content. */ |
| 67 | mrs r2, cpsr |
| 68 | push {r2} |
| 69 | bic r2, r2, #0x1f |
| 70 | orr r2, r2, #0xd3 |
| 71 | msr cpsr, r2 |
Marek Vasut | 926227e | 2011-11-08 23:18:21 +0000 | [diff] [blame] | 72 | |
Marek Vasut | 926227e | 2011-11-08 23:18:21 +0000 | [diff] [blame] | 73 | bl board_init_ll |
| 74 | |
Marek Vasut | 0dc62ba | 2013-08-31 15:53:44 +0200 | [diff] [blame] | 75 | /* Restore BootROM's CPU mode (especially FIQ). */ |
| 76 | pop {r2} |
| 77 | msr cpsr,r2 |
| 78 | |
Matthias Fuchs | dcb3a8a | 2012-02-06 23:32:42 +0000 | [diff] [blame] | 79 | /* |
Marek Vasut | 0dc62ba | 2013-08-31 15:53:44 +0200 | [diff] [blame] | 80 | * Restore c1 register. Especially set exception vector location |
| 81 | * back to BootROM space which is required by bootrom for USB boot. |
Matthias Fuchs | dcb3a8a | 2012-02-06 23:32:42 +0000 | [diff] [blame] | 82 | */ |
Marek Vasut | 0dc62ba | 2013-08-31 15:53:44 +0200 | [diff] [blame] | 83 | pop {r2} |
| 84 | mcr p15, 0, r2, c1, c0, 0 |
| 85 | |
| 86 | pop {r0-r12,r14} |
Matthias Fuchs | dcb3a8a | 2012-02-06 23:32:42 +0000 | [diff] [blame] | 87 | |
| 88 | /* |
Marek Vasut | 0dc62ba | 2013-08-31 15:53:44 +0200 | [diff] [blame] | 89 | * In case this code was started by the CALL instruction, the register |
| 90 | * r0 is examined by the BootROM after this code returns. The value in |
| 91 | * r0 must be set to 0 to indicate successful return. |
Matthias Fuchs | dcb3a8a | 2012-02-06 23:32:42 +0000 | [diff] [blame] | 92 | */ |
Marek Vasut | 0dc62ba | 2013-08-31 15:53:44 +0200 | [diff] [blame] | 93 | mov r0, #0 |
Matthias Fuchs | dcb3a8a | 2012-02-06 23:32:42 +0000 | [diff] [blame] | 94 | |
Marek Vasut | 926227e | 2011-11-08 23:18:21 +0000 | [diff] [blame] | 95 | bx lr |