blob: 0989407fc7db8093204d6b25516bfdb4080f85fe [file] [log] [blame]
wdenkc6097192002-11-03 00:24:07 +00001/*
Matthias Fuchsd1797702007-03-13 13:38:05 +01002 * (C) Copyright 2007
3 * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
4 *
stroesea9484a92004-12-16 18:05:42 +00005 * (C) Copyright 2001-2004
Matthias Fuchsd1797702007-03-13 13:38:05 +01006 * Stefan Roese, DENX Software Engineering, sr@denx.de.
wdenkc6097192002-11-03 00:24:07 +00007 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +02008 * SPDX-License-Identifier: GPL-2.0+
wdenkc6097192002-11-03 00:24:07 +00009 */
10
11/*
12 * board/config.h - configuration options, board specific
13 */
14
15#ifndef __CONFIG_H
16#define __CONFIG_H
17
18/*
19 * High Level Configuration Options
20 * (easy to change)
21 */
wdenkc6097192002-11-03 00:24:07 +000022#define CONFIG_405GP 1 /* This is a PPC405 CPU */
wdenkda55c6e2004-01-20 23:12:12 +000023#define CONFIG_PCI405 1 /* ...on a PCI405 board */
wdenkc6097192002-11-03 00:24:07 +000024
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020025#define CONFIG_SYS_TEXT_BASE 0xFFFD0000
26
wdenkda55c6e2004-01-20 23:12:12 +000027#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
wdenkc6097192002-11-03 00:24:07 +000028#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() on init */
29
wdenkda55c6e2004-01-20 23:12:12 +000030#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
wdenkc6097192002-11-03 00:24:07 +000031
stroesea9484a92004-12-16 18:05:42 +000032#define CONFIG_BOARD_TYPES 1 /* support board types */
wdenkc6097192002-11-03 00:24:07 +000033
stroesea9484a92004-12-16 18:05:42 +000034#define CONFIG_BAUDRATE 115200
35#define CONFIG_BOOTDELAY 0 /* autoboot after 0 seconds */
wdenkc6097192002-11-03 00:24:07 +000036
37#undef CONFIG_BOOTARGS
stroesea9484a92004-12-16 18:05:42 +000038#define CONFIG_EXTRA_ENV_SETTINGS \
39 "mem_linux=14336k\0" \
40 "optargs=panic=0\0" \
41 "ramargs=setenv bootargs mem=$mem_linux root=/dev/ram rw\0" \
Matthias Fuchsd1797702007-03-13 13:38:05 +010042 "addcons=setenv bootargs $bootargs console=ttyS0,$baudrate $optargs\0" \
stroesea9484a92004-12-16 18:05:42 +000043 ""
Matthias Fuchsd1797702007-03-13 13:38:05 +010044#define CONFIG_BOOTCOMMAND "run ramargs;run addcons;loadpci"
stroesea9484a92004-12-16 18:05:42 +000045
46#define CONFIG_PREBOOT /* enable preboot variable */
wdenkc6097192002-11-03 00:24:07 +000047
Jon Loeligerbeb9ff42007-07-10 09:22:23 -050048/*
Jon Loeligercc1f0bb2007-07-08 14:49:44 -050049 * Command line configuration.
50 */
51#include <config_cmd_default.h>
52
Matthias Fuchseda6a402008-11-24 15:11:10 +010053#undef CONFIG_CMD_IMLS
54#undef CONFIG_CMD_ITEST
55#undef CONFIG_CMD_LOADB
56#undef CONFIG_CMD_LOADS
57#undef CONFIG_CMD_NET
58#undef CONFIG_CMD_NFS
59
Jon Loeligercc1f0bb2007-07-08 14:49:44 -050060#define CONFIG_CMD_PCI
Jon Loeligercc1f0bb2007-07-08 14:49:44 -050061#define CONFIG_CMD_ELF
Jon Loeligercc1f0bb2007-07-08 14:49:44 -050062#define CONFIG_CMD_I2C
63#define CONFIG_CMD_BSP
64#define CONFIG_CMD_EEPROM
65
wdenkda55c6e2004-01-20 23:12:12 +000066#undef CONFIG_WATCHDOG /* watchdog disabled */
wdenkc6097192002-11-03 00:24:07 +000067
wdenkda55c6e2004-01-20 23:12:12 +000068#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
wdenkc6097192002-11-03 00:24:07 +000069
wdenkda55c6e2004-01-20 23:12:12 +000070#define CONFIG_PRAM 2048 /* reserve 2 MB "protected RAM" */
stroese65f36a72003-03-25 14:41:35 +000071
wdenkc6097192002-11-03 00:24:07 +000072/*
73 * Miscellaneous configurable options
74 */
wdenkc6097192002-11-03 00:24:07 +000075
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020076#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
wdenkc6097192002-11-03 00:24:07 +000077
Jon Loeligercc1f0bb2007-07-08 14:49:44 -050078#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020079#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +000080#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020081#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +000082#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020083#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
84#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
85#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkc6097192002-11-03 00:24:07 +000086
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020087#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
wdenkc6097192002-11-03 00:24:07 +000088
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020089#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
wdenkc6097192002-11-03 00:24:07 +000090
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020091#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
92#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkc6097192002-11-03 00:24:07 +000093
Stefan Roese3ddce572010-09-20 16:05:31 +020094#define CONFIG_CONS_INDEX 1 /* Use UART0 */
95#define CONFIG_SYS_NS16550
96#define CONFIG_SYS_NS16550_SERIAL
97#define CONFIG_SYS_NS16550_REG_SIZE 1
98#define CONFIG_SYS_NS16550_CLK get_serial_clock()
99
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200100#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200101#define CONFIG_SYS_BASE_BAUD 691200
wdenkc6097192002-11-03 00:24:07 +0000102
103/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200104#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk57b2d802003-06-27 21:31:46 +0000105 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
106 57600, 115200, 230400, 460800, 921600 }
wdenkc6097192002-11-03 00:24:07 +0000107
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200108#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
109#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
wdenkc6097192002-11-03 00:24:07 +0000110
stroese65f36a72003-03-25 14:41:35 +0000111#undef CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
wdenkc6097192002-11-03 00:24:07 +0000112
wdenkda55c6e2004-01-20 23:12:12 +0000113#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
stroese9b117ff2003-09-12 08:53:54 +0000114
wdenkc6097192002-11-03 00:24:07 +0000115/*-----------------------------------------------------------------------
116 * PCI stuff
117 *-----------------------------------------------------------------------
118 */
wdenkda55c6e2004-01-20 23:12:12 +0000119#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
120#define PCI_HOST_FORCE 1 /* configure as pci host */
121#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
wdenkc6097192002-11-03 00:24:07 +0000122
wdenkda55c6e2004-01-20 23:12:12 +0000123#define CONFIG_PCI /* include pci support */
Gabor Juhosb4458732013-05-30 07:06:12 +0000124#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
wdenkda55c6e2004-01-20 23:12:12 +0000125#define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci host function */
126#undef CONFIG_PCI_PNP /* no pci plug-and-play */
127 /* resource configuration */
wdenkc6097192002-11-03 00:24:07 +0000128
wdenkda55c6e2004-01-20 23:12:12 +0000129#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
wdenkc6097192002-11-03 00:24:07 +0000130
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200131#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
132#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0407 /* PCI Device ID: PCI-405 */
133#define CONFIG_SYS_PCI_CLASSCODE 0x0280 /* PCI Class Code: Network/Other*/
134#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
135#define CONFIG_SYS_PCI_PTM1MS 0xff000001 /* 16MB, enable hard-wired to 1 */
136#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
wdenkc6097192002-11-03 00:24:07 +0000137
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200138#define CONFIG_SYS_PCI_PTM2LA 0xef600000 /* point to internal regs */
139#define CONFIG_SYS_PCI_PTM2MS 0xffe00001 /* 2MB, enable */
140#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
wdenkc6097192002-11-03 00:24:07 +0000141
142/*-----------------------------------------------------------------------
143 * Start addresses for the final memory configuration
144 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200145 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkc6097192002-11-03 00:24:07 +0000146 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200147#define CONFIG_SYS_SDRAM_BASE 0x00000000
148#define CONFIG_SYS_FLASH_BASE 0xFFFD0000
149#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
150#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */
151#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
wdenkc6097192002-11-03 00:24:07 +0000152
153/*
154 * For booting Linux, the board info and command line data
155 * have to be in the first 8 MB of memory, since this is
156 * the maximum mapped by the Linux kernel during initialization.
157 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200158#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkc6097192002-11-03 00:24:07 +0000159/*-----------------------------------------------------------------------
160 * FLASH organization
161 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200162#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
163#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenkc6097192002-11-03 00:24:07 +0000164
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200165#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
166#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenkc6097192002-11-03 00:24:07 +0000167
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200168#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
169#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
170#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
wdenkc6097192002-11-03 00:24:07 +0000171/*
172 * The following defines are added for buggy IOP480 byte interface.
173 * All other boards should use the standard values (CPCI405 etc.)
174 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200175#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
176#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
177#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
wdenkc6097192002-11-03 00:24:07 +0000178
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200179#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
wdenkc6097192002-11-03 00:24:07 +0000180
Jean-Christophe PLAGNIOL-VILLARDe46af642008-09-05 09:19:30 +0200181#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200182#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
183#define CONFIG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars*/
wdenk57b2d802003-06-27 21:31:46 +0000184 /* total size of a CAT24WC08 is 1024 bytes */
wdenkc6097192002-11-03 00:24:07 +0000185
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200186#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
187#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
wdenkc6097192002-11-03 00:24:07 +0000188
189/*-----------------------------------------------------------------------
190 * I2C EEPROM (CAT24WC16) for environment
191 */
Dirk Eibach42b204f2013-04-25 02:40:01 +0000192#define CONFIG_SYS_I2C
193#define CONFIG_SYS_I2C_PPC4XX
194#define CONFIG_SYS_I2C_PPC4XX_CH0
195#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
196#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
wdenkc6097192002-11-03 00:24:07 +0000197
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200198#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
199#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
wdenkda55c6e2004-01-20 23:12:12 +0000200/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200201#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
202#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
wdenkc6097192002-11-03 00:24:07 +0000203 /* 16 byte page write mode using*/
wdenkda55c6e2004-01-20 23:12:12 +0000204 /* last 4 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200205#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
wdenkc6097192002-11-03 00:24:07 +0000206
wdenkc6097192002-11-03 00:24:07 +0000207/*
208 * Init Memory Controller:
209 *
210 * BR0/1 and OR0/1 (FLASH)
211 */
212
213#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */
214
215/*-----------------------------------------------------------------------
216 * External Bus Controller (EBC) Setup
217 */
218
wdenkda55c6e2004-01-20 23:12:12 +0000219/* Memory Bank 0 (Flash Bank 0) initialization */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200220#define CONFIG_SYS_EBC_PB0AP 0x92015480
221#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
wdenkc6097192002-11-03 00:24:07 +0000222
wdenkda55c6e2004-01-20 23:12:12 +0000223/* Memory Bank 1 (NVRAM/RTC) initialization */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200224#define CONFIG_SYS_EBC_PB1AP 0x01005280 /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1 */
225#define CONFIG_SYS_EBC_PB1CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
wdenkc6097192002-11-03 00:24:07 +0000226
wdenkda55c6e2004-01-20 23:12:12 +0000227/* Memory Bank 2 (CAN0, 1) initialization */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200228#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
229/*#define CONFIG_SYS_EBC_PB2AP 0x038056C0 / * BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
230#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
wdenkc6097192002-11-03 00:24:07 +0000231
wdenkda55c6e2004-01-20 23:12:12 +0000232/* Memory Bank 3 (FPGA internal) initialization */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200233#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
234#define CONFIG_SYS_EBC_PB3CR 0xF041C000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */
235#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0400000
wdenkc6097192002-11-03 00:24:07 +0000236
237/*-----------------------------------------------------------------------
238 * FPGA stuff
239 */
240/* FPGA internal regs */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200241#define CONFIG_SYS_FPGA_MODE 0x00
242#define CONFIG_SYS_FPGA_STATUS 0x02
243#define CONFIG_SYS_FPGA_TS 0x04
244#define CONFIG_SYS_FPGA_TS_LOW 0x06
245#define CONFIG_SYS_FPGA_TS_CAP0 0x10
246#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12
247#define CONFIG_SYS_FPGA_TS_CAP1 0x14
248#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16
249#define CONFIG_SYS_FPGA_TS_CAP2 0x18
250#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a
251#define CONFIG_SYS_FPGA_TS_CAP3 0x1c
252#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e
wdenkc6097192002-11-03 00:24:07 +0000253
254/* FPGA Mode Reg */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200255#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001
256#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
257#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000
258#define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000
wdenkc6097192002-11-03 00:24:07 +0000259
260/* FPGA Status Reg */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200261#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001
262#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002
263#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004
264#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008
265#define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000
wdenkc6097192002-11-03 00:24:07 +0000266
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200267#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
268#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for XC2S15 */
wdenkc6097192002-11-03 00:24:07 +0000269
270/* FPGA program pin configuration */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200271#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
272#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
273#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
274#define CONFIG_SYS_FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */
275#define CONFIG_SYS_FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */
stroesea9484a92004-12-16 18:05:42 +0000276/* new INIT and DONE pins since board revision 1.2 (for PPC405GPr support) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200277#define CONFIG_SYS_FPGA_INIT_V12 0x00008000 /* FPGA init pin (ppc input) */
278#define CONFIG_SYS_FPGA_DONE_V12 0x00010000 /* FPGA done pin (ppc input) */
wdenkc6097192002-11-03 00:24:07 +0000279
280/*-----------------------------------------------------------------------
281 * Definitions for initial stack pointer and data area (in data cache)
282 */
stroesea9484a92004-12-16 18:05:42 +0000283/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200284#define CONFIG_SYS_TEMP_STACK_OCM 1
stroesea9484a92004-12-16 18:05:42 +0000285/* On Chip Memory location */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200286#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
287#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
288#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200289#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
stroesea9484a92004-12-16 18:05:42 +0000290
Wolfgang Denk0191e472010-10-26 14:34:52 +0200291#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200292#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkc6097192002-11-03 00:24:07 +0000293
wdenkc6097192002-11-03 00:24:07 +0000294#endif /* __CONFIG_H */