Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 1 | /* |
Kumar Gala | a9db4ec | 2011-01-11 00:52:35 -0600 | [diff] [blame] | 2 | * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc. |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 3 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 4 | * SPDX-License-Identifier: GPL-2.0+ |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | /* |
| 8 | * mpc8572ds board configuration file |
| 9 | * |
| 10 | */ |
| 11 | #ifndef __CONFIG_H |
| 12 | #define __CONFIG_H |
| 13 | |
York Sun | 4bd582d | 2014-04-30 14:43:49 -0700 | [diff] [blame] | 14 | #define CONFIG_SYS_GENERIC_BOARD |
| 15 | #define CONFIG_DISPLAY_BOARDINFO |
| 16 | |
Kumar Gala | f6f382b | 2010-05-21 04:05:14 -0500 | [diff] [blame] | 17 | #include "../board/freescale/common/ics307_clk.h" |
| 18 | |
Wolfgang Denk | dc25d15 | 2010-10-04 19:58:00 +0200 | [diff] [blame] | 19 | #ifdef CONFIG_36BIT |
Kumar Gala | 0d899ab | 2009-09-10 16:23:45 -0500 | [diff] [blame] | 20 | #define CONFIG_PHYS_64BIT |
| 21 | #endif |
| 22 | |
Kumar Gala | 90a535b | 2010-11-12 08:22:01 -0600 | [diff] [blame] | 23 | #ifndef CONFIG_SYS_TEXT_BASE |
York Sun | 6f231f3 | 2014-04-25 12:06:17 -0700 | [diff] [blame] | 24 | #define CONFIG_SYS_TEXT_BASE 0xeff40000 |
Kumar Gala | 90a535b | 2010-11-12 08:22:01 -0600 | [diff] [blame] | 25 | #endif |
| 26 | |
Kumar Gala | e727a36 | 2011-01-12 02:48:53 -0600 | [diff] [blame] | 27 | #ifndef CONFIG_RESET_VECTOR_ADDRESS |
| 28 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc |
| 29 | #endif |
| 30 | |
Kumar Gala | 90a535b | 2010-11-12 08:22:01 -0600 | [diff] [blame] | 31 | #ifndef CONFIG_SYS_MONITOR_BASE |
| 32 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
| 33 | #endif |
| 34 | |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 35 | /* High Level Configuration Options */ |
| 36 | #define CONFIG_BOOKE 1 /* BOOKE */ |
| 37 | #define CONFIG_E500 1 /* BOOKE e500 family */ |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 38 | #define CONFIG_MPC8572 1 |
| 39 | #define CONFIG_MPC8572DS 1 |
| 40 | #define CONFIG_MP 1 /* support multiple processors */ |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 41 | |
Kumar Gala | 1a5ba5f | 2009-01-23 14:22:13 -0600 | [diff] [blame] | 42 | #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 43 | #define CONFIG_PCI 1 /* Enable PCI/PCIE */ |
| 44 | #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ |
| 45 | #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ |
| 46 | #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ |
| 47 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ |
Gabor Juhos | b445873 | 2013-05-30 07:06:12 +0000 | [diff] [blame] | 48 | #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 49 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ |
Kumar Gala | 7738d5c | 2008-10-21 11:33:58 -0500 | [diff] [blame] | 50 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 51 | |
| 52 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
| 53 | |
| 54 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
| 55 | #define CONFIG_ENV_OVERWRITE |
| 56 | |
Kumar Gala | f6f382b | 2010-05-21 04:05:14 -0500 | [diff] [blame] | 57 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ |
| 58 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */ |
Haiying Wang | bcf35e5 | 2008-10-03 12:37:41 -0400 | [diff] [blame] | 59 | #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 60 | |
| 61 | /* |
| 62 | * These can be toggled for performance analysis, otherwise use default. |
| 63 | */ |
| 64 | #define CONFIG_L2_CACHE /* toggle L2 cache */ |
| 65 | #define CONFIG_BTB /* toggle branch predition */ |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 66 | |
| 67 | #define CONFIG_ENABLE_36BIT_PHYS 1 |
| 68 | |
Kumar Gala | e0f9741 | 2009-01-23 14:22:14 -0600 | [diff] [blame] | 69 | #ifdef CONFIG_PHYS_64BIT |
| 70 | #define CONFIG_ADDR_MAP 1 |
| 71 | #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ |
| 72 | #endif |
| 73 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 74 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ |
| 75 | #define CONFIG_SYS_MEMTEST_END 0x7fffffff |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 76 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ |
| 77 | |
| 78 | /* |
Kumar Gala | 90a535b | 2010-11-12 08:22:01 -0600 | [diff] [blame] | 79 | * Config the L2 Cache as L2 SRAM |
| 80 | */ |
| 81 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 |
| 82 | #ifdef CONFIG_PHYS_64BIT |
| 83 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull |
| 84 | #else |
| 85 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR |
| 86 | #endif |
| 87 | #define CONFIG_SYS_L2_SIZE (512 << 10) |
| 88 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) |
| 89 | |
Timur Tabi | d8f341c | 2011-08-04 18:03:41 -0500 | [diff] [blame] | 90 | #define CONFIG_SYS_CCSRBAR 0xffe00000 |
| 91 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 92 | |
Kumar Gala | 842aa5b | 2011-11-09 09:10:49 -0600 | [diff] [blame] | 93 | #if defined(CONFIG_NAND_SPL) |
Timur Tabi | d8f341c | 2011-08-04 18:03:41 -0500 | [diff] [blame] | 94 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE |
Kumar Gala | 90a535b | 2010-11-12 08:22:01 -0600 | [diff] [blame] | 95 | #endif |
| 96 | |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 97 | /* DDR Setup */ |
Kumar Gala | 6630ffb | 2009-02-06 09:56:35 -0600 | [diff] [blame] | 98 | #define CONFIG_VERY_BIG_RAM |
York Sun | f062659 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 99 | #define CONFIG_SYS_FSL_DDR2 |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 100 | #undef CONFIG_FSL_DDR_INTERACTIVE |
| 101 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ |
| 102 | #define CONFIG_DDR_SPD |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 103 | |
York Sun | 5e8435a | 2011-01-25 21:51:29 -0800 | [diff] [blame] | 104 | #define CONFIG_DDR_ECC |
Dave Liu | d3ca124 | 2008-10-28 17:53:38 +0800 | [diff] [blame] | 105 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 106 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
| 107 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 108 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
| 109 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 110 | |
| 111 | #define CONFIG_NUM_DDR_CONTROLLERS 2 |
| 112 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| 113 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 |
| 114 | |
| 115 | /* I2C addresses of SPD EEPROMs */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 116 | #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */ |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 117 | #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ |
| 118 | #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ |
| 119 | |
| 120 | /* These are used when DDR doesn't use SPD. */ |
Dave Liu | 6b78b16 | 2008-11-28 20:16:58 +0800 | [diff] [blame] | 121 | #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ |
| 122 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F |
| 123 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ |
| 124 | #define CONFIG_SYS_DDR_TIMING_3 0x00020000 |
| 125 | #define CONFIG_SYS_DDR_TIMING_0 0x00260802 |
| 126 | #define CONFIG_SYS_DDR_TIMING_1 0x626b2634 |
| 127 | #define CONFIG_SYS_DDR_TIMING_2 0x062874cf |
| 128 | #define CONFIG_SYS_DDR_MODE_1 0x00440462 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 129 | #define CONFIG_SYS_DDR_MODE_2 0x00000000 |
Dave Liu | 6b78b16 | 2008-11-28 20:16:58 +0800 | [diff] [blame] | 130 | #define CONFIG_SYS_DDR_INTERVAL 0x0c300100 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 131 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef |
Dave Liu | 6b78b16 | 2008-11-28 20:16:58 +0800 | [diff] [blame] | 132 | #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000 |
| 133 | #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 134 | #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 |
Dave Liu | 6b78b16 | 2008-11-28 20:16:58 +0800 | [diff] [blame] | 135 | #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */ |
| 136 | #define CONFIG_SYS_DDR_CONTROL2 0x24400000 |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 137 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 138 | #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d |
| 139 | #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 |
| 140 | #define CONFIG_SYS_DDR_SBE 0x00010000 |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 141 | |
| 142 | /* |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 143 | * Make sure required options are set |
| 144 | */ |
| 145 | #ifndef CONFIG_SPD_EEPROM |
| 146 | #error ("CONFIG_SPD_EEPROM is required") |
| 147 | #endif |
| 148 | |
| 149 | #undef CONFIG_CLOCKS_IN_MHZ |
| 150 | |
| 151 | /* |
| 152 | * Memory map |
| 153 | * |
| 154 | * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable |
| 155 | * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable |
| 156 | * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable |
| 157 | * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable |
| 158 | * |
| 159 | * Localbus cacheable (TBD) |
| 160 | * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable |
| 161 | * |
| 162 | * Localbus non-cacheable |
| 163 | * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable |
| 164 | * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable |
Wolfgang Denk | 82f15f3 | 2008-11-02 16:14:22 +0100 | [diff] [blame] | 165 | * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 166 | * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 |
| 167 | * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 |
| 168 | * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable |
| 169 | */ |
| 170 | |
| 171 | /* |
| 172 | * Local Bus Definitions |
| 173 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 174 | #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ |
Kumar Gala | e0f9741 | 2009-01-23 14:22:14 -0600 | [diff] [blame] | 175 | #ifdef CONFIG_PHYS_64BIT |
| 176 | #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull |
| 177 | #else |
Kumar Gala | 4be8b57 | 2008-12-02 14:19:34 -0600 | [diff] [blame] | 178 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE |
Kumar Gala | e0f9741 | 2009-01-23 14:22:14 -0600 | [diff] [blame] | 179 | #endif |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 180 | |
Kumar Gala | 90a535b | 2010-11-12 08:22:01 -0600 | [diff] [blame] | 181 | |
| 182 | #define CONFIG_FLASH_BR_PRELIM \ |
Timur Tabi | b56570c | 2012-07-06 07:39:26 +0000 | [diff] [blame] | 183 | (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) |
Kumar Gala | 90a535b | 2010-11-12 08:22:01 -0600 | [diff] [blame] | 184 | #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 185 | |
Kumar Gala | 4be8b57 | 2008-12-02 14:19:34 -0600 | [diff] [blame] | 186 | #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) |
| 187 | #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 188 | |
Kumar Gala | e0f9741 | 2009-01-23 14:22:14 -0600 | [diff] [blame] | 189 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 190 | #define CONFIG_SYS_FLASH_QUIET_TEST |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 191 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
| 192 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 193 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
| 194 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ |
| 195 | #undef CONFIG_SYS_FLASH_CHECKSUM |
| 196 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
| 197 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 198 | |
Kumar Gala | 90a535b | 2010-11-12 08:22:01 -0600 | [diff] [blame] | 199 | #undef CONFIG_SYS_RAMBOOT |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 200 | |
| 201 | #define CONFIG_FLASH_CFI_DRIVER |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 202 | #define CONFIG_SYS_FLASH_CFI |
| 203 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
| 204 | #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 205 | |
| 206 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ |
| 207 | |
Kumar Gala | 362b998 | 2010-11-19 08:53:25 -0600 | [diff] [blame] | 208 | #define CONFIG_HWCONFIG /* enable hwconfig */ |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 209 | #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ |
| 210 | #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ |
Kumar Gala | e0f9741 | 2009-01-23 14:22:14 -0600 | [diff] [blame] | 211 | #ifdef CONFIG_PHYS_64BIT |
| 212 | #define PIXIS_BASE_PHYS 0xfffdf0000ull |
| 213 | #else |
Kumar Gala | 0f492b4 | 2008-12-02 14:19:33 -0600 | [diff] [blame] | 214 | #define PIXIS_BASE_PHYS PIXIS_BASE |
Kumar Gala | e0f9741 | 2009-01-23 14:22:14 -0600 | [diff] [blame] | 215 | #endif |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 216 | |
Kumar Gala | 0f492b4 | 2008-12-02 14:19:33 -0600 | [diff] [blame] | 217 | #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 218 | #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 219 | |
| 220 | #define PIXIS_ID 0x0 /* Board ID at offset 0 */ |
| 221 | #define PIXIS_VER 0x1 /* Board version at offset 1 */ |
| 222 | #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ |
| 223 | #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ |
| 224 | #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ |
| 225 | #define PIXIS_PWR 0x5 /* PIXIS Power status register */ |
| 226 | #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ |
| 227 | #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ |
| 228 | #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ |
| 229 | #define PIXIS_VCTL 0x10 /* VELA Control Register */ |
| 230 | #define PIXIS_VSTAT 0x11 /* VELA Status Register */ |
| 231 | #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ |
| 232 | #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ |
| 233 | #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ |
| 234 | #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ |
Kumar Gala | e21db03 | 2009-07-14 22:42:01 -0500 | [diff] [blame] | 235 | #define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */ |
| 236 | #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ |
| 237 | #define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */ |
| 238 | #define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */ |
| 239 | #define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */ |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 240 | #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ |
| 241 | #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ |
| 242 | #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ |
| 243 | #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */ |
| 244 | #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */ |
| 245 | #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */ |
| 246 | #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */ |
| 247 | #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */ |
| 248 | #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */ |
| 249 | #define PIXIS_VWATCH 0x24 /* Watchdog Register */ |
| 250 | #define PIXIS_LED 0x25 /* LED Register */ |
| 251 | |
Kumar Gala | 90a535b | 2010-11-12 08:22:01 -0600 | [diff] [blame] | 252 | #define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */ |
| 253 | |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 254 | /* old pixis referenced names */ |
| 255 | #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ |
| 256 | #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 257 | #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 |
Liu Yu | c49bce4 | 2008-10-10 11:40:59 +0800 | [diff] [blame] | 258 | #define PIXIS_VSPEED2_TSEC1SER 0x8 |
| 259 | #define PIXIS_VSPEED2_TSEC2SER 0x4 |
| 260 | #define PIXIS_VSPEED2_TSEC3SER 0x2 |
| 261 | #define PIXIS_VSPEED2_TSEC4SER 0x1 |
| 262 | #define PIXIS_VCFGEN1_TSEC1SER 0x20 |
| 263 | #define PIXIS_VCFGEN1_TSEC2SER 0x20 |
| 264 | #define PIXIS_VCFGEN1_TSEC3SER 0x20 |
| 265 | #define PIXIS_VCFGEN1_TSEC4SER 0x20 |
| 266 | #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ |
| 267 | | PIXIS_VSPEED2_TSEC2SER \ |
| 268 | | PIXIS_VSPEED2_TSEC3SER \ |
| 269 | | PIXIS_VSPEED2_TSEC4SER) |
| 270 | #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ |
| 271 | | PIXIS_VCFGEN1_TSEC2SER \ |
| 272 | | PIXIS_VCFGEN1_TSEC3SER \ |
| 273 | | PIXIS_VCFGEN1_TSEC4SER) |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 274 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 275 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
| 276 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 277 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 278 | |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 279 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 280 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 281 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 282 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
| 283 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 284 | |
Kumar Gala | 90a535b | 2010-11-12 08:22:01 -0600 | [diff] [blame] | 285 | #ifndef CONFIG_NAND_SPL |
Haiying Wang | 9fce13f | 2008-10-29 13:32:59 -0400 | [diff] [blame] | 286 | #define CONFIG_SYS_NAND_BASE 0xffa00000 |
Kumar Gala | e0f9741 | 2009-01-23 14:22:14 -0600 | [diff] [blame] | 287 | #ifdef CONFIG_PHYS_64BIT |
| 288 | #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull |
| 289 | #else |
Haiying Wang | 9fce13f | 2008-10-29 13:32:59 -0400 | [diff] [blame] | 290 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE |
Kumar Gala | e0f9741 | 2009-01-23 14:22:14 -0600 | [diff] [blame] | 291 | #endif |
Kumar Gala | 90a535b | 2010-11-12 08:22:01 -0600 | [diff] [blame] | 292 | #else |
| 293 | #define CONFIG_SYS_NAND_BASE 0xfff00000 |
| 294 | #ifdef CONFIG_PHYS_64BIT |
| 295 | #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull |
| 296 | #else |
| 297 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE |
| 298 | #endif |
| 299 | #endif |
| 300 | |
Haiying Wang | 9fce13f | 2008-10-29 13:32:59 -0400 | [diff] [blame] | 301 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ |
| 302 | CONFIG_SYS_NAND_BASE + 0x40000, \ |
| 303 | CONFIG_SYS_NAND_BASE + 0x80000,\ |
| 304 | CONFIG_SYS_NAND_BASE + 0xC0000} |
| 305 | #define CONFIG_SYS_MAX_NAND_DEVICE 4 |
Haiying Wang | 9fce13f | 2008-10-29 13:32:59 -0400 | [diff] [blame] | 306 | #define CONFIG_MTD_NAND_VERIFY_WRITE |
Wolfgang Denk | 82f15f3 | 2008-11-02 16:14:22 +0100 | [diff] [blame] | 307 | #define CONFIG_CMD_NAND 1 |
| 308 | #define CONFIG_NAND_FSL_ELBC 1 |
Haiying Wang | 9fce13f | 2008-10-29 13:32:59 -0400 | [diff] [blame] | 309 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) |
Prabhakar Kushwaha | 4d2ba17 | 2013-10-04 13:47:58 +0530 | [diff] [blame] | 310 | #define CONFIG_SYS_NAND_MAX_OOBFREE 5 |
| 311 | #define CONFIG_SYS_NAND_MAX_ECCPOS 56 |
Haiying Wang | 9fce13f | 2008-10-29 13:32:59 -0400 | [diff] [blame] | 312 | |
Kumar Gala | 90a535b | 2010-11-12 08:22:01 -0600 | [diff] [blame] | 313 | /* NAND boot: 4K NAND loader config */ |
| 314 | #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 |
| 315 | #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) |
| 316 | #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) |
| 317 | #define CONFIG_SYS_NAND_U_BOOT_START \ |
| 318 | (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) |
| 319 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) |
| 320 | #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) |
| 321 | #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) |
| 322 | |
| 323 | |
Haiying Wang | 9fce13f | 2008-10-29 13:32:59 -0400 | [diff] [blame] | 324 | /* NAND flash config */ |
Matthew McClintock | 48aab14 | 2011-04-05 14:39:33 -0500 | [diff] [blame] | 325 | #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
Wolfgang Denk | 82f15f3 | 2008-11-02 16:14:22 +0100 | [diff] [blame] | 326 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
| 327 | | BR_PS_8 /* Port Size = 8 bit */ \ |
| 328 | | BR_MS_FCM /* MSEL = FCM */ \ |
| 329 | | BR_V) /* valid */ |
Matthew McClintock | 48aab14 | 2011-04-05 14:39:33 -0500 | [diff] [blame] | 330 | #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ |
Wolfgang Denk | 82f15f3 | 2008-11-02 16:14:22 +0100 | [diff] [blame] | 331 | | OR_FCM_PGS /* Large Page*/ \ |
| 332 | | OR_FCM_CSCT \ |
| 333 | | OR_FCM_CST \ |
| 334 | | OR_FCM_CHT \ |
| 335 | | OR_FCM_SCY_1 \ |
| 336 | | OR_FCM_TRLX \ |
| 337 | | OR_FCM_EHTR) |
Haiying Wang | 9fce13f | 2008-10-29 13:32:59 -0400 | [diff] [blame] | 338 | |
Kumar Gala | 90a535b | 2010-11-12 08:22:01 -0600 | [diff] [blame] | 339 | #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ |
| 340 | #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ |
Matthew McClintock | 48aab14 | 2011-04-05 14:39:33 -0500 | [diff] [blame] | 341 | #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ |
| 342 | #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
Timur Tabi | b56570c | 2012-07-06 07:39:26 +0000 | [diff] [blame] | 343 | #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ |
Wolfgang Denk | 82f15f3 | 2008-11-02 16:14:22 +0100 | [diff] [blame] | 344 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
| 345 | | BR_PS_8 /* Port Size = 8 bit */ \ |
| 346 | | BR_MS_FCM /* MSEL = FCM */ \ |
| 347 | | BR_V) /* valid */ |
Matthew McClintock | 48aab14 | 2011-04-05 14:39:33 -0500 | [diff] [blame] | 348 | #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
Timur Tabi | b56570c | 2012-07-06 07:39:26 +0000 | [diff] [blame] | 349 | #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\ |
Wolfgang Denk | 82f15f3 | 2008-11-02 16:14:22 +0100 | [diff] [blame] | 350 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
| 351 | | BR_PS_8 /* Port Size = 8 bit */ \ |
| 352 | | BR_MS_FCM /* MSEL = FCM */ \ |
| 353 | | BR_V) /* valid */ |
Matthew McClintock | 48aab14 | 2011-04-05 14:39:33 -0500 | [diff] [blame] | 354 | #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
Haiying Wang | 9fce13f | 2008-10-29 13:32:59 -0400 | [diff] [blame] | 355 | |
Timur Tabi | b56570c | 2012-07-06 07:39:26 +0000 | [diff] [blame] | 356 | #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\ |
Wolfgang Denk | 82f15f3 | 2008-11-02 16:14:22 +0100 | [diff] [blame] | 357 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
| 358 | | BR_PS_8 /* Port Size = 8 bit */ \ |
| 359 | | BR_MS_FCM /* MSEL = FCM */ \ |
| 360 | | BR_V) /* valid */ |
Matthew McClintock | 48aab14 | 2011-04-05 14:39:33 -0500 | [diff] [blame] | 361 | #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
Haiying Wang | 9fce13f | 2008-10-29 13:32:59 -0400 | [diff] [blame] | 362 | |
| 363 | |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 364 | /* Serial Port - controlled on board with jumper J8 |
| 365 | * open - index 2 |
| 366 | * shorted - index 1 |
| 367 | */ |
| 368 | #define CONFIG_CONS_INDEX 1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 369 | #define CONFIG_SYS_NS16550 |
| 370 | #define CONFIG_SYS_NS16550_SERIAL |
| 371 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| 372 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) |
Kumar Gala | 90a535b | 2010-11-12 08:22:01 -0600 | [diff] [blame] | 373 | #ifdef CONFIG_NAND_SPL |
| 374 | #define CONFIG_NS16550_MIN_FUNCTIONS |
| 375 | #endif |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 376 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 377 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 378 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
| 379 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 380 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
| 381 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 382 | |
| 383 | /* Use the HUSH parser */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 384 | #define CONFIG_SYS_HUSH_PARSER |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 385 | |
| 386 | /* |
| 387 | * Pass open firmware flat tree |
| 388 | */ |
| 389 | #define CONFIG_OF_LIBFDT 1 |
| 390 | #define CONFIG_OF_BOARD_SETUP 1 |
| 391 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
| 392 | |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 393 | /* new uImage format support */ |
| 394 | #define CONFIG_FIT 1 |
| 395 | #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ |
| 396 | |
| 397 | /* I2C */ |
Heiko Schocher | f285074 | 2012-10-24 13:48:22 +0200 | [diff] [blame] | 398 | #define CONFIG_SYS_I2C |
| 399 | #define CONFIG_SYS_I2C_FSL |
| 400 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 |
| 401 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
| 402 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 |
| 403 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 |
| 404 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F |
| 405 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 |
| 406 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 407 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 408 | |
| 409 | /* |
Haiying Wang | 374130f | 2008-10-03 11:47:30 -0400 | [diff] [blame] | 410 | * I2C2 EEPROM |
| 411 | */ |
| 412 | #define CONFIG_ID_EEPROM |
| 413 | #ifdef CONFIG_ID_EEPROM |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 414 | #define CONFIG_SYS_I2C_EEPROM_NXID |
Haiying Wang | 374130f | 2008-10-03 11:47:30 -0400 | [diff] [blame] | 415 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 416 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
| 417 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
| 418 | #define CONFIG_SYS_EEPROM_BUS_NUM 1 |
Haiying Wang | 374130f | 2008-10-03 11:47:30 -0400 | [diff] [blame] | 419 | |
| 420 | /* |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 421 | * General PCI |
| 422 | * Memory space is mapped 1-1, but I/O space must start from 0. |
| 423 | */ |
| 424 | |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 425 | /* controller 3, direct to uli, tgtid 3, Base address 8000 */ |
Kumar Gala | d165dc5 | 2010-12-17 06:53:52 -0600 | [diff] [blame] | 426 | #define CONFIG_SYS_PCIE3_NAME "ULI" |
Kumar Gala | ef43b6e | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 427 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 |
Kumar Gala | e0f9741 | 2009-01-23 14:22:14 -0600 | [diff] [blame] | 428 | #ifdef CONFIG_PHYS_64BIT |
Kumar Gala | e1cb3db | 2009-06-18 08:39:42 -0500 | [diff] [blame] | 429 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 |
Kumar Gala | e0f9741 | 2009-01-23 14:22:14 -0600 | [diff] [blame] | 430 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull |
| 431 | #else |
Kumar Gala | 2275d0e | 2009-02-09 22:03:05 -0600 | [diff] [blame] | 432 | #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 |
Kumar Gala | ef43b6e | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 433 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 |
Kumar Gala | e0f9741 | 2009-01-23 14:22:14 -0600 | [diff] [blame] | 434 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 435 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ |
Kumar Gala | 60ff464 | 2008-12-02 16:08:40 -0600 | [diff] [blame] | 436 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 |
Kumar Gala | 64bb6d1 | 2008-12-02 16:08:37 -0600 | [diff] [blame] | 437 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 |
Kumar Gala | e0f9741 | 2009-01-23 14:22:14 -0600 | [diff] [blame] | 438 | #ifdef CONFIG_PHYS_64BIT |
| 439 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull |
| 440 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 441 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 |
Kumar Gala | e0f9741 | 2009-01-23 14:22:14 -0600 | [diff] [blame] | 442 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 443 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 444 | |
| 445 | /* controller 2, Slot 2, tgtid 2, Base address 9000 */ |
Kumar Gala | d165dc5 | 2010-12-17 06:53:52 -0600 | [diff] [blame] | 446 | #define CONFIG_SYS_PCIE2_NAME "Slot 1" |
Kumar Gala | ef43b6e | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 447 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 |
Kumar Gala | e0f9741 | 2009-01-23 14:22:14 -0600 | [diff] [blame] | 448 | #ifdef CONFIG_PHYS_64BIT |
Kumar Gala | e1cb3db | 2009-06-18 08:39:42 -0500 | [diff] [blame] | 449 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 |
Kumar Gala | e0f9741 | 2009-01-23 14:22:14 -0600 | [diff] [blame] | 450 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull |
| 451 | #else |
Kumar Gala | 2275d0e | 2009-02-09 22:03:05 -0600 | [diff] [blame] | 452 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 |
Kumar Gala | ef43b6e | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 453 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 |
Kumar Gala | e0f9741 | 2009-01-23 14:22:14 -0600 | [diff] [blame] | 454 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 455 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ |
Kumar Gala | 60ff464 | 2008-12-02 16:08:40 -0600 | [diff] [blame] | 456 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 |
Kumar Gala | 64bb6d1 | 2008-12-02 16:08:37 -0600 | [diff] [blame] | 457 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 |
Kumar Gala | e0f9741 | 2009-01-23 14:22:14 -0600 | [diff] [blame] | 458 | #ifdef CONFIG_PHYS_64BIT |
| 459 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull |
| 460 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 461 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 |
Kumar Gala | e0f9741 | 2009-01-23 14:22:14 -0600 | [diff] [blame] | 462 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 463 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 464 | |
| 465 | /* controller 1, Slot 1, tgtid 1, Base address a000 */ |
Kumar Gala | d165dc5 | 2010-12-17 06:53:52 -0600 | [diff] [blame] | 466 | #define CONFIG_SYS_PCIE1_NAME "Slot 2" |
Kumar Gala | ef43b6e | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 467 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 |
Kumar Gala | e0f9741 | 2009-01-23 14:22:14 -0600 | [diff] [blame] | 468 | #ifdef CONFIG_PHYS_64BIT |
Kumar Gala | e1cb3db | 2009-06-18 08:39:42 -0500 | [diff] [blame] | 469 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 |
Kumar Gala | e0f9741 | 2009-01-23 14:22:14 -0600 | [diff] [blame] | 470 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull |
| 471 | #else |
Kumar Gala | 2275d0e | 2009-02-09 22:03:05 -0600 | [diff] [blame] | 472 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 |
Kumar Gala | ef43b6e | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 473 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 |
Kumar Gala | e0f9741 | 2009-01-23 14:22:14 -0600 | [diff] [blame] | 474 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 475 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
Kumar Gala | 60ff464 | 2008-12-02 16:08:40 -0600 | [diff] [blame] | 476 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 |
Kumar Gala | 64bb6d1 | 2008-12-02 16:08:37 -0600 | [diff] [blame] | 477 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
Kumar Gala | e0f9741 | 2009-01-23 14:22:14 -0600 | [diff] [blame] | 478 | #ifdef CONFIG_PHYS_64BIT |
| 479 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull |
| 480 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 481 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 |
Kumar Gala | e0f9741 | 2009-01-23 14:22:14 -0600 | [diff] [blame] | 482 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 483 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 484 | |
| 485 | #if defined(CONFIG_PCI) |
| 486 | |
| 487 | /*PCIE video card used*/ |
Kumar Gala | 60ff464 | 2008-12-02 16:08:40 -0600 | [diff] [blame] | 488 | #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 489 | |
| 490 | /* video */ |
| 491 | #define CONFIG_VIDEO |
| 492 | |
| 493 | #if defined(CONFIG_VIDEO) |
| 494 | #define CONFIG_BIOSEMU |
| 495 | #define CONFIG_CFB_CONSOLE |
| 496 | #define CONFIG_VIDEO_SW_CURSOR |
| 497 | #define CONFIG_VGA_AS_SINGLE_DEVICE |
| 498 | #define CONFIG_ATI_RADEON_FB |
| 499 | #define CONFIG_VIDEO_LOGO |
| 500 | /*#define CONFIG_CONSOLE_CURSOR*/ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 501 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 502 | #endif |
| 503 | |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 504 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
| 505 | |
| 506 | #undef CONFIG_EEPRO100 |
| 507 | #undef CONFIG_TULIP |
| 508 | #undef CONFIG_RTL8139 |
Kumar Gala | cfc113e | 2010-11-09 23:19:50 -0600 | [diff] [blame] | 509 | #define CONFIG_E1000 /* Define e1000 pci Ethernet card */ |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 510 | |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 511 | #ifndef CONFIG_PCI_PNP |
Kumar Gala | 64bb6d1 | 2008-12-02 16:08:37 -0600 | [diff] [blame] | 512 | #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS |
| 513 | #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 514 | #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ |
| 515 | #endif |
| 516 | |
| 517 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| 518 | #define CONFIG_DOS_PARTITION |
| 519 | #define CONFIG_SCSI_AHCI |
| 520 | |
| 521 | #ifdef CONFIG_SCSI_AHCI |
Rob Herring | 83f6648 | 2013-08-24 10:10:54 -0500 | [diff] [blame] | 522 | #define CONFIG_LIBATA |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 523 | #define CONFIG_SATA_ULI5288 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 524 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 |
| 525 | #define CONFIG_SYS_SCSI_MAX_LUN 1 |
| 526 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) |
| 527 | #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 528 | #endif /* SCSI */ |
| 529 | |
| 530 | #endif /* CONFIG_PCI */ |
| 531 | |
| 532 | |
| 533 | #if defined(CONFIG_TSEC_ENET) |
| 534 | |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 535 | #define CONFIG_MII 1 /* MII PHY management */ |
| 536 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ |
| 537 | #define CONFIG_TSEC1 1 |
| 538 | #define CONFIG_TSEC1_NAME "eTSEC1" |
| 539 | #define CONFIG_TSEC2 1 |
| 540 | #define CONFIG_TSEC2_NAME "eTSEC2" |
| 541 | #define CONFIG_TSEC3 1 |
| 542 | #define CONFIG_TSEC3_NAME "eTSEC3" |
| 543 | #define CONFIG_TSEC4 1 |
| 544 | #define CONFIG_TSEC4_NAME "eTSEC4" |
| 545 | |
Liu Yu | c49bce4 | 2008-10-10 11:40:59 +0800 | [diff] [blame] | 546 | #define CONFIG_PIXIS_SGMII_CMD |
| 547 | #define CONFIG_FSL_SGMII_RISER 1 |
| 548 | #define SGMII_RISER_PHY_OFFSET 0x1c |
| 549 | |
| 550 | #ifdef CONFIG_FSL_SGMII_RISER |
| 551 | #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ |
| 552 | #endif |
| 553 | |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 554 | #define TSEC1_PHY_ADDR 0 |
| 555 | #define TSEC2_PHY_ADDR 1 |
| 556 | #define TSEC3_PHY_ADDR 2 |
| 557 | #define TSEC4_PHY_ADDR 3 |
| 558 | |
| 559 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| 560 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| 561 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| 562 | #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| 563 | |
| 564 | #define TSEC1_PHYIDX 0 |
| 565 | #define TSEC2_PHYIDX 0 |
| 566 | #define TSEC3_PHYIDX 0 |
| 567 | #define TSEC4_PHYIDX 0 |
| 568 | |
| 569 | #define CONFIG_ETHPRIME "eTSEC1" |
| 570 | |
| 571 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ |
| 572 | #endif /* CONFIG_TSEC_ENET */ |
| 573 | |
| 574 | /* |
| 575 | * Environment |
| 576 | */ |
Kumar Gala | 90a535b | 2010-11-12 08:22:01 -0600 | [diff] [blame] | 577 | |
| 578 | #if defined(CONFIG_SYS_RAMBOOT) |
Kumar Gala | 90a535b | 2010-11-12 08:22:01 -0600 | [diff] [blame] | 579 | |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 580 | #else |
Kumar Gala | 90a535b | 2010-11-12 08:22:01 -0600 | [diff] [blame] | 581 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| 582 | #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 |
| 583 | #define CONFIG_ENV_ADDR 0xfff80000 |
| 584 | #else |
| 585 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
| 586 | #endif |
| 587 | #define CONFIG_ENV_SIZE 0x2000 |
| 588 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 589 | #endif |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 590 | |
| 591 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 592 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 593 | |
| 594 | /* |
| 595 | * Command line configuration. |
| 596 | */ |
| 597 | #include <config_cmd_default.h> |
| 598 | |
York Sun | 6cad41c | 2011-01-26 00:14:57 -0600 | [diff] [blame] | 599 | #define CONFIG_CMD_ERRATA |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 600 | #define CONFIG_CMD_IRQ |
| 601 | #define CONFIG_CMD_PING |
| 602 | #define CONFIG_CMD_I2C |
| 603 | #define CONFIG_CMD_MII |
| 604 | #define CONFIG_CMD_ELF |
Kumar Gala | 489675d | 2008-09-22 23:40:42 -0500 | [diff] [blame] | 605 | #define CONFIG_CMD_SETEXPR |
Becky Bruce | ee888da | 2010-06-17 11:37:25 -0500 | [diff] [blame] | 606 | #define CONFIG_CMD_REGINFO |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 607 | |
| 608 | #if defined(CONFIG_PCI) |
| 609 | #define CONFIG_CMD_PCI |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 610 | #define CONFIG_CMD_NET |
| 611 | #define CONFIG_CMD_SCSI |
| 612 | #define CONFIG_CMD_EXT2 |
| 613 | #endif |
| 614 | |
Zhao Chenhui | 36f15a8 | 2011-03-04 16:31:41 +0800 | [diff] [blame] | 615 | /* |
| 616 | * USB |
| 617 | */ |
| 618 | #define CONFIG_USB_EHCI |
| 619 | |
| 620 | #ifdef CONFIG_USB_EHCI |
| 621 | #define CONFIG_CMD_USB |
| 622 | #define CONFIG_USB_EHCI_PCI |
| 623 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
| 624 | #define CONFIG_USB_STORAGE |
| 625 | #define CONFIG_PCI_EHCI_DEVICE 0 |
| 626 | #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 |
| 627 | #endif |
| 628 | |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 629 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 630 | |
| 631 | /* |
| 632 | * Miscellaneous configurable options |
| 633 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 634 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
Kim Phillips | f7758c1 | 2010-07-14 19:47:18 -0500 | [diff] [blame] | 635 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
| 636 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 637 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 638 | #if defined(CONFIG_CMD_KGDB) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 639 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 640 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 641 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 642 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 643 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 644 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 645 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 646 | |
| 647 | /* |
| 648 | * For booting Linux, the board info and command line data |
Kumar Gala | 39ffcc1 | 2011-04-28 10:13:41 -0500 | [diff] [blame] | 649 | * have to be in the first 64 MB of memory, since this is |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 650 | * the maximum mapped by the Linux kernel during initialization. |
| 651 | */ |
Kumar Gala | 39ffcc1 | 2011-04-28 10:13:41 -0500 | [diff] [blame] | 652 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ |
| 653 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 654 | |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 655 | #if defined(CONFIG_CMD_KGDB) |
| 656 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 657 | #endif |
| 658 | |
| 659 | /* |
| 660 | * Environment Configuration |
| 661 | */ |
| 662 | |
| 663 | /* The mac addresses for all ethernet interface */ |
| 664 | #if defined(CONFIG_TSEC_ENET) |
| 665 | #define CONFIG_HAS_ETH0 |
| 666 | #define CONFIG_ETHADDR 00:E0:0C:02:00:FD |
| 667 | #define CONFIG_HAS_ETH1 |
| 668 | #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD |
| 669 | #define CONFIG_HAS_ETH2 |
| 670 | #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD |
| 671 | #define CONFIG_HAS_ETH3 |
| 672 | #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD |
| 673 | #endif |
| 674 | |
| 675 | #define CONFIG_IPADDR 192.168.1.254 |
| 676 | |
| 677 | #define CONFIG_HOSTNAME unknown |
Joe Hershberger | 257ff78 | 2011-10-13 13:03:47 +0000 | [diff] [blame] | 678 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
Joe Hershberger | e4da248 | 2011-10-13 13:03:48 +0000 | [diff] [blame] | 679 | #define CONFIG_BOOTFILE "uImage" |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 680 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ |
| 681 | |
| 682 | #define CONFIG_SERVERIP 192.168.1.1 |
| 683 | #define CONFIG_GATEWAYIP 192.168.1.1 |
| 684 | #define CONFIG_NETMASK 255.255.255.0 |
| 685 | |
| 686 | /* default location for tftp and bootm */ |
| 687 | #define CONFIG_LOADADDR 1000000 |
| 688 | |
| 689 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ |
| 690 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
| 691 | |
| 692 | #define CONFIG_BAUDRATE 115200 |
| 693 | |
| 694 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
Hongtao Jia | 39bb2f2 | 2012-12-20 19:36:12 +0000 | [diff] [blame] | 695 | "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \ |
Marek Vasut | 0b3176c | 2012-09-23 17:41:24 +0200 | [diff] [blame] | 696 | "netdev=eth0\0" \ |
| 697 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
| 698 | "tftpflash=tftpboot $loadaddr $uboot; " \ |
| 699 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ |
| 700 | " +$filesize; " \ |
| 701 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ |
| 702 | " +$filesize; " \ |
| 703 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ |
| 704 | " $filesize; " \ |
| 705 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ |
| 706 | " +$filesize; " \ |
| 707 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ |
| 708 | " $filesize\0" \ |
| 709 | "consoledev=ttyS0\0" \ |
| 710 | "ramdiskaddr=2000000\0" \ |
| 711 | "ramdiskfile=8572ds/ramdisk.uboot\0" \ |
| 712 | "fdtaddr=c00000\0" \ |
| 713 | "fdtfile=8572ds/mpc8572ds.dtb\0" \ |
| 714 | "bdev=sda3\0" |
Kumar Gala | 3ab0b2d | 2008-08-12 11:13:08 -0500 | [diff] [blame] | 715 | |
| 716 | #define CONFIG_HDBOOT \ |
| 717 | "setenv bootargs root=/dev/$bdev rw " \ |
| 718 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 719 | "tftp $loadaddr $bootfile;" \ |
| 720 | "tftp $fdtaddr $fdtfile;" \ |
| 721 | "bootm $loadaddr - $fdtaddr" |
| 722 | |
| 723 | #define CONFIG_NFSBOOTCOMMAND \ |
| 724 | "setenv bootargs root=/dev/nfs rw " \ |
| 725 | "nfsroot=$serverip:$rootpath " \ |
| 726 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ |
| 727 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 728 | "tftp $loadaddr $bootfile;" \ |
| 729 | "tftp $fdtaddr $fdtfile;" \ |
| 730 | "bootm $loadaddr - $fdtaddr" |
| 731 | |
| 732 | #define CONFIG_RAMBOOTCOMMAND \ |
| 733 | "setenv bootargs root=/dev/ram rw " \ |
| 734 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 735 | "tftp $ramdiskaddr $ramdiskfile;" \ |
| 736 | "tftp $loadaddr $bootfile;" \ |
| 737 | "tftp $fdtaddr $fdtfile;" \ |
| 738 | "bootm $loadaddr $ramdiskaddr $fdtaddr" |
| 739 | |
| 740 | #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT |
| 741 | |
| 742 | #endif /* __CONFIG_H */ |