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git01.mediatek.com / filogic / uboot / c38755aabcfda1ce4ef3e98c6e09571578114bbe / . / arch / arm / include / asm / arch-imx8m / clock_imx8mq.h
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Peng Fanc38755a2019-08-27 06:25:48 +0000[diff] [blame^]1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright 2017 NXP
4 *
5 * Peng Fan <peng.fan@nxp.com>
6 */
7
8#ifndef _ASM_ARCH_IMX8M_CLOCK_H
9#define _ASM_ARCH_IMX8M_CLOCK_H
10
11enum pll_clocks {
12 ANATOP_ARM_PLL,
13 ANATOP_GPU_PLL,
14 ANATOP_SYSTEM_PLL1,
15 ANATOP_SYSTEM_PLL2,
16 ANATOP_SYSTEM_PLL3,
17 ANATOP_AUDIO_PLL1,
18 ANATOP_AUDIO_PLL2,
19 ANATOP_VIDEO_PLL1,
20 ANATOP_VIDEO_PLL2,
21 ANATOP_DRAM_PLL,
22};
23
24enum clk_root_index {
25 ARM_A53_CLK_ROOT = 0,
26 ARM_M4_CLK_ROOT = 1,
27 VPU_A53_CLK_ROOT = 2,
28 GPU_CORE_CLK_ROOT = 3,
29 GPU_SHADER_CLK_ROOT = 4,
30 MAIN_AXI_CLK_ROOT = 16,
31 ENET_AXI_CLK_ROOT = 17,
32 NAND_USDHC_BUS_CLK_ROOT = 18,
33 VPU_BUS_CLK_ROOT = 19,
34 DISPLAY_AXI_CLK_ROOT = 20,
35 DISPLAY_APB_CLK_ROOT = 21,
36 DISPLAY_RTRM_CLK_ROOT = 22,
37 USB_BUS_CLK_ROOT = 23,
38 GPU_AXI_CLK_ROOT = 24,
39 GPU_AHB_CLK_ROOT = 25,
40 NOC_CLK_ROOT = 26,
41 NOC_APB_CLK_ROOT = 27,
42 AHB_CLK_ROOT = 32,
43 IPG_CLK_ROOT = 33,
44 AUDIO_AHB_CLK_ROOT = 34,
45 MIPI_DSI_ESC_RX_CLK_ROOT = 36,
46 DRAM_SEL_CFG = 48,
47 CORE_SEL_CFG = 49,
48 DRAM_ALT_CLK_ROOT = 64,
49 DRAM_APB_CLK_ROOT = 65,
50 VPU_G1_CLK_ROOT = 66,
51 VPU_G2_CLK_ROOT = 67,
52 DISPLAY_DTRC_CLK_ROOT = 68,
53 DISPLAY_DC8000_CLK_ROOT = 69,
54 PCIE1_CTRL_CLK_ROOT = 70,
55 PCIE1_PHY_CLK_ROOT = 71,
56 PCIE1_AUX_CLK_ROOT = 72,
57 DC_PIXEL_CLK_ROOT = 73,
58 LCDIF_PIXEL_CLK_ROOT = 74,
59 SAI1_CLK_ROOT = 75,
60 SAI2_CLK_ROOT = 76,
61 SAI3_CLK_ROOT = 77,
62 SAI4_CLK_ROOT = 78,
63 SAI5_CLK_ROOT = 79,
64 SAI6_CLK_ROOT = 80,
65 SPDIF1_CLK_ROOT = 81,
66 SPDIF2_CLK_ROOT = 82,
67 ENET_REF_CLK_ROOT = 83,
68 ENET_TIMER_CLK_ROOT = 84,
69 ENET_PHY_REF_CLK_ROOT = 85,
70 NAND_CLK_ROOT = 86,
71 QSPI_CLK_ROOT = 87,
72 USDHC1_CLK_ROOT = 88,
73 USDHC2_CLK_ROOT = 89,
74 I2C1_CLK_ROOT = 90,
75 I2C2_CLK_ROOT = 91,
76 I2C3_CLK_ROOT = 92,
77 I2C4_CLK_ROOT = 93,
78 UART1_CLK_ROOT = 94,
79 UART2_CLK_ROOT = 95,
80 UART3_CLK_ROOT = 96,
81 UART4_CLK_ROOT = 97,
82 USB_CORE_REF_CLK_ROOT = 98,
83 USB_PHY_REF_CLK_ROOT = 99,
84 GIC_CLK_ROOT = 100,
85 ECSPI1_CLK_ROOT = 101,
86 ECSPI2_CLK_ROOT = 102,
87 PWM1_CLK_ROOT = 103,
88 PWM2_CLK_ROOT = 104,
89 PWM3_CLK_ROOT = 105,
90 PWM4_CLK_ROOT = 106,
91 GPT1_CLK_ROOT = 107,
92 GPT2_CLK_ROOT = 108,
93 GPT3_CLK_ROOT = 109,
94 GPT4_CLK_ROOT = 110,
95 GPT5_CLK_ROOT = 111,
96 GPT6_CLK_ROOT = 112,
97 TRACE_CLK_ROOT = 113,
98 WDOG_CLK_ROOT = 114,
99 WRCLK_CLK_ROOT = 115,
100 IPP_DO_CLKO1 = 116,
101 IPP_DO_CLKO2 = 117,
102 MIPI_DSI_CORE_CLK_ROOT = 118,
103 MIPI_DSI_PHY_REF_CLK_ROOT = 119,
104 MIPI_DSI_DBI_CLK_ROOT = 120,
105 OLD_MIPI_DSI_ESC_CLK_ROOT = 121,
106 MIPI_CSI1_CORE_CLK_ROOT = 122,
107 MIPI_CSI1_PHY_REF_CLK_ROOT = 123,
108 MIPI_CSI1_ESC_CLK_ROOT = 124,
109 MIPI_CSI2_CORE_CLK_ROOT = 125,
110 MIPI_CSI2_PHY_REF_CLK_ROOT = 126,
111 MIPI_CSI2_ESC_CLK_ROOT = 127,
112 PCIE2_CTRL_CLK_ROOT = 128,
113 PCIE2_PHY_CLK_ROOT = 129,
114 PCIE2_AUX_CLK_ROOT = 130,
115 ECSPI3_CLK_ROOT = 131,
116 OLD_MIPI_DSI_ESC_RX_ROOT = 132,
117 DISPLAY_HDMI_CLK_ROOT = 133,
118 CLK_ROOT_MAX,
119};
120
121enum clk_root_src {
122 OSC_25M_CLK,
123 ARM_PLL_CLK,
124 DRAM_PLL1_CLK,
125 VIDEO_PLL2_CLK,
126 VPU_PLL_CLK,
127 GPU_PLL_CLK,
128 SYSTEM_PLL1_800M_CLK,
129 SYSTEM_PLL1_400M_CLK,
130 SYSTEM_PLL1_266M_CLK,
131 SYSTEM_PLL1_200M_CLK,
132 SYSTEM_PLL1_160M_CLK,
133 SYSTEM_PLL1_133M_CLK,
134 SYSTEM_PLL1_100M_CLK,
135 SYSTEM_PLL1_80M_CLK,
136 SYSTEM_PLL1_40M_CLK,
137 SYSTEM_PLL2_1000M_CLK,
138 SYSTEM_PLL2_500M_CLK,
139 SYSTEM_PLL2_333M_CLK,
140 SYSTEM_PLL2_250M_CLK,
141 SYSTEM_PLL2_200M_CLK,
142 SYSTEM_PLL2_166M_CLK,
143 SYSTEM_PLL2_125M_CLK,
144 SYSTEM_PLL2_100M_CLK,
145 SYSTEM_PLL2_50M_CLK,
146 SYSTEM_PLL3_CLK,
147 AUDIO_PLL1_CLK,
148 AUDIO_PLL2_CLK,
149 VIDEO_PLL_CLK,
150 OSC_32K_CLK,
151 EXT_CLK_1,
152 EXT_CLK_2,
153 EXT_CLK_3,
154 EXT_CLK_4,
155 OSC_27M_CLK,
156};
157
158/* CCGR index */
159enum clk_ccgr_index {
160 CCGR_DVFS = 0,
161 CCGR_ANAMIX = 1,
162 CCGR_CPU = 2,
163 CCGR_CSU = 4,
164 CCGR_DRAM1 = 5,
165 CCGR_DRAM2_OBSOLETE = 6,
166 CCGR_ECSPI1 = 7,
167 CCGR_ECSPI2 = 8,
168 CCGR_ECSPI3 = 9,
169 CCGR_ENET1 = 10,
170 CCGR_GPIO1 = 11,
171 CCGR_GPIO2 = 12,
172 CCGR_GPIO3 = 13,
173 CCGR_GPIO4 = 14,
174 CCGR_GPIO5 = 15,
175 CCGR_GPT1 = 16,
176 CCGR_GPT2 = 17,
177 CCGR_GPT3 = 18,
178 CCGR_GPT4 = 19,
179 CCGR_GPT5 = 20,
180 CCGR_GPT6 = 21,
181 CCGR_HS = 22,
182 CCGR_I2C1 = 23,
183 CCGR_I2C2 = 24,
184 CCGR_I2C3 = 25,
185 CCGR_I2C4 = 26,
186 CCGR_IOMUX = 27,
187 CCGR_IOMUX1 = 28,
188 CCGR_IOMUX2 = 29,
189 CCGR_IOMUX3 = 30,
190 CCGR_IOMUX4 = 31,
191 CCGR_M4 = 32,
192 CCGR_MU = 33,
193 CCGR_OCOTP = 34,
194 CCGR_OCRAM = 35,
195 CCGR_OCRAM_S = 36,
196 CCGR_PCIE = 37,
197 CCGR_PERFMON1 = 38,
198 CCGR_PERFMON2 = 39,
199 CCGR_PWM1 = 40,
200 CCGR_PWM2 = 41,
201 CCGR_PWM3 = 42,
202 CCGR_PWM4 = 43,
203 CCGR_QOS = 44,
204 CCGR_DISMIX = 45,
205 CCGR_MEGAMIX = 46,
206 CCGR_QSPI = 47,
207 CCGR_RAWNAND = 48,
208 CCGR_RDC = 49,
209 CCGR_ROM = 50,
210 CCGR_SAI1 = 51,
211 CCGR_SAI2 = 52,
212 CCGR_SAI3 = 53,
213 CCGR_SAI4 = 54,
214 CCGR_SAI5 = 55,
215 CCGR_SAI6 = 56,
216 CCGR_SCTR = 57,
217 CCGR_SDMA1 = 58,
218 CCGR_SDMA2 = 59,
219 CCGR_SEC_DEBUG = 60,
220 CCGR_SEMA1 = 61,
221 CCGR_SEMA2 = 62,
222 CCGR_SIM_DISPLAY = 63,
223 CCGR_SIM_ENET = 64,
224 CCGR_SIM_M = 65,
225 CCGR_SIM_MAIN = 66,
226 CCGR_SIM_S = 67,
227 CCGR_SIM_WAKEUP = 68,
228 CCGR_SIM_USB = 69,
229 CCGR_SIM_VPU = 70,
230 CCGR_SNVS = 71,
231 CCGR_TRACE = 72,
232 CCGR_UART1 = 73,
233 CCGR_UART2 = 74,
234 CCGR_UART3 = 75,
235 CCGR_UART4 = 76,
236 CCGR_USB_CTRL1 = 77,
237 CCGR_USB_CTRL2 = 78,
238 CCGR_USB_PHY1 = 79,
239 CCGR_USB_PHY2 = 80,
240 CCGR_USDHC1 = 81,
241 CCGR_USDHC2 = 82,
242 CCGR_WDOG1 = 83,
243 CCGR_WDOG2 = 84,
244 CCGR_WDOG3 = 85,
245 CCGR_VA53 = 86,
246 CCGR_GPU = 87,
247 CCGR_HEVC = 88,
248 CCGR_AVC = 89,
249 CCGR_VP9 = 90,
250 CCGR_HEVC_INTER = 91,
251 CCGR_GIC = 92,
252 CCGR_DISPLAY = 93,
253 CCGR_HDMI = 94,
254 CCGR_HDMI_PHY = 95,
255 CCGR_XTAL = 96,
256 CCGR_PLL = 97,
257 CCGR_TSENSOR = 98,
258 CCGR_VPU_DEC = 99,
259 CCGR_PCIE2 = 100,
260 CCGR_MIPI_CSI1 = 101,
261 CCGR_MIPI_CSI2 = 102,
262 CCGR_MAX,
263};
264
265/* src index */
266enum clk_src_index {
267 CLK_SRC_CKIL_SYNC_REQ = 0,
268 CLK_SRC_ARM_PLL_EN = 1,
269 CLK_SRC_GPU_PLL_EN = 2,
270 CLK_SRC_VPU_PLL_EN = 3,
271 CLK_SRC_DRAM_PLL_EN = 4,
272 CLK_SRC_SYSTEM_PLL1_EN = 5,
273 CLK_SRC_SYSTEM_PLL2_EN = 6,
274 CLK_SRC_SYSTEM_PLL3_EN = 7,
275 CLK_SRC_AUDIO_PLL1_EN = 8,
276 CLK_SRC_AUDIO_PLL2_EN = 9,
277 CLK_SRC_VIDEO_PLL1_EN = 10,
278 CLK_SRC_VIDEO_PLL2_EN = 11,
279 CLK_SRC_ARM_PLL = 12,
280 CLK_SRC_GPU_PLL = 13,
281 CLK_SRC_VPU_PLL = 14,
282 CLK_SRC_DRAM_PLL = 15,
283 CLK_SRC_SYSTEM_PLL1_800M = 16,
284 CLK_SRC_SYSTEM_PLL1_400M = 17,
285 CLK_SRC_SYSTEM_PLL1_266M = 18,
286 CLK_SRC_SYSTEM_PLL1_200M = 19,
287 CLK_SRC_SYSTEM_PLL1_160M = 20,
288 CLK_SRC_SYSTEM_PLL1_133M = 21,
289 CLK_SRC_SYSTEM_PLL1_100M = 22,
290 CLK_SRC_SYSTEM_PLL1_80M = 23,
291 CLK_SRC_SYSTEM_PLL1_40M = 24,
292 CLK_SRC_SYSTEM_PLL2_1000M = 25,
293 CLK_SRC_SYSTEM_PLL2_500M = 26,
294 CLK_SRC_SYSTEM_PLL2_333M = 27,
295 CLK_SRC_SYSTEM_PLL2_250M = 28,
296 CLK_SRC_SYSTEM_PLL2_200M = 29,
297 CLK_SRC_SYSTEM_PLL2_166M = 30,
298 CLK_SRC_SYSTEM_PLL2_125M = 31,
299 CLK_SRC_SYSTEM_PLL2_100M = 32,
300 CLK_SRC_SYSTEM_PLL2_50M = 33,
301 CLK_SRC_SYSTEM_PLL3 = 34,
302 CLK_SRC_AUDIO_PLL1 = 35,
303 CLK_SRC_AUDIO_PLL2 = 36,
304 CLK_SRC_VIDEO_PLL1 = 37,
305 CLK_SRC_VIDEO_PLL2 = 38,
306 CLK_SRC_OSC_25M = 39,
307 CLK_SRC_OSC_27M = 40,
308};
309
310/* AUDIO PLL1/2 VIDEO PLL1 GPU PLL VPU PLL ARM PLL*/
311#define FRAC_PLL_LOCK_MASK BIT(31)
312#define FRAC_PLL_CLKE_MASK BIT(21)
313#define FRAC_PLL_PD_MASK BIT(19)
314#define FRAC_PLL_REFCLK_SEL_MASK BIT(16)
315#define FRAC_PLL_LOCK_SEL_MASK BIT(15)
316#define FRAC_PLL_BYPASS_MASK BIT(14)
317#define FRAC_PLL_COUNTCLK_SEL_MASK BIT(13)
318#define FRAC_PLL_NEWDIV_VAL_MASK BIT(12)
319#define FRAC_PLL_NEWDIV_ACK_MASK BIT(11)
320#define FRAC_PLL_REFCLK_DIV_VAL(n) (((n) << 5) & (0x3f << 5))
321#define FRAC_PLL_REFCLK_DIV_VAL_MASK (0x3f << 5)
322#define FRAC_PLL_REFCLK_DIV_VAL_SHIFT 5
323#define FRAC_PLL_OUTPUT_DIV_VAL_MASK 0x1f
324#define FRAC_PLL_OUTPUT_DIV_VAL(n) ((n) & 0x1f)
325
326#define FRAC_PLL_REFCLK_SEL_OSC_25M (0 << 16)
327#define FRAC_PLL_REFCLK_SEL_OSC_27M BIT(16)
328#define FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16)
329#define FRAC_PLL_REFCLK_SEL_CLK_PN (3 << 16)
330
331#define FRAC_PLL_FRAC_DIV_CTL_MASK (0x1ffffff << 7)
332#define FRAC_PLL_FRAC_DIV_CTL_SHIFT 7
333#define FRAC_PLL_INT_DIV_CTL_MASK 0x7f
334#define FRAC_PLL_INT_DIV_CTL_VAL(n) ((n) & 0x7f)
335
336/* SYS PLL1/2/3 VIDEO PLL2 DRAM PLL */
337#define SSCG_PLL_LOCK_MASK BIT(31)
338#define SSCG_PLL_CLKE_MASK BIT(25)
339#define SSCG_PLL_DIV2_CLKE_MASK BIT(23)
340#define SSCG_PLL_DIV3_CLKE_MASK BIT(21)
341#define SSCG_PLL_DIV4_CLKE_MASK BIT(19)
342#define SSCG_PLL_DIV5_CLKE_MASK BIT(17)
343#define SSCG_PLL_DIV6_CLKE_MASK BIT(15)
344#define SSCG_PLL_DIV8_CLKE_MASK BIT(13)
345#define SSCG_PLL_DIV10_CLKE_MASK BIT(11)
346#define SSCG_PLL_DIV20_CLKE_MASK BIT(9)
347#define SSCG_PLL_VIDEO_PLL2_CLKE_MASK BIT(9)
348#define SSCG_PLL_DRAM_PLL_CLKE_MASK BIT(9)
349#define SSCG_PLL_PLL3_CLKE_MASK BIT(9)
350#define SSCG_PLL_PD_MASK BIT(7)
351#define SSCG_PLL_BYPASS1_MASK BIT(5)
352#define SSCG_PLL_BYPASS2_MASK BIT(4)
353#define SSCG_PLL_LOCK_SEL_MASK BIT(3)
354#define SSCG_PLL_COUNTCLK_SEL_MASK BIT(2)
355#define SSCG_PLL_REFCLK_SEL_MASK 0x3
356#define SSCG_PLL_REFCLK_SEL_OSC_25M (0 << 16)
357#define SSCG_PLL_REFCLK_SEL_OSC_27M BIT(16)
358#define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16)
359#define SSCG_PLL_REFCLK_SEL_CLK_PN (3 << 16)
360
361#define SSCG_PLL_SSDS_MASK BIT(8)
362#define SSCG_PLL_SSMD_MASK (0x7 << 5)
363#define SSCG_PLL_SSMF_MASK (0xf << 1)
364#define SSCG_PLL_SSE_MASK 0x1
365
366#define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25)
367#define SSCG_PLL_REF_DIVR1_SHIFT 25
368#define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK)
369#define SSCG_PLL_REF_DIVR2_MASK (0x3f << 19)
370#define SSCG_PLL_REF_DIVR2_SHIFT 19
371#define SSCG_PLL_REF_DIVR2_VAL(n) (((n) << 19) & SSCG_PLL_REF_DIVR2_MASK)
372#define SSCG_PLL_FEEDBACK_DIV_F1_MASK (0x3f << 13)
373#define SSCG_PLL_FEEDBACK_DIV_F1_SHIFT 13
374#define SSCG_PLL_FEEDBACK_DIV_F1_VAL(n) (((n) << 13) & \
375 SSCG_PLL_FEEDBACK_DIV_F1_MASK)
376#define SSCG_PLL_FEEDBACK_DIV_F2_MASK (0x3f << 7)
377#define SSCG_PLL_FEEDBACK_DIV_F2_SHIFT 7
378#define SSCG_PLL_FEEDBACK_DIV_F2_VAL(n) (((n) << 7) & \
379 SSCG_PLL_FEEDBACK_DIV_F2_MASK)
380#define SSCG_PLL_OUTPUT_DIV_VAL_MASK (0x3f << 1)
381#define SSCG_PLL_OUTPUT_DIV_VAL_SHIFT 1
382#define SSCG_PLL_OUTPUT_DIV_VAL(n) (((n) << 1) & \
383 SSCG_PLL_OUTPUT_DIV_VAL_MASK)
384#define SSCG_PLL_FILTER_RANGE_MASK 0x1
385
386#define HW_DIGPROG_MAJOR_UPPER_MASK (0xff << 16)
387#define HW_DIGPROG_MAJOR_LOWER_MASK (0xff << 8)
388#define HW_DIGPROG_MINOR_MASK 0xff
389
390#define HW_OSC_27M_CLKE_MASK BIT(4)
391#define HW_OSC_25M_CLKE_MASK BIT(2)
392#define HW_OSC_32K_SEL_MASK 0x1
393#define HW_OSC_32K_SEL_RTC 0x1
394#define HW_OSC_32K_SEL_25M_DIV800 0x0
395
396#define HW_FRAC_ARM_PLL_DIV_MASK (0x7 << 20)
397#define HW_FRAC_ARM_PLL_DIV_SHIFT 20
398#define HW_FRAC_VPU_PLL_DIV_MASK (0x7 << 16)
399#define HW_FRAC_VPU_PLL_DIV_SHIFT 16
400#define HW_FRAC_GPU_PLL_DIV_MASK (0x7 << 12)
401#define HW_FRAC_GPU_PLL_DIV_SHIFT 12
402#define HW_FRAC_VIDEO_PLL1_DIV_MASK (0x7 << 10)
403#define HW_FRAC_VIDEO_PLL1_DIV_SHIFT 10
404#define HW_FRAC_AUDIO_PLL2_DIV_MASK (0x7 << 4)
405#define HW_FRAC_AUDIO_PLL2_DIV_SHIFT 4
406#define HW_FRAC_AUDIO_PLL1_DIV_MASK 0x7
407#define HW_FRAC_AUDIO_PLL1_DIV_SHIFT 0
408
409#define HW_SSCG_VIDEO_PLL2_DIV_MASK (0x7 << 16)
410#define HW_SSCG_VIDEO_PLL2_DIV_SHIFT 16
411#define HW_SSCG_DRAM_PLL_DIV_MASK (0x7 << 14)
412#define HW_SSCG_DRAM_PLL_DIV_SHIFT 14
413#define HW_SSCG_SYSTEM_PLL3_DIV_MASK (0x7 << 8)
414#define HW_SSCG_SYSTEM_PLL3_DIV_SHIFT 8
415#define HW_SSCG_SYSTEM_PLL2_DIV_MASK (0x7 << 4)
416#define HW_SSCG_SYSTEM_PLL2_DIV_SHIFT 4
417#define HW_SSCG_SYSTEM_PLL1_DIV_MASK 0x7
418#define HW_SSCG_SYSTEM_PLL1_DIV_SHIFT 0
419
420enum frac_pll_out_val {
421 FRAC_PLL_OUT_1000M,
422 FRAC_PLL_OUT_1600M,
423};
424#endif