blob: 2c11428430912ead41a2936640da0721d7618507 [file] [log] [blame]
developer3f7834c2023-07-19 17:17:54 +08001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2022 MediaTek Inc.
4 * Author: Sam Shih <sam.shih@mediatek.com>
5 */
6
7/dts-v1/;
8#include "mt7988.dtsi"
9#include <dt-bindings/gpio/gpio.h>
10
11/ {
12 model = "mt7988-rfb";
13 compatible = "mediatek,mt7988-rfb";
14
15 chosen {
16 stdout-path = &uart0;
17 };
18
19 memory@40000000 {
20 device_type = "memory";
21 reg = <0 0x40000000 0 0x10000000>;
22 };
23
24 reg_3p3v: regulator-3p3v {
25 compatible = "regulator-fixed";
26 regulator-name = "fixed-3.3V";
27 regulator-min-microvolt = <3300000>;
28 regulator-max-microvolt = <3300000>;
29 regulator-boot-on;
30 regulator-always-on;
31 };
32
33 reg_1p8v: regulator-1p8v {
34 compatible = "regulator-fixed";
35 regulator-name = "fixed-1.8V";
36 regulator-min-microvolt = <1800000>;
37 regulator-max-microvolt = <1800000>;
38 regulator-boot-on;
39 regulator-always-on;
40 };
41};
42
43&uart0 {
44 status = "okay";
45};
46
47&i2c1 {
48 pinctrl-names = "default";
49 pinctrl-0 = <&i2c1_pins>;
50 status = "okay";
51};
52
53&eth {
54 status = "okay";
55 mediatek,gmac-id = <0>;
56 phy-mode = "usxgmii";
57 mediatek,switch = "mt7988";
58
59 fixed-link {
60 speed = <1000>;
61 full-duplex;
62 pause;
63 };
64};
65
66&pinctrl {
67 i2c1_pins: i2c1-pins {
68 mux {
69 function = "i2c";
70 groups = "i2c1_0";
71 };
72 };
73
74 pwm_pins: pwm-pins {
75 mux {
76 function = "pwm";
77 groups = "pwm0", "pwm1", "pwm2", "pwm3", "pwm4",
78 "pwm5", "pwm6", "pwm7";
79 };
80 };
81
82 spi0_pins: spi0-pins {
83 mux {
84 function = "spi";
85 groups = "spi0", "spi0_wp_hold";
86 };
87 };
88
89 spi2_pins: spi2-pins {
90 mux {
91 function = "spi";
92 groups = "spi2", "spi2_wp_hold";
93 };
94 };
95
96 mmc0_pins_default: mmc0default {
97 mux {
98 function = "flash";
99 groups = "emmc_51";
100 };
101
102 conf-cmd-dat {
103 pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
104 "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
105 "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
106 input-enable;
107 };
108
109 conf-clk {
110 pins = "EMMC_CK";
111 };
112
113 conf-dsl {
114 pins = "EMMC_DSL";
115 };
116
117 conf-rst {
118 pins = "EMMC_RSTB";
119 };
120 };
121};
122
123&pwm {
124 pinctrl-names = "default";
125 pinctrl-0 = <&pwm_pins>;
126 status = "okay";
127};
128
129&spi0 {
130 pinctrl-names = "default";
131 pinctrl-0 = <&spi0_pins>;
132 #address-cells = <1>;
133 #size-cells = <0>;
134 status = "okay";
135 must_tx;
136 enhance_timing;
137 dma_ext;
138 ipm_design;
139 support_quad;
140 tick_dly = <2>;
141 sample_sel = <0>;
142
143 spi_nand@0 {
144 compatible = "spi-nand";
145 reg = <0>;
146 spi-max-frequency = <52000000>;
147 };
148};
149
150&spi2 {
151 pinctrl-names = "default";
152 pinctrl-0 = <&spi2_pins>;
153 #address-cells = <1>;
154 #size-cells = <0>;
155 status = "okay";
156 must_tx;
157 enhance_timing;
158 dma_ext;
159 ipm_design;
160 support_quad;
161 tick_dly = <2>;
162 sample_sel = <0>;
163
164 spi_nor@0 {
165 compatible = "jedec,spi-nor";
166 reg = <0>;
167 spi-max-frequency = <52000000>;
168 };
169};
170
171&mmc0 {
172 pinctrl-names = "default";
173 pinctrl-0 = <&mmc0_pins_default>;
174 max-frequency = <52000000>;
175 bus-width = <8>;
176 cap-mmc-highspeed;
177 cap-mmc-hw-reset;
178 vmmc-supply = <&reg_3p3v>;
179 vqmmc-supply = <&reg_1p8v>;
180 non-removable;
181 status = "okay";
182};