blob: ac869296d525125343e1bd245ee701f4af3f836a [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Jin Zhengxiongae180dc2006-08-23 19:10:44 +08002/*
Kumar Gala6a6d9482009-07-28 21:49:52 -05003 * Copyright (C) Freescale Semiconductor, Inc. 2006.
Jin Zhengxiongae180dc2006-08-23 19:10:44 +08004 * Author: Jason Jin<Jason.jin@freescale.com>
5 * Zhang Wei<wei.zhang@freescale.com>
6 *
Jin Zhengxiongae180dc2006-08-23 19:10:44 +08007 * with the reference on libata and ahci drvier in kernel
Simon Glass84fac542017-06-14 21:28:37 -06008 *
9 * This driver provides a SCSI interface to SATA.
Jin Zhengxiongae180dc2006-08-23 19:10:44 +080010 */
Simon Glass655306c2020-05-10 11:39:58 -060011#include <blk.h>
Simon Glass63334482019-11-14 12:57:39 -070012#include <cpu_func.h>
Simon Glass0f2af882020-05-10 11:40:05 -060013#include <log.h>
Tom Rinidec7ea02024-05-20 13:35:03 -060014#include <time.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060015#include <linux/bitops.h>
Simon Glassdbd79542020-05-10 11:40:11 -060016#include <linux/delay.h>
Jin Zhengxiongae180dc2006-08-23 19:10:44 +080017
Jin Zhengxiongae180dc2006-08-23 19:10:44 +080018#include <command.h>
Simon Glass6f9135b2015-11-29 13:18:06 -070019#include <dm.h>
Jin Zhengxiongae180dc2006-08-23 19:10:44 +080020#include <pci.h>
21#include <asm/processor.h>
Masahiro Yamada56a931c2016-09-21 11:28:55 +090022#include <linux/errno.h>
Jin Zhengxiongae180dc2006-08-23 19:10:44 +080023#include <asm/io.h>
24#include <malloc.h>
Simon Glass2dd337a2015-09-02 17:24:58 -060025#include <memalign.h>
Simon Glassc6b44302017-06-14 21:28:46 -060026#include <pci.h>
Jin Zhengxiongae180dc2006-08-23 19:10:44 +080027#include <scsi.h>
Rob Herring83f66482013-08-24 10:10:54 -050028#include <libata.h>
Jin Zhengxiongae180dc2006-08-23 19:10:44 +080029#include <linux/ctype.h>
30#include <ahci.h>
Simon Glassc6b44302017-06-14 21:28:46 -060031#include <dm/device-internal.h>
32#include <dm/lists.h>
Jin Zhengxiongae180dc2006-08-23 19:10:44 +080033
Simon Glasse0c419b2017-06-14 21:28:34 -060034static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port);
Marc Jones49ec4b12012-10-29 05:24:02 +000035
Jon Loeligerc0b0cda2006-08-23 11:04:43 -050036#define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
37
Vadim Bendebury700f85c2012-10-29 05:23:44 +000038/*
Hung-Te Lin0f10bd42012-10-29 05:23:53 +000039 * Some controllers limit number of blocks they can read/write at once.
40 * Contemporary SSD devices work much faster if the read/write size is aligned
41 * to a power of 2. Let's set default to 128 and allowing to be overwritten if
42 * needed.
Vadim Bendebury700f85c2012-10-29 05:23:44 +000043 */
Hung-Te Lin0f10bd42012-10-29 05:23:53 +000044#ifndef MAX_SATA_BLOCKS_READ_WRITE
45#define MAX_SATA_BLOCKS_READ_WRITE 0x80
Vadim Bendebury700f85c2012-10-29 05:23:44 +000046#endif
Jin Zhengxiongae180dc2006-08-23 19:10:44 +080047
Walter Murphyefd49b42012-10-29 05:24:00 +000048/* Maximum timeouts for each event */
Rob Herring249b9372013-08-24 10:10:53 -050049#define WAIT_MS_SPINUP 20000
Mark Langsdorf2cc6e1b2015-06-05 00:58:46 +010050#define WAIT_MS_DATAIO 10000
Marc Jones49ec4b12012-10-29 05:24:02 +000051#define WAIT_MS_FLUSH 5000
Ian Campbell368989b2014-07-18 20:38:39 +010052#define WAIT_MS_LINKUP 200
Walter Murphyefd49b42012-10-29 05:24:00 +000053
Roman Kaplda326dd2019-10-14 11:21:09 +020054#define AHCI_CAP_S64A BIT(31)
55
Stefan Roesed99a30e2016-08-31 10:02:15 +020056__weak void __iomem *ahci_port_base(void __iomem *base, u32 port)
Jin Zhengxiongae180dc2006-08-23 19:10:44 +080057{
58 return base + 0x100 + (port * 0x80);
59}
60
Jin Zhengxiongae180dc2006-08-23 19:10:44 +080061#define msleep(a) udelay(a * 1000)
Jon Loeligerc0b0cda2006-08-23 11:04:43 -050062
Tang Yuantian3f262d02015-07-09 14:37:30 +080063static void ahci_dcache_flush_range(unsigned long begin, unsigned long len)
Taylor Hutt33e4c2f2012-10-29 05:23:59 +000064{
65 const unsigned long start = begin;
66 const unsigned long end = start + len;
67
68 debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end);
69 flush_dcache_range(start, end);
70}
71
72/*
73 * SATA controller DMAs to physical RAM. Ensure data from the
74 * controller is invalidated from dcache; next access comes from
75 * physical RAM.
76 */
Tang Yuantian3f262d02015-07-09 14:37:30 +080077static void ahci_dcache_invalidate_range(unsigned long begin, unsigned long len)
Taylor Hutt33e4c2f2012-10-29 05:23:59 +000078{
79 const unsigned long start = begin;
80 const unsigned long end = start + len;
81
82 debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end);
83 invalidate_dcache_range(start, end);
84}
85
86/*
87 * Ensure data for SATA controller is flushed out of dcache and
88 * written to physical memory.
89 */
90static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp)
91{
92 ahci_dcache_flush_range((unsigned long)pp->cmd_slot,
93 AHCI_PORT_PRIV_DMA_SZ);
94}
95
Tang Yuantian3f262d02015-07-09 14:37:30 +080096static int waiting_for_cmd_completed(void __iomem *offset,
Jon Loeligerc0b0cda2006-08-23 11:04:43 -050097 int timeout_msec,
98 u32 sign)
Jin Zhengxiongae180dc2006-08-23 19:10:44 +080099{
100 int i;
101 u32 status;
Jon Loeligerc0b0cda2006-08-23 11:04:43 -0500102
103 for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800104 msleep(1);
105
Jon Loeligerc0b0cda2006-08-23 11:04:43 -0500106 return (i < timeout_msec) ? 0 : -1;
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800107}
108
Marek Behún2eba1922021-05-20 13:24:21 +0200109int __weak ahci_link_up(struct ahci_uc_priv *uc_priv, int port)
Rob Herringaaec0982013-08-24 10:10:51 -0500110{
111 u32 tmp;
112 int j = 0;
Simon Glasscb875242017-06-14 21:28:33 -0600113 void __iomem *port_mmio = uc_priv->port[port].port_mmio;
Rob Herringaaec0982013-08-24 10:10:51 -0500114
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +0200115 /*
Rob Herringaaec0982013-08-24 10:10:51 -0500116 * Bring up SATA link.
117 * SATA link bringup time is usually less than 1 ms; only very
118 * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
119 */
120 while (j < WAIT_MS_LINKUP) {
121 tmp = readl(port_mmio + PORT_SCR_STAT);
122 tmp &= PORT_SCR_STAT_DET_MASK;
123 if (tmp == PORT_SCR_STAT_DET_PHYRDY)
124 return 0;
125 udelay(1000);
126 j++;
127 }
128 return 1;
129}
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800130
Ian Campbella2ebf922014-07-18 20:38:41 +0100131#ifdef CONFIG_SUNXI_AHCI
132/* The sunxi AHCI controller requires this undocumented setup */
Tang Yuantian3f262d02015-07-09 14:37:30 +0800133static void sunxi_dma_init(void __iomem *port_mmio)
Ian Campbella2ebf922014-07-18 20:38:41 +0100134{
135 clrsetbits_le32(port_mmio + PORT_P0DMACR, 0x0000ff00, 0x00004400);
136}
137#endif
138
Scott Wood16519a32015-04-17 09:19:01 -0500139int ahci_reset(void __iomem *base)
Dmitry Lifshitzcff59a72014-12-15 16:02:55 +0200140{
141 int i = 1000;
Scott Wood16519a32015-04-17 09:19:01 -0500142 u32 __iomem *host_ctl_reg = base + HOST_CTL;
Dmitry Lifshitzcff59a72014-12-15 16:02:55 +0200143 u32 tmp = readl(host_ctl_reg); /* global controller reset */
144
145 if ((tmp & HOST_RESET) == 0)
146 writel_with_flush(tmp | HOST_RESET, host_ctl_reg);
147
148 /*
149 * reset must complete within 1 second, or
150 * the hardware should be considered fried.
151 */
152 do {
153 udelay(1000);
154 tmp = readl(host_ctl_reg);
155 i--;
156 } while ((i > 0) && (tmp & HOST_RESET));
157
158 if (i == 0) {
159 printf("controller reset failed (0x%x)\n", tmp);
160 return -1;
161 }
162
163 return 0;
164}
165
Simon Glasse0c419b2017-06-14 21:28:34 -0600166static int ahci_host_init(struct ahci_uc_priv *uc_priv)
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800167{
Simon Glasse0c419b2017-06-14 21:28:34 -0600168 void __iomem *mmio = uc_priv->mmio_base;
Marc Jonesbbb57842012-10-29 05:24:01 +0000169 u32 tmp, cap_save, cmd;
Rob Herringaaec0982013-08-24 10:10:51 -0500170 int i, j, ret;
Tang Yuantian3f262d02015-07-09 14:37:30 +0800171 void __iomem *port_mmio;
Richard Gibbs8bc0ab72013-08-24 10:10:47 -0500172 u32 port_map;
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800173
Vadim Bendebury700f85c2012-10-29 05:23:44 +0000174 debug("ahci_host_init: start\n");
175
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800176 cap_save = readl(mmio + HOST_CAP);
Jon Loeligerc0b0cda2006-08-23 11:04:43 -0500177 cap_save &= ((1 << 28) | (1 << 17));
Marc Jonesbbb57842012-10-29 05:24:01 +0000178 cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800179
Simon Glasse0c419b2017-06-14 21:28:34 -0600180 ret = ahci_reset(uc_priv->mmio_base);
Dmitry Lifshitzcff59a72014-12-15 16:02:55 +0200181 if (ret)
182 return ret;
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800183
184 writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
185 writel(cap_save, mmio + HOST_CAP);
186 writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
187
Simon Glasse0c419b2017-06-14 21:28:34 -0600188 uc_priv->cap = readl(mmio + HOST_CAP);
189 uc_priv->port_map = readl(mmio + HOST_PORTS_IMPL);
190 port_map = uc_priv->port_map;
191 uc_priv->n_ports = (uc_priv->cap & 0x1f) + 1;
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800192
193 debug("cap 0x%x port_map 0x%x n_ports %d\n",
Simon Glasse0c419b2017-06-14 21:28:34 -0600194 uc_priv->cap, uc_priv->port_map, uc_priv->n_ports);
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800195
Simon Glasse0c419b2017-06-14 21:28:34 -0600196 for (i = 0; i < uc_priv->n_ports; i++) {
Richard Gibbs8bc0ab72013-08-24 10:10:47 -0500197 if (!(port_map & (1 << i)))
198 continue;
Simon Glasse0c419b2017-06-14 21:28:34 -0600199 uc_priv->port[i].port_mmio = ahci_port_base(mmio, i);
200 port_mmio = (u8 *)uc_priv->port[i].port_mmio;
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800201
202 /* make sure port is not active */
203 tmp = readl(port_mmio + PORT_CMD);
204 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
205 PORT_CMD_FIS_RX | PORT_CMD_START)) {
Stefan Reinauer7ee0e4372012-10-29 05:23:50 +0000206 debug("Port %d is active. Deactivating.\n", i);
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800207 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
208 PORT_CMD_FIS_RX | PORT_CMD_START);
209 writel_with_flush(tmp, port_mmio + PORT_CMD);
210
211 /* spec says 500 msecs for each bit, so
212 * this is slightly incorrect.
213 */
214 msleep(500);
215 }
216
Ian Campbella2ebf922014-07-18 20:38:41 +0100217#ifdef CONFIG_SUNXI_AHCI
218 sunxi_dma_init(port_mmio);
219#endif
220
Marc Jonesbbb57842012-10-29 05:24:01 +0000221 /* Add the spinup command to whatever mode bits may
222 * already be on in the command register.
223 */
224 cmd = readl(port_mmio + PORT_CMD);
Marc Jonesbbb57842012-10-29 05:24:01 +0000225 cmd |= PORT_CMD_SPIN_UP;
226 writel_with_flush(cmd, port_mmio + PORT_CMD);
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800227
Rob Herringaaec0982013-08-24 10:10:51 -0500228 /* Bring up SATA link. */
Simon Glasse0c419b2017-06-14 21:28:34 -0600229 ret = ahci_link_up(uc_priv, i);
Rob Herringaaec0982013-08-24 10:10:51 -0500230 if (ret) {
Marc Jonesbbb57842012-10-29 05:24:01 +0000231 printf("SATA link %d timeout.\n", i);
232 continue;
233 } else {
234 debug("SATA link ok.\n");
235 }
236
237 /* Clear error status */
238 tmp = readl(port_mmio + PORT_SCR_ERR);
239 if (tmp)
240 writel(tmp, port_mmio + PORT_SCR_ERR);
241
242 debug("Spinning up device on SATA port %d... ", i);
243
244 j = 0;
245 while (j < WAIT_MS_SPINUP) {
246 tmp = readl(port_mmio + PORT_TFDATA);
Rob Herring83f66482013-08-24 10:10:54 -0500247 if (!(tmp & (ATA_BUSY | ATA_DRQ)))
Marc Jonesbbb57842012-10-29 05:24:01 +0000248 break;
249 udelay(1000);
Rob Herringc4698542013-08-24 10:10:52 -0500250 tmp = readl(port_mmio + PORT_SCR_STAT);
251 tmp &= PORT_SCR_STAT_DET_MASK;
252 if (tmp == PORT_SCR_STAT_DET_PHYRDY)
253 break;
Marc Jonesbbb57842012-10-29 05:24:01 +0000254 j++;
255 }
Rob Herringc4698542013-08-24 10:10:52 -0500256
257 tmp = readl(port_mmio + PORT_SCR_STAT) & PORT_SCR_STAT_DET_MASK;
258 if (tmp == PORT_SCR_STAT_DET_COMINIT) {
259 debug("SATA link %d down (COMINIT received), retrying...\n", i);
260 i--;
261 continue;
262 }
263
Marc Jonesbbb57842012-10-29 05:24:01 +0000264 printf("Target spinup took %d ms.\n", j);
265 if (j == WAIT_MS_SPINUP)
Stefan Reinauera63341c2012-10-29 05:23:49 +0000266 debug("timeout.\n");
267 else
268 debug("ok.\n");
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800269
270 tmp = readl(port_mmio + PORT_SCR_ERR);
271 debug("PORT_SCR_ERR 0x%x\n", tmp);
272 writel(tmp, port_mmio + PORT_SCR_ERR);
273
274 /* ack any pending irq events for this port */
275 tmp = readl(port_mmio + PORT_IRQ_STAT);
276 debug("PORT_IRQ_STAT 0x%x\n", tmp);
277 if (tmp)
278 writel(tmp, port_mmio + PORT_IRQ_STAT);
279
280 writel(1 << i, mmio + HOST_IRQ_STAT);
281
Stefan Reinauer48791f12012-10-29 05:23:51 +0000282 /* register linkup ports */
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800283 tmp = readl(port_mmio + PORT_SCR_STAT);
Marc Jones49ec4b12012-10-29 05:24:02 +0000284 debug("SATA port %d status: 0x%x\n", i, tmp);
Rob Herring723a2812013-08-24 10:10:50 -0500285 if ((tmp & PORT_SCR_STAT_DET_MASK) == PORT_SCR_STAT_DET_PHYRDY)
Simon Glasse0c419b2017-06-14 21:28:34 -0600286 uc_priv->link_port_map |= (0x01 << i);
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800287 }
288
289 tmp = readl(mmio + HOST_CTL);
290 debug("HOST_CTL 0x%x\n", tmp);
291 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
292 tmp = readl(mmio + HOST_CTL);
293 debug("HOST_CTL 0x%x\n", tmp);
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800294 return 0;
295}
296
297
Simon Glasse0c419b2017-06-14 21:28:34 -0600298static void ahci_print_info(struct ahci_uc_priv *uc_priv)
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800299{
Simon Glasse0c419b2017-06-14 21:28:34 -0600300 void __iomem *mmio = uc_priv->mmio_base;
Stefan Reinauer48791f12012-10-29 05:23:51 +0000301 u32 vers, cap, cap2, impl, speed;
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800302 const char *speed_s;
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800303 const char *scc_s;
304
305 vers = readl(mmio + HOST_VERSION);
Simon Glasse0c419b2017-06-14 21:28:34 -0600306 cap = uc_priv->cap;
Stefan Reinauer48791f12012-10-29 05:23:51 +0000307 cap2 = readl(mmio + HOST_CAP2);
Simon Glasse0c419b2017-06-14 21:28:34 -0600308 impl = uc_priv->port_map;
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800309
310 speed = (cap >> 20) & 0xf;
311 if (speed == 1)
312 speed_s = "1.5";
313 else if (speed == 2)
314 speed_s = "3";
Stefan Reinauer48791f12012-10-29 05:23:51 +0000315 else if (speed == 3)
316 speed_s = "6";
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800317 else
318 speed_s = "?";
319
Rob Herringc2829ff2011-07-06 16:13:36 +0000320 scc_s = "SATA";
Jon Loeligerc0b0cda2006-08-23 11:04:43 -0500321 printf("AHCI %02x%02x.%02x%02x "
322 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
323 (vers >> 24) & 0xff,
324 (vers >> 16) & 0xff,
325 (vers >> 8) & 0xff,
326 vers & 0xff,
327 ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800328
329 printf("flags: "
Stefan Reinauer48791f12012-10-29 05:23:51 +0000330 "%s%s%s%s%s%s%s"
331 "%s%s%s%s%s%s%s"
332 "%s%s%s%s%s%s\n",
Jon Loeligerc0b0cda2006-08-23 11:04:43 -0500333 cap & (1 << 31) ? "64bit " : "",
334 cap & (1 << 30) ? "ncq " : "",
335 cap & (1 << 28) ? "ilck " : "",
336 cap & (1 << 27) ? "stag " : "",
337 cap & (1 << 26) ? "pm " : "",
338 cap & (1 << 25) ? "led " : "",
339 cap & (1 << 24) ? "clo " : "",
340 cap & (1 << 19) ? "nz " : "",
341 cap & (1 << 18) ? "only " : "",
342 cap & (1 << 17) ? "pmp " : "",
Stefan Reinauer48791f12012-10-29 05:23:51 +0000343 cap & (1 << 16) ? "fbss " : "",
Jon Loeligerc0b0cda2006-08-23 11:04:43 -0500344 cap & (1 << 15) ? "pio " : "",
345 cap & (1 << 14) ? "slum " : "",
Stefan Reinauer48791f12012-10-29 05:23:51 +0000346 cap & (1 << 13) ? "part " : "",
347 cap & (1 << 7) ? "ccc " : "",
348 cap & (1 << 6) ? "ems " : "",
349 cap & (1 << 5) ? "sxs " : "",
350 cap2 & (1 << 2) ? "apst " : "",
351 cap2 & (1 << 1) ? "nvmp " : "",
352 cap2 & (1 << 0) ? "boh " : "");
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800353}
354
Simon Glasscf01b5b2017-06-14 21:28:38 -0600355static int ahci_init_one(struct ahci_uc_priv *uc_priv, struct udevice *dev)
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800356{
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800357 int rc;
358
Simon Glasse0c419b2017-06-14 21:28:34 -0600359 uc_priv->dev = dev;
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800360
Simon Glasse0c419b2017-06-14 21:28:34 -0600361 uc_priv->host_flags = ATA_FLAG_SATA
Jon Loeligerc0b0cda2006-08-23 11:04:43 -0500362 | ATA_FLAG_NO_LEGACY
363 | ATA_FLAG_MMIO
364 | ATA_FLAG_PIO_DMA
365 | ATA_FLAG_NO_ATAPI;
Simon Glasse0c419b2017-06-14 21:28:34 -0600366 uc_priv->pio_mask = 0x1f;
367 uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800368
Simon Glassb75b15b2020-12-03 16:55:23 -0700369 struct scsi_plat *plat = dev_get_uclass_plat(dev);
Simon Glasse0c419b2017-06-14 21:28:34 -0600370 uc_priv->mmio_base = (void *)plat->base;
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800371
Simon Glasse0c419b2017-06-14 21:28:34 -0600372 debug("ahci mmio_base=0x%p\n", uc_priv->mmio_base);
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800373 /* initialize adapter */
Simon Glasse0c419b2017-06-14 21:28:34 -0600374 rc = ahci_host_init(uc_priv);
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800375 if (rc)
376 goto err_out;
377
Simon Glasse0c419b2017-06-14 21:28:34 -0600378 ahci_print_info(uc_priv);
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800379
380 return 0;
381
Jon Loeligerc0b0cda2006-08-23 11:04:43 -0500382 err_out:
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800383 return rc;
384}
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800385
386#define MAX_DATA_BYTE_COUNT (4*1024*1024)
Jon Loeligerc0b0cda2006-08-23 11:04:43 -0500387
Simon Glasse0c419b2017-06-14 21:28:34 -0600388static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port,
389 unsigned char *buf, int buf_len)
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800390{
Simon Glasse0c419b2017-06-14 21:28:34 -0600391 struct ahci_ioports *pp = &(uc_priv->port[port]);
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800392 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
Stefan Roese5b2de1c2021-04-07 09:12:35 +0200393 phys_addr_t pa = virt_to_phys(buf);
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800394 u32 sg_count;
395 int i;
396
397 sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
Jon Loeligerc0b0cda2006-08-23 11:04:43 -0500398 if (sg_count > AHCI_MAX_SG) {
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800399 printf("Error:Too much sg!\n");
400 return -1;
401 }
402
Jon Loeligerc0b0cda2006-08-23 11:04:43 -0500403 for (i = 0; i < sg_count; i++) {
Roman Kaplda326dd2019-10-14 11:21:09 +0200404 ahci_sg->addr = cpu_to_le32(lower_32_bits(pa));
405 ahci_sg->addr_hi = cpu_to_le32(upper_32_bits(pa));
406 if (ahci_sg->addr_hi && !(uc_priv->cap & AHCI_CAP_S64A)) {
407 printf("Error: DMA address too high\n");
408 return -1;
409 }
Jon Loeligerc0b0cda2006-08-23 11:04:43 -0500410 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
Stefan Roese5b2de1c2021-04-07 09:12:35 +0200411 (buf_len < MAX_DATA_BYTE_COUNT ?
412 (buf_len - 1) :
413 (MAX_DATA_BYTE_COUNT - 1)));
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800414 ahci_sg++;
415 buf_len -= MAX_DATA_BYTE_COUNT;
Stefan Roese5b2de1c2021-04-07 09:12:35 +0200416 pa += MAX_DATA_BYTE_COUNT;
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800417 }
418
419 return sg_count;
420}
421
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800422static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
423{
Stefan Roese5b2de1c2021-04-07 09:12:35 +0200424 phys_addr_t pa = virt_to_phys((void *)pp->cmd_tbl);
425
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800426 pp->cmd_slot->opts = cpu_to_le32(opts);
427 pp->cmd_slot->status = 0;
Stefan Roese5b2de1c2021-04-07 09:12:35 +0200428 pp->cmd_slot->tbl_addr = cpu_to_le32(lower_32_bits(pa));
Tang Yuantian3f262d02015-07-09 14:37:30 +0800429#ifdef CONFIG_PHYS_64BIT
Stefan Roese5b2de1c2021-04-07 09:12:35 +0200430 pp->cmd_slot->tbl_addr_hi = cpu_to_le32(upper_32_bits(pa));
Tang Yuantian3f262d02015-07-09 14:37:30 +0800431#endif
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800432}
433
Tang Yuantian3f262d02015-07-09 14:37:30 +0800434static int wait_spinup(void __iomem *port_mmio)
Bin Mengb138e912014-12-31 17:18:39 +0800435{
436 ulong start;
437 u32 tf_data;
438
439 start = get_timer(0);
440 do {
441 tf_data = readl(port_mmio + PORT_TFDATA);
442 if (!(tf_data & ATA_BUSY))
443 return 0;
444 } while (get_timer(start) < WAIT_MS_SPINUP);
445
446 return -ETIMEDOUT;
447}
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800448
Simon Glasse0c419b2017-06-14 21:28:34 -0600449static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800450{
Simon Glasse0c419b2017-06-14 21:28:34 -0600451 struct ahci_ioports *pp = &(uc_priv->port[port]);
Tang Yuantian3f262d02015-07-09 14:37:30 +0800452 void __iomem *port_mmio = pp->port_mmio;
Oleksandr Rybalko5b99a602019-08-22 12:26:56 +0200453 u64 dma_addr;
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800454 u32 port_status;
Tang Yuantian3f262d02015-07-09 14:37:30 +0800455 void __iomem *mem;
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800456
Jon Loeligerc0b0cda2006-08-23 11:04:43 -0500457 debug("Enter start port: %d\n", port);
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800458 port_status = readl(port_mmio + PORT_SCR_STAT);
Jon Loeligerc0b0cda2006-08-23 11:04:43 -0500459 debug("Port %d status: %x\n", port, port_status);
460 if ((port_status & 0xf) != 0x03) {
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800461 printf("No Link on this port!\n");
462 return -1;
463 }
464
Christian Gmeiner66aca962019-05-06 15:18:54 +0200465 mem = memalign(2048, AHCI_PORT_PRIV_DMA_SZ);
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800466 if (!mem) {
467 free(pp);
Roger Quadros7b6cb612013-11-11 16:56:37 +0200468 printf("%s: No mem for table!\n", __func__);
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800469 return -ENOMEM;
470 }
Tang Yuantian3f262d02015-07-09 14:37:30 +0800471 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800472
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800473 /*
474 * First item in chunk of DMA memory: 32-slot command table,
475 * 32 bytes each in size
476 */
Taylor Hutt3455f532012-10-29 05:23:58 +0000477 pp->cmd_slot =
478 (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem);
Tang Yuantian3f262d02015-07-09 14:37:30 +0800479 debug("cmd_slot = %p\n", pp->cmd_slot);
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800480 mem += (AHCI_CMD_SLOT_SZ + 224);
Jon Loeligerc0b0cda2006-08-23 11:04:43 -0500481
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800482 /*
483 * Second item: Received-FIS area
484 */
Taylor Hutt3455f532012-10-29 05:23:58 +0000485 pp->rx_fis = virt_to_phys((void *)mem);
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800486 mem += AHCI_RX_FIS_SZ;
Jon Loeligerc0b0cda2006-08-23 11:04:43 -0500487
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800488 /*
489 * Third item: data area for storing a single command
490 * and its scatter-gather table
491 */
Taylor Hutt3455f532012-10-29 05:23:58 +0000492 pp->cmd_tbl = virt_to_phys((void *)mem);
Tang Yuantian3f262d02015-07-09 14:37:30 +0800493 debug("cmd_tbl_dma = %lx\n", pp->cmd_tbl);
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800494
495 mem += AHCI_CMD_TBL_HDR;
Taylor Hutt3455f532012-10-29 05:23:58 +0000496 pp->cmd_tbl_sg =
497 (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800498
Oleksandr Rybalko5b99a602019-08-22 12:26:56 +0200499 dma_addr = (ulong)pp->cmd_slot;
500 writel_with_flush(dma_addr, port_mmio + PORT_LST_ADDR);
501 writel_with_flush(dma_addr >> 32, port_mmio + PORT_LST_ADDR_HI);
502 dma_addr = (ulong)pp->rx_fis;
503 writel_with_flush(dma_addr, port_mmio + PORT_FIS_ADDR);
504 writel_with_flush(dma_addr >> 32, port_mmio + PORT_FIS_ADDR_HI);
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800505
Ian Campbella2ebf922014-07-18 20:38:41 +0100506#ifdef CONFIG_SUNXI_AHCI
507 sunxi_dma_init(port_mmio);
508#endif
509
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800510 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
Jon Loeligerc0b0cda2006-08-23 11:04:43 -0500511 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
512 PORT_CMD_START, port_mmio + PORT_CMD);
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800513
Jon Loeligerc0b0cda2006-08-23 11:04:43 -0500514 debug("Exit start port %d\n", port);
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800515
Bin Mengb138e912014-12-31 17:18:39 +0800516 /*
517 * Make sure interface is not busy based on error and status
518 * information from task file data register before proceeding
519 */
520 return wait_spinup(port_mmio);
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800521}
522
523
Simon Glasse0c419b2017-06-14 21:28:34 -0600524static int ahci_device_data_io(struct ahci_uc_priv *uc_priv, u8 port, u8 *fis,
525 int fis_len, u8 *buf, int buf_len, u8 is_write)
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800526{
527
Simon Glasse0c419b2017-06-14 21:28:34 -0600528 struct ahci_ioports *pp = &(uc_priv->port[port]);
Tang Yuantian3f262d02015-07-09 14:37:30 +0800529 void __iomem *port_mmio = pp->port_mmio;
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800530 u32 opts;
531 u32 port_status;
532 int sg_count;
533
Hung-Te Lin0f10bd42012-10-29 05:23:53 +0000534 debug("Enter %s: for port %d\n", __func__, port);
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800535
Simon Glasse0c419b2017-06-14 21:28:34 -0600536 if (port > uc_priv->n_ports) {
Taylor Hutt1b1d42e2012-10-29 05:23:56 +0000537 printf("Invalid port number %d\n", port);
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800538 return -1;
539 }
540
541 port_status = readl(port_mmio + PORT_SCR_STAT);
Jon Loeligerc0b0cda2006-08-23 11:04:43 -0500542 if ((port_status & 0xf) != 0x03) {
543 debug("No Link on port %d!\n", port);
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800544 return -1;
545 }
546
547 memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
548
Simon Glasse0c419b2017-06-14 21:28:34 -0600549 sg_count = ahci_fill_sg(uc_priv, port, buf, buf_len);
Hung-Te Lin0f10bd42012-10-29 05:23:53 +0000550 opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6);
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800551 ahci_fill_cmd_slot(pp, opts);
552
Taylor Hutt33e4c2f2012-10-29 05:23:59 +0000553 ahci_dcache_flush_sata_cmd(pp);
Tang Yuantian3f262d02015-07-09 14:37:30 +0800554 ahci_dcache_flush_range((unsigned long)buf, (unsigned long)buf_len);
Taylor Hutt33e4c2f2012-10-29 05:23:59 +0000555
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800556 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
557
Walter Murphyefd49b42012-10-29 05:24:00 +0000558 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
559 WAIT_MS_DATAIO, 0x1)) {
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800560 printf("timeout exit!\n");
561 return -1;
562 }
Taylor Hutt33e4c2f2012-10-29 05:23:59 +0000563
Tang Yuantian3f262d02015-07-09 14:37:30 +0800564 ahci_dcache_invalidate_range((unsigned long)buf,
565 (unsigned long)buf_len);
Stefan Roese5b2de1c2021-04-07 09:12:35 +0200566 debug("%s: %d byte transferred.\n", __func__,
567 le32_to_cpu(pp->cmd_slot->status));
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800568
569 return 0;
570}
571
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800572static char *ata_id_strcpy(u16 *target, u16 *src, int len)
573{
574 int i;
Jon Loeligerc0b0cda2006-08-23 11:04:43 -0500575 for (i = 0; i < len / 2; i++)
Rob Herring336018392011-06-01 09:10:26 +0000576 target[i] = swab16(src[i]);
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800577 return (char *)target;
578}
579
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800580/*
581 * SCSI INQUIRY command operation.
582 */
Simon Glasscb875242017-06-14 21:28:33 -0600583static int ata_scsiop_inquiry(struct ahci_uc_priv *uc_priv,
584 struct scsi_cmd *pccb)
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800585{
Rob Herring9855a232013-08-24 10:10:48 -0500586 static const u8 hdr[] = {
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800587 0,
588 0,
Jon Loeligerc0b0cda2006-08-23 11:04:43 -0500589 0x5, /* claim SPC-3 version compatibility */
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800590 2,
591 95 - 4,
592 };
593 u8 fis[20];
Roger Quadrosda3976e2014-04-01 17:26:40 +0300594 u16 *idbuf;
Roger Quadrosff56ee12013-11-11 16:56:38 +0200595 ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS);
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800596 u8 port;
597
598 /* Clean ccb data buffer */
599 memset(pccb->pdata, 0, pccb->datalen);
600
601 memcpy(pccb->pdata, hdr, sizeof(hdr));
602
Jon Loeligerc0b0cda2006-08-23 11:04:43 -0500603 if (pccb->datalen <= 35)
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800604 return 0;
605
Taylor Hutt54d0f552012-10-29 05:23:55 +0000606 memset(fis, 0, sizeof(fis));
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800607 /* Construct the FIS */
Jon Loeligerc0b0cda2006-08-23 11:04:43 -0500608 fis[0] = 0x27; /* Host to device FIS. */
609 fis[1] = 1 << 7; /* Command FIS. */
Rob Herring83f66482013-08-24 10:10:54 -0500610 fis[2] = ATA_CMD_ID_ATA; /* Command byte. */
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800611
612 /* Read id from sata */
613 port = pccb->target;
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800614
Simon Glass6268e7c2023-01-17 10:47:53 -0700615 /* If this port number is not valid, give up */
616 if (!(uc_priv->port_map & (1 << port))) {
617 debug("Port %x not valid in map %x\n", port, uc_priv->port_map);
618 return -ENODEV;
619 }
620
Simon Glasse0c419b2017-06-14 21:28:34 -0600621 if (ahci_device_data_io(uc_priv, port, (u8 *)&fis, sizeof(fis),
622 (u8 *)tmpid, ATA_ID_WORDS * 2, 0)) {
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800623 debug("scsi_ahci: SCSI inquiry command failure.\n");
624 return -EIO;
625 }
626
Simon Glasscb875242017-06-14 21:28:33 -0600627 if (!uc_priv->ataid[port]) {
628 uc_priv->ataid[port] = malloc(ATA_ID_WORDS * 2);
629 if (!uc_priv->ataid[port]) {
Roger Quadrosda3976e2014-04-01 17:26:40 +0300630 printf("%s: No memory for ataid[port]\n", __func__);
631 return -ENOMEM;
632 }
633 }
634
Simon Glasscb875242017-06-14 21:28:33 -0600635 idbuf = uc_priv->ataid[port];
Roger Quadrosda3976e2014-04-01 17:26:40 +0300636
637 memcpy(idbuf, tmpid, ATA_ID_WORDS * 2);
638 ata_swap_buf_le16(idbuf, ATA_ID_WORDS);
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800639
640 memcpy(&pccb->pdata[8], "ATA ", 8);
Roger Quadrosda3976e2014-04-01 17:26:40 +0300641 ata_id_strcpy((u16 *)&pccb->pdata[16], &idbuf[ATA_ID_PROD], 16);
642 ata_id_strcpy((u16 *)&pccb->pdata[32], &idbuf[ATA_ID_FW_REV], 4);
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800643
Rob Herring83f66482013-08-24 10:10:54 -0500644#ifdef DEBUG
Roger Quadrosda3976e2014-04-01 17:26:40 +0300645 ata_dump_id(idbuf);
Rob Herring83f66482013-08-24 10:10:54 -0500646#endif
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800647 return 0;
648}
649
650
651/*
Hung-Te Lin0f10bd42012-10-29 05:23:53 +0000652 * SCSI READ10/WRITE10 command operation.
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800653 */
Simon Glasse0c419b2017-06-14 21:28:34 -0600654static int ata_scsiop_read_write(struct ahci_uc_priv *uc_priv,
655 struct scsi_cmd *pccb, u8 is_write)
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800656{
Mark Langsdorf5ed06fc2015-06-05 00:58:45 +0100657 lbaint_t lba = 0;
Vadim Bendebury700f85c2012-10-29 05:23:44 +0000658 u16 blocks = 0;
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800659 u8 fis[20];
Vadim Bendebury700f85c2012-10-29 05:23:44 +0000660 u8 *user_buffer = pccb->pdata;
661 u32 user_buffer_size = pccb->datalen;
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800662
Vadim Bendebury700f85c2012-10-29 05:23:44 +0000663 /* Retrieve the base LBA number from the ccb structure. */
Mark Langsdorf5ed06fc2015-06-05 00:58:45 +0100664 if (pccb->cmd[0] == SCSI_READ16) {
665 memcpy(&lba, pccb->cmd + 2, 8);
666 lba = be64_to_cpu(lba);
667 } else {
668 u32 temp;
669 memcpy(&temp, pccb->cmd + 2, 4);
670 lba = be32_to_cpu(temp);
671 }
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800672
Vadim Bendebury700f85c2012-10-29 05:23:44 +0000673 /*
Mark Langsdorf5ed06fc2015-06-05 00:58:45 +0100674 * Retrieve the base LBA number and the block count from
675 * the ccb structure.
Vadim Bendebury700f85c2012-10-29 05:23:44 +0000676 *
677 * For 10-byte and 16-byte SCSI R/W commands, transfer
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800678 * length 0 means transfer 0 block of data.
679 * However, for ATA R/W commands, sector count 0 means
680 * 256 or 65536 sectors, not 0 sectors as in SCSI.
681 *
682 * WARNING: one or two older ATA drives treat 0 as 0...
683 */
Mark Langsdorf5ed06fc2015-06-05 00:58:45 +0100684 if (pccb->cmd[0] == SCSI_READ16)
685 blocks = (((u16)pccb->cmd[13]) << 8) | ((u16) pccb->cmd[14]);
686 else
687 blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]);
Vadim Bendebury700f85c2012-10-29 05:23:44 +0000688
Mark Langsdorf5ed06fc2015-06-05 00:58:45 +0100689 debug("scsi_ahci: %s %u blocks starting from lba 0x" LBAFU "\n",
690 is_write ? "write" : "read", blocks, lba);
Vadim Bendebury700f85c2012-10-29 05:23:44 +0000691
692 /* Preset the FIS */
Taylor Hutt54d0f552012-10-29 05:23:55 +0000693 memset(fis, 0, sizeof(fis));
Vadim Bendebury700f85c2012-10-29 05:23:44 +0000694 fis[0] = 0x27; /* Host to device FIS. */
695 fis[1] = 1 << 7; /* Command FIS. */
Hung-Te Lin0f10bd42012-10-29 05:23:53 +0000696 /* Command byte (read/write). */
Walter Murphyd1cb64b2012-10-29 05:24:03 +0000697 fis[2] = is_write ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800698
Vadim Bendebury700f85c2012-10-29 05:23:44 +0000699 while (blocks) {
700 u16 now_blocks; /* number of blocks per iteration */
701 u32 transfer_size; /* number of bytes per iteration */
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800702
Masahiro Yamadadb204642014-11-07 03:03:31 +0900703 now_blocks = min((u16)MAX_SATA_BLOCKS_READ_WRITE, blocks);
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800704
Rob Herring83f66482013-08-24 10:10:54 -0500705 transfer_size = ATA_SECT_SIZE * now_blocks;
Vadim Bendebury700f85c2012-10-29 05:23:44 +0000706 if (transfer_size > user_buffer_size) {
707 printf("scsi_ahci: Error: buffer too small.\n");
708 return -EIO;
709 }
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800710
Mark Langsdorf5ed06fc2015-06-05 00:58:45 +0100711 /*
712 * LBA48 SATA command but only use 32bit address range within
713 * that (unless we've enabled 64bit LBA support). The next
714 * smaller command range (28bit) is too small.
Walter Murphyd1cb64b2012-10-29 05:24:03 +0000715 */
Vadim Bendebury700f85c2012-10-29 05:23:44 +0000716 fis[4] = (lba >> 0) & 0xff;
717 fis[5] = (lba >> 8) & 0xff;
718 fis[6] = (lba >> 16) & 0xff;
Walter Murphyd1cb64b2012-10-29 05:24:03 +0000719 fis[7] = 1 << 6; /* device reg: set LBA mode */
720 fis[8] = ((lba >> 24) & 0xff);
Mark Langsdorf5ed06fc2015-06-05 00:58:45 +0100721#ifdef CONFIG_SYS_64BIT_LBA
722 if (pccb->cmd[0] == SCSI_READ16) {
723 fis[9] = ((lba >> 32) & 0xff);
724 fis[10] = ((lba >> 40) & 0xff);
725 }
726#endif
727
Walter Murphyd1cb64b2012-10-29 05:24:03 +0000728 fis[3] = 0xe0; /* features */
Vadim Bendebury700f85c2012-10-29 05:23:44 +0000729
730 /* Block (sector) count */
731 fis[12] = (now_blocks >> 0) & 0xff;
732 fis[13] = (now_blocks >> 8) & 0xff;
733
Hung-Te Lin0f10bd42012-10-29 05:23:53 +0000734 /* Read/Write from ahci */
Simon Glasse0c419b2017-06-14 21:28:34 -0600735 if (ahci_device_data_io(uc_priv, pccb->target, (u8 *)&fis,
736 sizeof(fis), user_buffer, transfer_size,
Hung-Te Lin0f10bd42012-10-29 05:23:53 +0000737 is_write)) {
738 debug("scsi_ahci: SCSI %s10 command failure.\n",
739 is_write ? "WRITE" : "READ");
Vadim Bendebury700f85c2012-10-29 05:23:44 +0000740 return -EIO;
741 }
Marc Jones49ec4b12012-10-29 05:24:02 +0000742
743 /* If this transaction is a write, do a following flush.
744 * Writes in u-boot are so rare, and the logic to know when is
745 * the last write and do a flush only there is sufficiently
746 * difficult. Just do a flush after every write. This incurs,
747 * usually, one extra flush when the rare writes do happen.
748 */
749 if (is_write) {
Simon Glasse0c419b2017-06-14 21:28:34 -0600750 if (-EIO == ata_io_flush(uc_priv, pccb->target))
Marc Jones49ec4b12012-10-29 05:24:02 +0000751 return -EIO;
752 }
Vadim Bendebury700f85c2012-10-29 05:23:44 +0000753 user_buffer += transfer_size;
754 user_buffer_size -= transfer_size;
755 blocks -= now_blocks;
756 lba += now_blocks;
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800757 }
758
759 return 0;
760}
761
762
763/*
764 * SCSI READ CAPACITY10 command operation.
765 */
Simon Glasscb875242017-06-14 21:28:33 -0600766static int ata_scsiop_read_capacity10(struct ahci_uc_priv *uc_priv,
767 struct scsi_cmd *pccb)
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800768{
Kumar Gala8a190652009-07-13 09:24:00 -0500769 u32 cap;
Rob Herring83f66482013-08-24 10:10:54 -0500770 u64 cap64;
Gabe Blackdd2c7342012-10-29 05:23:54 +0000771 u32 block_size;
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800772
Simon Glasscb875242017-06-14 21:28:33 -0600773 if (!uc_priv->ataid[pccb->target]) {
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800774 printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
Jon Loeligerc0b0cda2006-08-23 11:04:43 -0500775 "\tNo ATA info!\n"
Vagrant Cascadianbeb288b2015-11-24 14:46:24 -0800776 "\tPlease run SCSI command INQUIRY first!\n");
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800777 return -EPERM;
778 }
779
Simon Glasscb875242017-06-14 21:28:33 -0600780 cap64 = ata_id_n_sectors(uc_priv->ataid[pccb->target]);
Rob Herring83f66482013-08-24 10:10:54 -0500781 if (cap64 > 0x100000000ULL)
782 cap64 = 0xffffffff;
Gabe Blackdd2c7342012-10-29 05:23:54 +0000783
Rob Herring83f66482013-08-24 10:10:54 -0500784 cap = cpu_to_be32(cap64);
Gabe Blackdd2c7342012-10-29 05:23:54 +0000785 memcpy(pccb->pdata, &cap, sizeof(cap));
786
787 block_size = cpu_to_be32((u32)512);
788 memcpy(&pccb->pdata[4], &block_size, 4);
789
790 return 0;
791}
792
793
794/*
795 * SCSI READ CAPACITY16 command operation.
796 */
Simon Glasscb875242017-06-14 21:28:33 -0600797static int ata_scsiop_read_capacity16(struct ahci_uc_priv *uc_priv,
798 struct scsi_cmd *pccb)
Gabe Blackdd2c7342012-10-29 05:23:54 +0000799{
800 u64 cap;
801 u64 block_size;
802
Simon Glasscb875242017-06-14 21:28:33 -0600803 if (!uc_priv->ataid[pccb->target]) {
Gabe Blackdd2c7342012-10-29 05:23:54 +0000804 printf("scsi_ahci: SCSI READ CAPACITY16 command failure. "
805 "\tNo ATA info!\n"
Vagrant Cascadianbeb288b2015-11-24 14:46:24 -0800806 "\tPlease run SCSI command INQUIRY first!\n");
Gabe Blackdd2c7342012-10-29 05:23:54 +0000807 return -EPERM;
808 }
809
Simon Glasscb875242017-06-14 21:28:33 -0600810 cap = ata_id_n_sectors(uc_priv->ataid[pccb->target]);
Gabe Blackdd2c7342012-10-29 05:23:54 +0000811 cap = cpu_to_be64(cap);
Kumar Gala8a190652009-07-13 09:24:00 -0500812 memcpy(pccb->pdata, &cap, sizeof(cap));
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800813
Gabe Blackdd2c7342012-10-29 05:23:54 +0000814 block_size = cpu_to_be64((u64)512);
815 memcpy(&pccb->pdata[8], &block_size, 8);
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800816
817 return 0;
818}
819
820
821/*
822 * SCSI TEST UNIT READY command operation.
823 */
Simon Glasscb875242017-06-14 21:28:33 -0600824static int ata_scsiop_test_unit_ready(struct ahci_uc_priv *uc_priv,
825 struct scsi_cmd *pccb)
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800826{
Simon Glasscb875242017-06-14 21:28:33 -0600827 return (uc_priv->ataid[pccb->target]) ? 0 : -EPERM;
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800828}
829
Jon Loeligerc0b0cda2006-08-23 11:04:43 -0500830
Simon Glass23123c62017-06-14 21:28:42 -0600831static int ahci_scsi_exec(struct udevice *dev, struct scsi_cmd *pccb)
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800832{
Tom Rini15a2ab52023-10-27 20:59:51 -0400833 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev->parent);
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800834 int ret;
835
Jon Loeligerc0b0cda2006-08-23 11:04:43 -0500836 switch (pccb->cmd[0]) {
Mark Langsdorf5ed06fc2015-06-05 00:58:45 +0100837 case SCSI_READ16:
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800838 case SCSI_READ10:
Simon Glasse0c419b2017-06-14 21:28:34 -0600839 ret = ata_scsiop_read_write(uc_priv, pccb, 0);
Hung-Te Lin0f10bd42012-10-29 05:23:53 +0000840 break;
841 case SCSI_WRITE10:
Simon Glasse0c419b2017-06-14 21:28:34 -0600842 ret = ata_scsiop_read_write(uc_priv, pccb, 1);
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800843 break;
Gabe Blackdd2c7342012-10-29 05:23:54 +0000844 case SCSI_RD_CAPAC10:
Simon Glasscb875242017-06-14 21:28:33 -0600845 ret = ata_scsiop_read_capacity10(uc_priv, pccb);
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800846 break;
Gabe Blackdd2c7342012-10-29 05:23:54 +0000847 case SCSI_RD_CAPAC16:
Simon Glasscb875242017-06-14 21:28:33 -0600848 ret = ata_scsiop_read_capacity16(uc_priv, pccb);
Gabe Blackdd2c7342012-10-29 05:23:54 +0000849 break;
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800850 case SCSI_TST_U_RDY:
Simon Glasscb875242017-06-14 21:28:33 -0600851 ret = ata_scsiop_test_unit_ready(uc_priv, pccb);
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800852 break;
853 case SCSI_INQUIRY:
Simon Glasscb875242017-06-14 21:28:33 -0600854 ret = ata_scsiop_inquiry(uc_priv, pccb);
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800855 break;
856 default:
857 printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
Simon Glassa140e862017-06-14 21:28:44 -0600858 return -ENOTSUPP;
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800859 }
860
Jon Loeligerc0b0cda2006-08-23 11:04:43 -0500861 if (ret) {
862 debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
Simon Glassa140e862017-06-14 21:28:44 -0600863 return ret;
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800864 }
Simon Glassa140e862017-06-14 21:28:44 -0600865 return 0;
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800866
867}
868
Simon Glass0a47bbb2017-06-14 21:28:36 -0600869static int ahci_start_ports(struct ahci_uc_priv *uc_priv)
870{
871 u32 linkmap;
872 int i;
873
874 linkmap = uc_priv->link_port_map;
875
Tuomas Tynkkynen69a38992018-09-13 01:28:54 +0300876 for (i = 0; i < uc_priv->n_ports; i++) {
Simon Glass0a47bbb2017-06-14 21:28:36 -0600877 if (((linkmap >> i) & 0x01)) {
878 if (ahci_port_start(uc_priv, (u8) i)) {
879 printf("Can not start port %d\n", i);
880 continue;
881 }
882 }
883 }
884
885 return 0;
886}
Simon Glass84fac542017-06-14 21:28:37 -0600887
Michal Simek2d72d3c2017-11-02 15:53:56 +0100888int ahci_init_one_dm(struct udevice *dev)
Simon Glass84fac542017-06-14 21:28:37 -0600889{
Simon Glasscf01b5b2017-06-14 21:28:38 -0600890 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
891
892 return ahci_init_one(uc_priv, dev);
Simon Glass84fac542017-06-14 21:28:37 -0600893}
Simon Glass84fac542017-06-14 21:28:37 -0600894
Michal Simek2d72d3c2017-11-02 15:53:56 +0100895int ahci_start_ports_dm(struct udevice *dev)
Simon Glass84fac542017-06-14 21:28:37 -0600896{
Simon Glasscf01b5b2017-06-14 21:28:38 -0600897 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
Simon Glass84fac542017-06-14 21:28:37 -0600898
899 return ahci_start_ports(uc_priv);
900}
Jin Zhengxiongae180dc2006-08-23 19:10:44 +0800901
Marc Jones49ec4b12012-10-29 05:24:02 +0000902/*
903 * In the general case of generic rotating media it makes sense to have a
904 * flush capability. It probably even makes sense in the case of SSDs because
905 * one cannot always know for sure what kind of internal cache/flush mechanism
906 * is embodied therein. At first it was planned to invoke this after the last
907 * write to disk and before rebooting. In practice, knowing, a priori, which
908 * is the last write is difficult. Because writing to the disk in u-boot is
909 * very rare, this flush command will be invoked after every block write.
910 */
Simon Glasse0c419b2017-06-14 21:28:34 -0600911static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port)
Marc Jones49ec4b12012-10-29 05:24:02 +0000912{
913 u8 fis[20];
Simon Glasse0c419b2017-06-14 21:28:34 -0600914 struct ahci_ioports *pp = &(uc_priv->port[port]);
Tang Yuantian3f262d02015-07-09 14:37:30 +0800915 void __iomem *port_mmio = pp->port_mmio;
Marc Jones49ec4b12012-10-29 05:24:02 +0000916 u32 cmd_fis_len = 5; /* five dwords */
917
918 /* Preset the FIS */
919 memset(fis, 0, 20);
920 fis[0] = 0x27; /* Host to device FIS. */
921 fis[1] = 1 << 7; /* Command FIS. */
Walter Murphyd1cb64b2012-10-29 05:24:03 +0000922 fis[2] = ATA_CMD_FLUSH_EXT;
Marc Jones49ec4b12012-10-29 05:24:02 +0000923
924 memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
925 ahci_fill_cmd_slot(pp, cmd_fis_len);
Tang Yuantian93b99e02016-04-14 16:21:00 +0800926 ahci_dcache_flush_sata_cmd(pp);
Marc Jones49ec4b12012-10-29 05:24:02 +0000927 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
928
929 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
930 WAIT_MS_FLUSH, 0x1)) {
931 debug("scsi_ahci: flush command timeout on port %d.\n", port);
932 return -EIO;
933 }
934
935 return 0;
936}
937
Simon Glass23123c62017-06-14 21:28:42 -0600938static int ahci_scsi_bus_reset(struct udevice *dev)
939{
940 /* Not implemented */
941
942 return 0;
943}
944
Simon Glassc6b44302017-06-14 21:28:46 -0600945int ahci_bind_scsi(struct udevice *ahci_dev, struct udevice **devp)
946{
947 struct udevice *dev;
948 int ret;
949
950 ret = device_bind_driver(ahci_dev, "ahci_scsi", "ahci_scsi", &dev);
951 if (ret)
952 return ret;
953 *devp = dev;
954
955 return 0;
956}
957
Simon Glass89e7d972017-07-04 13:31:18 -0600958int ahci_probe_scsi(struct udevice *ahci_dev, ulong base)
Simon Glassc6b44302017-06-14 21:28:46 -0600959{
Simon Glassc6b44302017-06-14 21:28:46 -0600960 struct ahci_uc_priv *uc_priv;
Simon Glassb75b15b2020-12-03 16:55:23 -0700961 struct scsi_plat *uc_plat;
Simon Glassc6b44302017-06-14 21:28:46 -0600962 struct udevice *dev;
963 int ret;
964
965 device_find_first_child(ahci_dev, &dev);
966 if (!dev)
967 return -ENODEV;
Simon Glass71fa5b42020-12-03 16:55:18 -0700968 uc_plat = dev_get_uclass_plat(dev);
Simon Glass89e7d972017-07-04 13:31:18 -0600969 uc_plat->base = base;
Simon Glassc6b44302017-06-14 21:28:46 -0600970 uc_plat->max_lun = 1;
971 uc_plat->max_id = 2;
Simon Glass89e7d972017-07-04 13:31:18 -0600972
973 uc_priv = dev_get_uclass_priv(ahci_dev);
Simon Glassc6b44302017-06-14 21:28:46 -0600974 ret = ahci_init_one(uc_priv, dev);
975 if (ret)
976 return ret;
977 ret = ahci_start_ports(uc_priv);
978 if (ret)
979 return ret;
Simon Glassc6b44302017-06-14 21:28:46 -0600980
Park, Aiden1d5a1aa2019-08-20 16:47:42 +0000981 /*
982 * scsi_scan_dev() scans devices up-to the number of max_id.
983 * Update max_id if the number of detected ports exceeds max_id.
984 * This allows SCSI to scan all detected ports.
985 */
986 uc_plat->max_id = max_t(unsigned long, uc_priv->n_ports,
987 uc_plat->max_id);
Suneel Garapati2dcfb242021-03-25 17:07:36 -0700988 /* If port count is less than max_id, update max_id */
989 if (uc_priv->n_ports < uc_plat->max_id)
990 uc_plat->max_id = uc_priv->n_ports;
Park, Aiden1d5a1aa2019-08-20 16:47:42 +0000991
Simon Glassc6b44302017-06-14 21:28:46 -0600992 return 0;
993}
994
Simon Glass89e7d972017-07-04 13:31:18 -0600995int ahci_probe_scsi_pci(struct udevice *ahci_dev)
996{
997 ulong base;
Christian Gmeinere6d1f6a2023-04-11 17:07:02 +0200998 u16 vendor, device, cmd;
999
1000 /* Enable bus mastering */
1001 dm_pci_read_config16(ahci_dev, PCI_COMMAND, &cmd);
1002 cmd |= PCI_COMMAND_MASTER;
1003 dm_pci_write_config16(ahci_dev, PCI_COMMAND, cmd);
Simon Glass89e7d972017-07-04 13:31:18 -06001004
Andrew Scull58c61022022-04-21 16:11:10 +00001005 base = (ulong)dm_pci_map_bar(ahci_dev, PCI_BASE_ADDRESS_5, 0, 0,
Andrew Scull6520c822022-04-21 16:11:13 +00001006 PCI_REGION_TYPE, PCI_REGION_MEM);
Simon Glass89e7d972017-07-04 13:31:18 -06001007
Suneel Garapatib2708552019-10-19 17:48:25 -07001008 /*
1009 * Note:
1010 * Right now, we have only one quirk here, which is not enough to
1011 * introduce a new Kconfig option to select this. Once we have more
1012 * quirks in this AHCI code, we should add a Kconfig option for
1013 * this though.
1014 */
1015 dm_pci_read_config16(ahci_dev, PCI_VENDOR_ID, &vendor);
1016 dm_pci_read_config16(ahci_dev, PCI_DEVICE_ID, &device);
1017
1018 if (vendor == PCI_VENDOR_ID_CAVIUM &&
1019 device == PCI_DEVICE_ID_CAVIUM_SATA)
Andrew Scull6520c822022-04-21 16:11:13 +00001020 base = (uintptr_t)dm_pci_map_bar(ahci_dev, PCI_BASE_ADDRESS_0,
1021 0, 0, PCI_REGION_TYPE,
Suneel Garapatib2708552019-10-19 17:48:25 -07001022 PCI_REGION_MEM);
Simon Glass89e7d972017-07-04 13:31:18 -06001023 return ahci_probe_scsi(ahci_dev, base);
1024}
Simon Glass89e7d972017-07-04 13:31:18 -06001025
Simon Glassc4dfa892017-06-14 21:28:43 -06001026struct scsi_ops scsi_ops = {
1027 .exec = ahci_scsi_exec,
1028 .bus_reset = ahci_scsi_bus_reset,
1029};
Simon Glassc6b44302017-06-14 21:28:46 -06001030
1031U_BOOT_DRIVER(ahci_scsi) = {
1032 .name = "ahci_scsi",
1033 .id = UCLASS_SCSI,
1034 .ops = &scsi_ops,
1035};