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git01.mediatek.com / filogic / uboot / c361582b9f83ec8b81139efbd5a09a90bc827664 / . / board / cssi / cmpc885 / sdram.c
blob: 11a50c3a52d62a3c5fe3563860c70e910f3b48a0 [file] [log] [blame]
Christophe Leroy1fc46f52022-10-14 12:54:50 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2020 CS Group
4 * Charles Frey <charles.frey@c-s.fr>
5 */
6
Christophe Leroy1fc46f52022-10-14 12:54:50 +0200[diff] [blame]7#include <linux/sizes.h>
8#include <linux/delay.h>
9#include <init.h>
10#include <asm/io.h>
11#include <mpc8xx.h>
12#include <watchdog.h>
Christophe Leroyf4ecd0f2023-11-06 19:12:05 +0100[diff] [blame]13#include <asm/ppc.h>
14#include <asm/immap_8xx.h>
Christophe Leroy1fc46f52022-10-14 12:54:50 +0200[diff] [blame]15
16DECLARE_GLOBAL_DATA_PTR;
17
18#define ADDR_CPLD_R_TYPE ((unsigned char __iomem *)CONFIG_CPLD_BASE + 3)
19
20#define _NOT_USED_ 0xFFFFEC04
21
22static const uint sdram_table[] = {
23 /* DRAM - single read. (offset 0 in upm RAM) */
24 0x0F0CEC04, 0x0FFFEC04, 0x00AF2C04, 0x0FFFEC00,
25 0x0FFCE004, 0xFFFFEC05, _NOT_USED_, _NOT_USED_,
26
27 /* DRAM - burst read. (offset 8 in upm RAM) */
28 0x0F0CEC04, 0x0FFFEC04, 0x00AF2C04, 0x00FFEC00,
29 0x00FFEC00, 0x00FFEC00, 0x0FFCE000, 0x1FFFEC05,
30
31 /* DRAM - Precharge all banks. (offset 16 in upm RAM) */
32 _NOT_USED_, 0x0FFCE004, 0x1FFFEC05, _NOT_USED_,
33
34 /* DRAM - NOP. (offset 20 in upm RAM) */
35 0x1FFFEC05, _NOT_USED_, _NOT_USED_, _NOT_USED_,
36
37 /* DRAM - single write. (offset 24 in upm RAM) */
38 0x0F0CEC04, 0x0FFFEC00, 0x00AF2004, 0x0FFFEC04,
39 0x0FFCE004, 0x0FFFEC04, 0xFFFFEC05, _NOT_USED_,
40
41 /* DRAM - burst write. (offset 32 in upm RAM) */
42 0x0F0CEC04, 0x0FFFEC00, 0x00AF2000, 0x00FFEC00,
43 0x00FFEC00, 0x00FFEC04, 0x0FFFEC04, 0x0FFCE004,
44 0x1FFFEC05, _NOT_USED_, _NOT_USED_, _NOT_USED_,
45 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
46
47 /* refresh (offset 48 in upm RAM) */
48 0x0FFDE404, 0x0FFEAC04, 0x0FFD6C84, 0x0FFFEC04,
49 0x0FFFEC04, 0x0FFFEC04, 0x0FFFEC04, 0x1FFFEC85,
50
51 /* init (offset 56 in upm RAM) */
52 0x0FEEA874, 0x0FBD6474, 0x1FFFEC45, _NOT_USED_,
53
54 /* exception. (offset 60 in upm RAM) */
55 0x0FFCE004, 0xFFFFEC05, _NOT_USED_, _NOT_USED_
56};
57
58/* SDRAM initialization */
59int dram_init(void)
60{
61 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
62 memctl8xx_t __iomem *memctl = &immap->im_memctl;
63 u32 max_size, mamr;
64 u8 val;
65
66 printf("UPMA init for SDRAM (CAS latency 2), ");
67 printf("init address 0x%08x, size ", (int)dram_init);
68
69 /* Verify the SDRAM size of the board */
70 val = (in_8(ADDR_CPLD_R_TYPE) & 0x30) >> 4;
71
72 if (val == 0x03 || val == 0x00) {
73 max_size = 64 * SZ_1M; /* 64 Mo of SDRAM */
74 mamr = 0x20104000;
75 } else {
76 max_size = 128 * SZ_1M; /* 128 Mo of SDRAM */
77 mamr = 0x20206000;
78 }
79
80 /* Configure CS1 */
81 out_be32(&memctl->memc_or1,
82 ~(max_size - 1) | OR_CSNT_SAM | OR_ACS_DIV2);
83 out_be32(&memctl->memc_br1, CFG_SYS_SDRAM_BASE | BR_MS_UPMA | BR_V);
84
85 /* Configure UPMA for CS1 */
86 upmconfig(UPMA, (uint *)sdram_table, ARRAY_SIZE(sdram_table));
87
88 out_be16(&memctl->memc_mptpr, MPTPR_PTP_DIV32);
89 /* disable refresh */
90 out_be32(&memctl->memc_mamr, mamr);
91 udelay(100);
92
93 /* NOP to maintain DQM high */
94 out_be32(&memctl->memc_mcr, 0x80002114);
95 udelay(200);
96
97 out_be32(&memctl->memc_mcr, 0x80002111); /* PRECHARGE cmd */
98 out_be32(&memctl->memc_mcr, 0x80002830); /* AUTO REFRESH cmd */
99 out_be32(&memctl->memc_mar, 0x00000088);
100 out_be32(&memctl->memc_mcr, 0x80002138);
101
102 /* Enable refresh */
103 setbits_be32(&memctl->memc_mamr, MAMR_PTAE);
104
105 gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, max_size);
106
107 return 0;
108}