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git01.mediatek.com / filogic / uboot / c332fca5f07b95024ba6e894778a6a8883702c58 / . / include / power / max8997_pmic.h
blob: 956eebb9685cec33a3d5ca3f23bd75e2a488dc8e [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Łukasz Majewskie2ec82c2012-03-29 01:29:17 +0000[diff] [blame]2/*
3 * Copyright (C) 2011 Samsung Electronics
4 * Lukasz Majewski <l.majewski@samsung.com>
Łukasz Majewskie2ec82c2012-03-29 01:29:17 +0000[diff] [blame]5 */
6
7#ifndef __MAX8997_PMIC_H_
8#define __MAX8997_PMIC_H_
9
10/* MAX 8997 registers */
11enum {
12 MAX8997_REG_PMIC_ID0 = 0x00,
13 MAX8997_REG_PMIC_ID1 = 0x01,
14 MAX8997_REG_INTSRC = 0x02,
15 MAX8997_REG_INT1 = 0x03,
16 MAX8997_REG_INT2 = 0x04,
17 MAX8997_REG_INT3 = 0x05,
18 MAX8997_REG_INT4 = 0x06,
19
20 MAX8997_REG_INT1MSK = 0x08,
21 MAX8997_REG_INT2MSK = 0x09,
22 MAX8997_REG_INT3MSK = 0x0a,
23 MAX8997_REG_INT4MSK = 0x0b,
24
25 MAX8997_REG_STATUS1 = 0x0d,
26 MAX8997_REG_STATUS2 = 0x0e,
27 MAX8997_REG_STATUS3 = 0x0f,
28 MAX8997_REG_STATUS4 = 0x10,
29
30 MAX8997_REG_MAINCON1 = 0x13,
31 MAX8997_REG_MAINCON2 = 0x14,
32 MAX8997_REG_BUCKRAMP = 0x15,
33
34 MAX8997_REG_BUCK1CTRL = 0x18,
35 MAX8997_REG_BUCK1DVS1 = 0x19,
36 MAX8997_REG_BUCK1DVS2 = 0x1a,
37 MAX8997_REG_BUCK1DVS3 = 0x1b,
38 MAX8997_REG_BUCK1DVS4 = 0x1c,
39 MAX8997_REG_BUCK1DVS5 = 0x1d,
40 MAX8997_REG_BUCK1DVS6 = 0x1e,
41 MAX8997_REG_BUCK1DVS7 = 0x1f,
42 MAX8997_REG_BUCK1DVS8 = 0x20,
43 MAX8997_REG_BUCK2CTRL = 0x21,
44 MAX8997_REG_BUCK2DVS1 = 0x22,
45 MAX8997_REG_BUCK2DVS2 = 0x23,
46 MAX8997_REG_BUCK2DVS3 = 0x24,
47 MAX8997_REG_BUCK2DVS4 = 0x25,
48 MAX8997_REG_BUCK2DVS5 = 0x26,
49 MAX8997_REG_BUCK2DVS6 = 0x27,
50 MAX8997_REG_BUCK2DVS7 = 0x28,
51 MAX8997_REG_BUCK2DVS8 = 0x29,
52 MAX8997_REG_BUCK3CTRL = 0x2a,
53 MAX8997_REG_BUCK3DVS = 0x2b,
54 MAX8997_REG_BUCK4CTRL = 0x2c,
55 MAX8997_REG_BUCK4DVS = 0x2d,
56 MAX8997_REG_BUCK5CTRL = 0x2e,
57 MAX8997_REG_BUCK5DVS1 = 0x2f,
58 MAX8997_REG_BUCK5DVS2 = 0x30,
59 MAX8997_REG_BUCK5DVS3 = 0x31,
60 MAX8997_REG_BUCK5DVS4 = 0x32,
61 MAX8997_REG_BUCK5DVS5 = 0x33,
62 MAX8997_REG_BUCK5DVS6 = 0x34,
63 MAX8997_REG_BUCK5DVS7 = 0x35,
64 MAX8997_REG_BUCK5DVS8 = 0x36,
65 MAX8997_REG_BUCK6CTRL = 0x37,
66 MAX8997_REG_BUCK6BPSKIPCTRL = 0x38,
67 MAX8997_REG_BUCK7CTRL = 0x39,
68 MAX8997_REG_BUCK7DVS = 0x3a,
69 MAX8997_REG_LDO1CTRL = 0x3b,
70 MAX8997_REG_LDO2CTRL = 0x3c,
71 MAX8997_REG_LDO3CTRL = 0x3d,
72 MAX8997_REG_LDO4CTRL = 0x3e,
73 MAX8997_REG_LDO5CTRL = 0x3f,
74 MAX8997_REG_LDO6CTRL = 0x40,
75 MAX8997_REG_LDO7CTRL = 0x41,
76 MAX8997_REG_LDO8CTRL = 0x42,
77 MAX8997_REG_LDO9CTRL = 0x43,
78 MAX8997_REG_LDO10CTRL = 0x44,
79 MAX8997_REG_LDO11CTRL = 0x45,
80 MAX8997_REG_LDO12CTRL = 0x46,
81 MAX8997_REG_LDO13CTRL = 0x47,
82 MAX8997_REG_LDO14CTRL = 0x48,
83 MAX8997_REG_LDO15CTRL = 0x49,
84 MAX8997_REG_LDO16CTRL = 0x4a,
85 MAX8997_REG_LDO17CTRL = 0x4b,
86 MAX8997_REG_LDO18CTRL = 0x4c,
87 MAX8997_REG_LDO21CTRL = 0x4d,
88
89 MAX8997_REG_MBCCTRL1 = 0x50,
90 MAX8997_REG_MBCCTRL2 = 0x51,
91 MAX8997_REG_MBCCTRL3 = 0x52,
92 MAX8997_REG_MBCCTRL4 = 0x53,
93 MAX8997_REG_MBCCTRL5 = 0x54,
94 MAX8997_REG_MBCCTRL6 = 0x55,
95 MAX8997_REG_OTPCGHCVS = 0x56,
96
Łukasz Majewski1c6dba12012-11-13 03:21:55 +0000[diff] [blame]97 MAX8997_REG_SAFEOUTCTRL = 0x5a,
Łukasz Majewskie2ec82c2012-03-29 01:29:17 +0000[diff] [blame]98
99 MAX8997_REG_LBCNFG1 = 0x5e,
100 MAX8997_REG_LBCNFG2 = 0x5f,
101 MAX8997_REG_BBCCTRL = 0x60,
102
103 MAX8997_REG_FLASH1_CUR = 0x63, /* 0x63 ~ 0x6e for FLASH */
104 MAX8997_REG_FLASH2_CUR = 0x64,
105 MAX8997_REG_MOVIE_CUR = 0x65,
106 MAX8997_REG_GSMB_CUR = 0x66,
107 MAX8997_REG_BOOST_CNTL = 0x67,
108 MAX8997_REG_LEN_CNTL = 0x68,
109 MAX8997_REG_FLASH_CNTL = 0x69,
110 MAX8997_REG_WDT_CNTL = 0x6a,
111 MAX8997_REG_MAXFLASH1 = 0x6b,
112 MAX8997_REG_MAXFLASH2 = 0x6c,
113 MAX8997_REG_FLASHSTATUS = 0x6d,
114 MAX8997_REG_FLASHSTATUSMASK = 0x6e,
115
116 MAX8997_REG_GPIOCNTL1 = 0x70,
117 MAX8997_REG_GPIOCNTL2 = 0x71,
118 MAX8997_REG_GPIOCNTL3 = 0x72,
119 MAX8997_REG_GPIOCNTL4 = 0x73,
120 MAX8997_REG_GPIOCNTL5 = 0x74,
121 MAX8997_REG_GPIOCNTL6 = 0x75,
122 MAX8997_REG_GPIOCNTL7 = 0x76,
123 MAX8997_REG_GPIOCNTL8 = 0x77,
124 MAX8997_REG_GPIOCNTL9 = 0x78,
125 MAX8997_REG_GPIOCNTL10 = 0x79,
126 MAX8997_REG_GPIOCNTL11 = 0x7a,
127 MAX8997_REG_GPIOCNTL12 = 0x7b,
128
129 MAX8997_REG_LDO1CONFIG = 0x80,
130 MAX8997_REG_LDO2CONFIG = 0x81,
131 MAX8997_REG_LDO3CONFIG = 0x82,
132 MAX8997_REG_LDO4CONFIG = 0x83,
133 MAX8997_REG_LDO5CONFIG = 0x84,
134 MAX8997_REG_LDO6CONFIG = 0x85,
135 MAX8997_REG_LDO7CONFIG = 0x86,
136 MAX8997_REG_LDO8CONFIG = 0x87,
137 MAX8997_REG_LDO9CONFIG = 0x88,
138 MAX8997_REG_LDO10CONFIG = 0x89,
139 MAX8997_REG_LDO11CONFIG = 0x8a,
140 MAX8997_REG_LDO12CONFIG = 0x8b,
141 MAX8997_REG_LDO13CONFIG = 0x8c,
142 MAX8997_REG_LDO14CONFIG = 0x8d,
143 MAX8997_REG_LDO15CONFIG = 0x8e,
144 MAX8997_REG_LDO16CONFIG = 0x8f,
145 MAX8997_REG_LDO17CONFIG = 0x90,
146 MAX8997_REG_LDO18CONFIG = 0x91,
147 MAX8997_REG_LDO21CONFIG = 0x92,
148
149 MAX8997_REG_DVSOKTIMER1 = 0x97,
150 MAX8997_REG_DVSOKTIMER2 = 0x98,
151 MAX8997_REG_DVSOKTIMER4 = 0x99,
152 MAX8997_REG_DVSOKTIMER5 = 0x9a,
153
154 PMIC_NUM_OF_REGS = 0x9b,
155};
156
Łukasz Majewski1c6dba12012-11-13 03:21:55 +0000[diff] [blame]157#define ACTDISSAFEO1 (1 << 4)
158#define ACTDISSAFEO2 (1 << 5)
Łukasz Majewskie2ec82c2012-03-29 01:29:17 +0000[diff] [blame]159#define ENSAFEOUT1 (1 << 6)
160#define ENSAFEOUT2 (1 << 7)
161
Łukasz Majewskid72e0ae2012-11-13 03:22:05 +0000[diff] [blame]162#define ENBUCK (1 << 0)
163#define ACTIVE_DISCHARGE (1 << 3)
164#define GNSLCT (1 << 2)
165#define LDO_ADE (1 << 1)
166#define SAFEOUT_4_85V 0x00
167#define SAFEOUT_4_90V 0x01
168#define SAFEOUT_4_95V 0x02
169#define SAFEOUT_3_30V 0x03
170
Łukasz Majewski1c6dba12012-11-13 03:21:55 +0000[diff] [blame]171/* Charger */
Łukasz Majewski1c6dba12012-11-13 03:21:55 +0000[diff] [blame]172#define DETBAT (1 << 2)
173#define MBCICHFCSET (1 << 4)
174#define MBCHOSTEN (1 << 6)
175#define VCHGR_FC (1 << 7)
176
177#define CHARGER_MIN_CURRENT 200
178#define CHARGER_MAX_CURRENT 950
179#define CHARGER_CURRENT_RESOLUTION 50
180
Łukasz Majewskie2ec82c2012-03-29 01:29:17 +0000[diff] [blame]181#define MAX8997_I2C_ADDR (0xCC >> 1)
182#define MAX8997_RTC_ADDR (0x0C >> 1)
183#define MAX8997_MUIC_ADDR (0x4A >> 1)
184#define MAX8997_FG_ADDR (0x6C >> 1)
185
186enum {
187 LDO_OFF = 0,
188 LDO_ON = 1,
189
190 DIS_LDO = (0x00 << 6),
191 EN_LDO = (0x3 << 6),
192};
193
Łukasz Majewski57e91112012-11-13 03:22:04 +0000[diff] [blame]194#define MAX8997_LDO_MAX_VAL 0x3F
195unsigned char max8997_reg_ldo(int uV);
Łukasz Majewskie2ec82c2012-03-29 01:29:17 +0000[diff] [blame]196#endif /* __MAX8997_PMIC_H_ */