blob: b34c080b4ba0cc608bd568a2f324c471db128bd1 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Ying Zhang8876a512014-10-31 18:06:18 +08002/*
3 * Copyright 2014 Freescale Semiconductor, Inc.
Meenakshi Aggarwal8a03b0d2020-12-04 20:17:28 +05304 * Copyright 2020 NXP
Ying Zhang8876a512014-10-31 18:06:18 +08005 */
6
7#ifndef __VID_H_
8#define __VID_H_
9
Stephen Carlsonc3301a22021-02-08 11:11:29 +010010/* IR36021 command codes */
Ying Zhang8876a512014-10-31 18:06:18 +080011#define IR36021_LOOP1_MANUAL_ID_OFFSET 0x6A
12#define IR36021_LOOP1_VOUT_OFFSET 0x9A
13#define IR36021_MFR_ID_OFFSET 0x92
14#define IR36021_MFR_ID 0x43
Stephen Carlsonc3301a22021-02-08 11:11:29 +010015#define IR36021_INTEL_MODE_OFFSET 0x14
Ying Zhang7ad5eff2016-01-22 12:15:12 +080016#define IR36021_MODE_MASK 0x20
17#define IR36021_INTEL_MODE 0x00
18#define IR36021_AMD_MODE 0x20
Ying Zhang8876a512014-10-31 18:06:18 +080019
Stephen Carlsonc3301a22021-02-08 11:11:29 +010020/* Step the IR regulator in 5mV increments */
Ying Zhang8876a512014-10-31 18:06:18 +080021#define IR_VDD_STEP_DOWN 5
22#define IR_VDD_STEP_UP 5
Biwen Li71ecd382020-10-12 20:07:35 +080023
24/* LTC3882 */
25#define PMBUS_CMD_WRITE_PROTECT 0x10
26/*
27 * WRITE_PROTECT command supported values
28 * 0x80: Disable all writes except WRITE_PROTECT, PAGE,
29 * STORE_USER_ALL and MFR_EE_UNLOCK commands.
30 * 0x40: Disable all writes except WRITE_PROTECT, PAGE, STORE_USER_ALL,
31 * MFR_EE_UNLOCK, OPERATION, CLEAR_PEAKS and CLEAR_FAULTS commands.
32 * Individual faults can also be cleared by writing a 1 to the
33 * respective status bit.
34 * 0x20: Disable all writes except WRITE_PROTECT, PAGE, STORE_USER_ ALL,
35 * MFR_EE_UNLOCK, OPERATION, CLEAR_PEAKS, CLEAR_FAULTS, ON_OFF_CONFIG
36 * and VOUT_COMMAND commands. Individual faults can be cleared by
37 * writing a 1 to the respective status bit.
38 * 0x00: Enables write to all commands
39 */
40#define EN_WRITE_ALL_CMD (0)
41
Meenakshi Aggarwal8a03b0d2020-12-04 20:17:28 +053042#ifdef CONFIG_TARGET_LX2160ARDB
43/* The lowest and highest voltage allowed*/
44#define VDD_MV_MIN 775
45#define VDD_MV_MAX 855
46#endif
47
48#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
49/* The lowest and highest voltage allowed*/
50#define VDD_MV_MIN 775
51#define VDD_MV_MAX 925
52#endif
53
Meenakshi Aggarwal8a03b0d2020-12-04 20:17:28 +053054/* PM Bus commands code for LTC3882*/
55#define PWM_CHANNEL0 0x0
56#define PMBUS_CMD_PAGE 0x0
57#define PMBUS_CMD_READ_VOUT 0x8B
Stephen Carlsonc3301a22021-02-08 11:11:29 +010058#define PMBUS_CMD_VOUT_MODE 0x20
Meenakshi Aggarwal8a03b0d2020-12-04 20:17:28 +053059#define PMBUS_CMD_VOUT_COMMAND 0x21
60#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05
61
Stephen Carlsonc3301a22021-02-08 11:11:29 +010062#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) || \
63defined(CONFIG_TARGET_LX2160ARDB)
Meenakshi Aggarwal8a03b0d2020-12-04 20:17:28 +053064/* Voltage monitor on channel 2*/
65#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
66#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
67#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
68#define I2C_VOL_MONITOR_ADDR 0x63
69#define I2C_MUX_CH_VOL_MONITOR 0xA
70#endif
71
Ying Zhang8876a512014-10-31 18:06:18 +080072int adjust_vdd(ulong vdd_override);
Stephen Carlsonc3301a22021-02-08 11:11:29 +010073u16 soc_get_fuse_vid(int vid_index);
Ying Zhang8876a512014-10-31 18:06:18 +080074
75#endif /* __VID_H_ */