Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Stefan Roese | cb41033 | 2016-05-25 08:13:45 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2016 Stefan Roese <sr@denx.de> |
Stefan Roese | cb41033 | 2016-05-25 08:13:45 +0200 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <common.h> |
| 7 | #include <dm.h> |
| 8 | #include <fdtdec.h> |
Simon Glass | 6980b6b | 2019-11-14 12:57:45 -0700 | [diff] [blame] | 9 | #include <init.h> |
Simon Glass | 274e0b0 | 2020-05-10 11:39:56 -0600 | [diff] [blame] | 10 | #include <asm/cache.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 11 | #include <asm/global_data.h> |
Simon Glass | 6b9f010 | 2020-05-10 11:40:06 -0600 | [diff] [blame] | 12 | #include <asm/ptrace.h> |
Masahiro Yamada | 75f82d0 | 2018-03-05 01:20:11 +0900 | [diff] [blame] | 13 | #include <linux/libfdt.h> |
Baruch Siach | 3692741 | 2018-11-11 12:31:04 +0200 | [diff] [blame] | 14 | #include <linux/sizes.h> |
Konstantin Porotchkin | cc5d612 | 2017-04-05 17:42:33 +0300 | [diff] [blame] | 15 | #include <pci.h> |
Stefan Roese | cb41033 | 2016-05-25 08:13:45 +0200 | [diff] [blame] | 16 | #include <asm/io.h> |
| 17 | #include <asm/system.h> |
| 18 | #include <asm/arch/cpu.h> |
| 19 | #include <asm/arch/soc.h> |
| 20 | #include <asm/armv8/mmu.h> |
| 21 | |
| 22 | DECLARE_GLOBAL_DATA_PTR; |
| 23 | |
| 24 | /* |
Stefan Roese | b720ff4 | 2016-11-11 08:18:44 +0100 | [diff] [blame] | 25 | * Not all memory is mapped in the MMU. So we need to restrict the |
| 26 | * memory size so that U-Boot does not try to access it. Also, the |
| 27 | * internal registers are located at 0xf000.0000 - 0xffff.ffff. |
| 28 | * Currently only 2GiB are mapped for system memory. This is what |
| 29 | * we pass to the U-Boot subsystem here. |
| 30 | */ |
| 31 | #define USABLE_RAM_SIZE 0x80000000 |
| 32 | |
| 33 | ulong board_get_usable_ram_top(ulong total_size) |
| 34 | { |
| 35 | if (gd->ram_size > USABLE_RAM_SIZE) |
| 36 | return USABLE_RAM_SIZE; |
| 37 | |
| 38 | return gd->ram_size; |
| 39 | } |
| 40 | |
| 41 | /* |
Stefan Roese | cb41033 | 2016-05-25 08:13:45 +0200 | [diff] [blame] | 42 | * On ARMv8, MBus is not configured in U-Boot. To enable compilation |
| 43 | * of the already implemented drivers, lets add a dummy version of |
| 44 | * this function so that linking does not fail. |
| 45 | */ |
| 46 | const struct mbus_dram_target_info *mvebu_mbus_dram_info(void) |
| 47 | { |
| 48 | return NULL; |
| 49 | } |
| 50 | |
Marek Behún | 22a0ce3 | 2018-12-17 16:10:09 +0100 | [diff] [blame] | 51 | __weak int dram_init_banksize(void) |
Stefan Roese | cb41033 | 2016-05-25 08:13:45 +0200 | [diff] [blame] | 52 | { |
Baruch Siach | 3692741 | 2018-11-11 12:31:04 +0200 | [diff] [blame] | 53 | if (CONFIG_IS_ENABLED(ARMADA_8K)) |
Marek Behún | e577cc3 | 2020-04-08 19:25:18 +0200 | [diff] [blame] | 54 | return a8k_dram_init_banksize(); |
Marek Behún | f9d5e73 | 2020-04-08 19:25:19 +0200 | [diff] [blame] | 55 | else if (CONFIG_IS_ENABLED(ARMADA_3700)) |
| 56 | return a3700_dram_init_banksize(); |
Baruch Siach | 3692741 | 2018-11-11 12:31:04 +0200 | [diff] [blame] | 57 | else |
Marek Behún | e577cc3 | 2020-04-08 19:25:18 +0200 | [diff] [blame] | 58 | return fdtdec_setup_memory_banksize(); |
Stefan Roese | cb41033 | 2016-05-25 08:13:45 +0200 | [diff] [blame] | 59 | } |
| 60 | |
Marek Behún | 22a0ce3 | 2018-12-17 16:10:09 +0100 | [diff] [blame] | 61 | __weak int dram_init(void) |
Stefan Roese | cb41033 | 2016-05-25 08:13:45 +0200 | [diff] [blame] | 62 | { |
Baruch Siach | 3692741 | 2018-11-11 12:31:04 +0200 | [diff] [blame] | 63 | if (CONFIG_IS_ENABLED(ARMADA_8K)) { |
| 64 | gd->ram_size = a8k_dram_scan_ap_sz(); |
| 65 | if (gd->ram_size != 0) |
| 66 | return 0; |
| 67 | } |
| 68 | |
Marek Behún | f9d5e73 | 2020-04-08 19:25:19 +0200 | [diff] [blame] | 69 | if (CONFIG_IS_ENABLED(ARMADA_3700)) |
| 70 | return a3700_dram_init(); |
| 71 | |
Siva Durga Prasad Paladugu | b3d55ea | 2018-07-16 15:56:11 +0530 | [diff] [blame] | 72 | if (fdtdec_setup_mem_size_base() != 0) |
Stefan Roese | cb41033 | 2016-05-25 08:13:45 +0200 | [diff] [blame] | 73 | return -EINVAL; |
| 74 | |
Simon Glass | 2f949c3 | 2017-03-31 08:40:32 -0600 | [diff] [blame] | 75 | return 0; |
Stefan Roese | cb41033 | 2016-05-25 08:13:45 +0200 | [diff] [blame] | 76 | } |
| 77 | |
| 78 | int arch_cpu_init(void) |
| 79 | { |
| 80 | /* Nothing to do (yet) */ |
| 81 | return 0; |
| 82 | } |
| 83 | |
| 84 | int arch_early_init_r(void) |
| 85 | { |
| 86 | struct udevice *dev; |
| 87 | int ret; |
Stefan Roese | e13461b | 2016-10-25 18:12:40 +0200 | [diff] [blame] | 88 | int i; |
| 89 | |
| 90 | /* |
| 91 | * Loop over all MISC uclass drivers to call the comphy code |
| 92 | * and init all CP110 devices enabled in the DT |
| 93 | */ |
| 94 | i = 0; |
| 95 | while (1) { |
| 96 | /* Call the comphy code via the MISC uclass driver */ |
| 97 | ret = uclass_get_device(UCLASS_MISC, i++, &dev); |
Stefan Roese | cb41033 | 2016-05-25 08:13:45 +0200 | [diff] [blame] | 98 | |
Stefan Roese | e13461b | 2016-10-25 18:12:40 +0200 | [diff] [blame] | 99 | /* We're done, once no further CP110 device is found */ |
| 100 | if (ret) |
| 101 | break; |
Stefan Roese | cb41033 | 2016-05-25 08:13:45 +0200 | [diff] [blame] | 102 | } |
| 103 | |
| 104 | /* Cause the SATA device to do its early init */ |
| 105 | uclass_first_device(UCLASS_AHCI, &dev); |
| 106 | |
Konstantin Porotchkin | cc5d612 | 2017-04-05 17:42:33 +0300 | [diff] [blame] | 107 | #ifdef CONFIG_DM_PCI |
| 108 | /* Trigger PCIe devices detection */ |
| 109 | pci_init(); |
| 110 | #endif |
| 111 | |
Stefan Roese | cb41033 | 2016-05-25 08:13:45 +0200 | [diff] [blame] | 112 | return 0; |
| 113 | } |