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git01.mediatek.com / filogic / uboot / c31f901b7c095a32d4809608d6598ecd8fee50e4 / . / dts / upstream / src / arm64 / freescale / imx8dxl-evk.dts
blob: 2412ab145c0661300ecf57a725e1881d5556061d [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019~2020, 2022 NXP
4 */
5
6/dts-v1/;
7
8#include "imx8dxl.dtsi"
9
10/ {
11 model = "Freescale i.MX8DXL EVK";
12 compatible = "fsl,imx8dxl-evk", "fsl,imx8dxl";
13
14 aliases {
15 i2c2 = &i2c2;
16 mmc0 = &usdhc1;
17 mmc1 = &usdhc2;
18 serial0 = &lpuart0;
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]19 serial1 = &lpuart1;
20 serial6 = &cm40_lpuart;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]21 };
22
23 chosen {
24 stdout-path = &lpuart0;
25 };
26
27 memory@80000000 {
28 device_type = "memory";
29 reg = <0x00000000 0x80000000 0 0x40000000>;
30 };
31
32 reserved-memory {
33 #address-cells = <2>;
34 #size-cells = <2>;
35 ranges;
36
37 /*
38 * Memory reserved for optee usage. Please do not use.
39 * This will be automatically added to dtb if OP-TEE is installed.
40 * optee@96000000 {
41 * reg = <0 0x96000000 0 0x2000000>;
42 * no-map;
43 * };
44 */
45
46 /* global autoconfigured region for contiguous allocations */
47 linux,cma {
48 compatible = "shared-dma-pool";
49 reusable;
50 size = <0 0x14000000>;
51 alloc-ranges = <0 0x98000000 0 0x14000000>;
52 linux,cma-default;
53 };
54 };
55
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]56 m2_uart1_sel: regulator-m2uart1sel {
57 compatible = "regulator-fixed";
58 regulator-min-microvolt = <3300000>;
59 regulator-max-microvolt = <3300000>;
60 regulator-name = "m2_uart1_sel";
61 gpio = <&pca6416_1 6 GPIO_ACTIVE_HIGH>;
62 enable-active-high;
63 regulator-always-on;
64 };
65
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]66 mux3_en: regulator-0 {
67 compatible = "regulator-fixed";
68 regulator-min-microvolt = <3300000>;
69 regulator-max-microvolt = <3300000>;
70 regulator-name = "mux3_en";
71 gpio = <&pca6416_2 8 GPIO_ACTIVE_LOW>;
72 regulator-always-on;
73 };
74
75 reg_fec1_sel: regulator-1 {
76 compatible = "regulator-fixed";
77 regulator-name = "fec1_supply";
78 regulator-min-microvolt = <3300000>;
79 regulator-max-microvolt = <3300000>;
80 gpio = <&pca6416_1 11 GPIO_ACTIVE_LOW>;
81 regulator-always-on;
82 status = "disabled";
83 };
84
85 reg_fec1_io: regulator-2 {
86 compatible = "regulator-fixed";
87 regulator-name = "fec1_io_supply";
88 regulator-min-microvolt = <1800000>;
89 regulator-max-microvolt = <1800000>;
90 gpio = <&max7322 0 GPIO_ACTIVE_HIGH>;
91 enable-active-high;
92 regulator-always-on;
93 status = "disabled";
94 };
95
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]96 reg_can0_stby: regulator-4 {
97 compatible = "regulator-fixed";
98 regulator-name = "can0-stby";
99 regulator-min-microvolt = <3300000>;
100 regulator-max-microvolt = <3300000>;
101 gpio = <&pca6416_3 0 GPIO_ACTIVE_HIGH>;
102 enable-active-high;
103 };
104
105 reg_can1_stby: regulator-5 {
106 compatible = "regulator-fixed";
107 regulator-name = "can1-stby";
108 regulator-min-microvolt = <3300000>;
109 regulator-max-microvolt = <3300000>;
110 gpio = <&pca6416_3 1 GPIO_ACTIVE_HIGH>;
111 enable-active-high;
112 };
113
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]114 reg_usdhc2_vmmc: regulator-3 {
115 compatible = "regulator-fixed";
116 regulator-name = "SD1_SPWR";
117 regulator-min-microvolt = <3000000>;
118 regulator-max-microvolt = <3000000>;
119 gpio = <&lsio_gpio4 30 GPIO_ACTIVE_HIGH>;
120 enable-active-high;
121 off-on-delay-us = <3480>;
122 };
123
124 reg_vref_1v8: regulator-adc-vref {
125 compatible = "regulator-fixed";
126 regulator-name = "vref_1v8";
127 regulator-min-microvolt = <1800000>;
128 regulator-max-microvolt = <1800000>;
129 };
130
131 mii_select: regulator-4 {
132 compatible = "regulator-fixed";
133 regulator-name = "mii-select";
134 regulator-min-microvolt = <3300000>;
135 regulator-max-microvolt = <3300000>;
136 gpio = <&scu_gpio 6 GPIO_ACTIVE_HIGH>;
137 enable-active-high;
138 regulator-always-on;
139 };
140};
141
142&adc0 {
143 vref-supply = <&reg_vref_1v8>;
144 status = "okay";
145};
146
147&eqos {
148 pinctrl-names = "default";
149 pinctrl-0 = <&pinctrl_eqos>;
150 phy-mode = "rgmii-id";
151 phy-handle = <&ethphy0>;
152 nvmem-cells = <&fec_mac1>;
153 nvmem-cell-names = "mac-address";
154 status = "okay";
155
156 mdio {
157 compatible = "snps,dwmac-mdio";
158 #address-cells = <1>;
159 #size-cells = <0>;
160
161 ethphy0: ethernet-phy@0 {
162 compatible = "ethernet-phy-ieee802.3-c22";
163 reg = <0>;
164 eee-broken-1000t;
165 qca,disable-smarteee;
166 qca,disable-hibernation-mode;
167 reset-gpios = <&pca6416_1 2 GPIO_ACTIVE_LOW>;
168 reset-assert-us = <20>;
169 reset-deassert-us = <200000>;
170 vddio-supply = <&vddio0>;
171
172 vddio0: vddio-regulator {
173 regulator-min-microvolt = <1800000>;
174 regulator-max-microvolt = <1800000>;
175 };
176 };
177 };
178};
179
180/*
181 * fec1 shares the some PINs with usdhc2.
182 * by default usdhc2 is enabled in this dts.
183 * Please disable usdhc2 to enable fec1
184 */
185&fec1 {
186 pinctrl-names = "default";
187 pinctrl-0 = <&pinctrl_fec1>;
188 phy-mode = "rgmii-txid";
189 phy-handle = <&ethphy1>;
190 fsl,magic-packet;
191 rx-internal-delay-ps = <2000>;
192 nvmem-cells = <&fec_mac0>;
193 nvmem-cell-names = "mac-address";
194 status = "disabled";
195
196 mdio {
197 #address-cells = <1>;
198 #size-cells = <0>;
199
200 ethphy1: ethernet-phy@1 {
201 compatible = "ethernet-phy-ieee802.3-c22";
202 reg = <1>;
203 reset-gpios = <&pca6416_1 0 GPIO_ACTIVE_LOW>;
204 reset-assert-us = <10000>;
205 qca,disable-smarteee;
206 vddio-supply = <&vddio1>;
207
208 vddio1: vddio-regulator {
209 regulator-min-microvolt = <1800000>;
210 regulator-max-microvolt = <1800000>;
211 };
212 };
213 };
214};
215
216&flexspi0 {
217 pinctrl-names = "default";
218 pinctrl-0 = <&pinctrl_flexspi0>;
219 status = "okay";
220
221 mt35xu512aba0: flash@0 {
222 reg = <0>;
223 #address-cells = <1>;
224 #size-cells = <1>;
225 compatible = "jedec,spi-nor";
226 spi-max-frequency = <133000000>;
227 spi-tx-bus-width = <8>;
228 spi-rx-bus-width = <8>;
229 };
230};
231
232&i2c2 {
233 #address-cells = <1>;
234 #size-cells = <0>;
235 clock-frequency = <100000>;
236 pinctrl-names = "default";
237 pinctrl-0 = <&pinctrl_i2c2>;
238 status = "okay";
239
240 pca6416_1: gpio@20 {
241 compatible = "ti,tca6416";
242 reg = <0x20>;
243 gpio-controller;
244 #gpio-cells = <2>;
245 };
246
247 pca6416_2: gpio@21 {
248 compatible = "ti,tca6416";
249 reg = <0x21>;
250 gpio-controller;
251 #gpio-cells = <2>;
252 };
253
254 pca9548_1: i2c-mux@70 {
255 compatible = "nxp,pca9548";
256 #address-cells = <1>;
257 #size-cells = <0>;
258 reg = <0x70>;
259
260 i2c@0 {
261 #address-cells = <1>;
262 #size-cells = <0>;
263 reg = <0x0>;
264
265 max7322: gpio@68 {
266 compatible = "maxim,max7322";
267 reg = <0x68>;
268 gpio-controller;
269 #gpio-cells = <2>;
270 status = "disabled";
271 };
272 };
273
274 i2c@4 {
275 #address-cells = <1>;
276 #size-cells = <0>;
277 reg = <0x4>;
278 };
279
280 i2c@5 {
281 #address-cells = <1>;
282 #size-cells = <0>;
283 reg = <0x5>;
284 };
285
286 i2c@6 {
287 #address-cells = <1>;
288 #size-cells = <0>;
289 reg = <0x6>;
290 };
291 };
292};
293
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]294&i2c3 {
295 #address-cells = <1>;
296 #size-cells = <0>;
297 clock-frequency = <100000>;
298 pinctrl-names = "default";
299 pinctrl-0 = <&pinctrl_i2c3>;
300 status = "okay";
301
302 pca6416_3: gpio@20 {
303 compatible = "ti,tca6416";
304 reg = <0x20>;
305 gpio-controller;
306 #gpio-cells = <2>;
307 interrupt-parent = <&lsio_gpio2>;
308 interrupts = <5 IRQ_TYPE_EDGE_RISING>;
309 };
310
311 pca9548_2: i2c-mux@70 {
312 compatible = "nxp,pca9548";
313 reg = <0x70>;
314 #address-cells = <1>;
315 #size-cells = <0>;
316
317 i2c@0 {
318 #address-cells = <1>;
319 #size-cells = <0>;
320 reg = <0x0>;
321 };
322
323 i2c@1 {
324 #address-cells = <1>;
325 #size-cells = <0>;
326 reg = <0x1>;
327 };
328
329 i2c@2 {
330 #address-cells = <1>;
331 #size-cells = <0>;
332 reg = <0x2>;
333 };
334
335 i2c@3 {
336 #address-cells = <1>;
337 #size-cells = <0>;
338 reg = <0x3>;
339 };
340
341 i2c@4 {
342 #address-cells = <1>;
343 #size-cells = <0>;
344 reg = <0x4>;
345 };
346 };
347};
348
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]349&lpuart0 {
350 pinctrl-names = "default";
351 pinctrl-0 = <&pinctrl_lpuart0>;
352 status = "okay";
353};
354
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]355&lpuart1 {
356 pinctrl-names = "default";
357 pinctrl-0 = <&pinctrl_lpuart1>;
358 status = "okay";
359};
360
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]361&flexcan2 {
362 pinctrl-names = "default";
363 pinctrl-0 = <&pinctrl_flexcan2>;
364 xceiver-supply = <&reg_can0_stby>;
365 status = "okay";
366};
367
368&flexcan3 {
369 pinctrl-names = "default";
370 pinctrl-0 = <&pinctrl_flexcan3>;
371 xceiver-supply = <&reg_can1_stby>;
372 status = "okay";
373};
374
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]375&cm40_intmux {
376 status = "disabled";
377};
378
379&cm40_lpuart {
380 pinctrl-names = "default";
381 pinctrl-0 = <&pinctrl_cm40_lpuart>;
382 status = "disabled";
383};
384
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]385&lsio_gpio4 {
386 status = "okay";
387};
388
389&lsio_gpio5 {
390 status = "okay";
391};
392
393&thermal_zones {
394 pmic-thermal {
395 polling-delay-passive = <250>;
396 polling-delay = <2000>;
397 thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
398
399 trips {
400 pmic_alert0: trip0 {
401 temperature = <110000>;
402 hysteresis = <2000>;
403 type = "passive";
404 };
405
406 pmic_crit0: trip1 {
407 temperature = <125000>;
408 hysteresis = <2000>;
409 type = "critical";
410 };
411 };
412
413 cooling-maps {
414 map0 {
415 trip = <&pmic_alert0>;
416 cooling-device =
417 <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
418 <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
419 };
420 };
421 };
422};
423
424&usbphy1 {
425 /* USB eye diagram tests result */
426 fsl,tx-d-cal = <114>;
427 status = "okay";
428};
429
430&usbotg1 {
431 pinctrl-names = "default";
432 pinctrl-0 = <&pinctrl_usbotg1>;
433 srp-disable;
434 hnp-disable;
435 adp-disable;
436 power-active-high;
437 disable-over-current;
438 status = "okay";
439};
440
441&usbphy2 {
442 /* USB eye diagram tests result */
443 fsl,tx-d-cal = <111>;
444 status = "okay";
445};
446
447&usbotg2 {
448 pinctrl-names = "default";
449 pinctrl-0 = <&pinctrl_usbotg2>;
450 srp-disable;
451 hnp-disable;
452 adp-disable;
453 power-active-high;
454 disable-over-current;
455 status = "okay";
456};
457
458&usdhc1 {
459 pinctrl-names = "default";
460 pinctrl-0 = <&pinctrl_usdhc1>;
461 bus-width = <8>;
462 no-sd;
463 no-sdio;
464 non-removable;
465 status = "okay";
466};
467
468&usdhc2 {
469 pinctrl-names = "default";
470 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
471 bus-width = <4>;
472 vmmc-supply = <&reg_usdhc2_vmmc>;
473 cd-gpios = <&lsio_gpio5 1 GPIO_ACTIVE_LOW>;
474 wp-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>;
475 status = "okay";
476};
477
478&lpspi3 {
479 fsl,spi-only-use-cs1-sel;
480 pinctrl-names = "default";
481 pinctrl-0 = <&pinctrl_lpspi3>;
482 status = "okay";
483
484 spidev0: spi@0 {
485 reg = <0>;
486 compatible = "rohm,dh2228fv";
487 spi-max-frequency = <30000000>;
488 };
489};
490
491&iomuxc {
492 pinctrl-names = "default";
493 pinctrl-0 = <&pinctrl_hog>;
494
495 pinctrl_hog: hoggrp {
496 fsl,pins = <
497 IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0
498 IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD 0x000014a0
499 IMX8DXL_SPI3_CS0_ADMA_ACM_MCLK_OUT1 0x0600004c
500 IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN 0x0600004c
501 >;
502 };
503
504 pinctrl_usbotg1: usbotg1grp {
505 fsl,pins = <
506 IMX8DXL_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021
507 >;
508 };
509
510 pinctrl_usbotg2: usbotg2grp {
511 fsl,pins = <
512 IMX8DXL_USB_SS3_TC1_CONN_USB_OTG2_PWR 0x00000021
513 >;
514 };
515
516 pinctrl_eqos: eqosgrp {
517 fsl,pins = <
518 IMX8DXL_ENET0_MDC_CONN_EQOS_MDC 0x06000020
519 IMX8DXL_ENET0_MDIO_CONN_EQOS_MDIO 0x06000020
520 IMX8DXL_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC 0x06000020
521 IMX8DXL_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0 0x06000020
522 IMX8DXL_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1 0x06000020
523 IMX8DXL_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2 0x06000020
524 IMX8DXL_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3 0x06000020
525 IMX8DXL_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL 0x06000020
526 IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC 0x06000020
527 IMX8DXL_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0 0x06000020
528 IMX8DXL_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1 0x06000020
529 IMX8DXL_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2 0x06000020
530 IMX8DXL_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3 0x06000020
531 IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL 0x06000020
532 >;
533 };
534
535 pinctrl_flexspi0: flexspi0grp {
536 fsl,pins = <
537 IMX8DXL_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021
538 IMX8DXL_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021
539 IMX8DXL_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021
540 IMX8DXL_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021
541 IMX8DXL_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021
542 IMX8DXL_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021
543 IMX8DXL_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021
544 IMX8DXL_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021
545 IMX8DXL_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021
546 IMX8DXL_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021
547 IMX8DXL_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021
548 IMX8DXL_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021
549 IMX8DXL_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021
550 IMX8DXL_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021
551 >;
552 };
553
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]554 pinctrl_flexcan2: flexcan2grp {
555 fsl,pins = <
556 IMX8DXL_UART2_TX_ADMA_FLEXCAN1_TX 0x00000021
557 IMX8DXL_UART2_RX_ADMA_FLEXCAN1_RX 0x00000021
558 >;
559 };
560
561 pinctrl_flexcan3: flexcan3grp {
562 fsl,pins = <
563 IMX8DXL_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x00000021
564 IMX8DXL_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x00000021
565 >;
566 };
567
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]568 pinctrl_fec1: fec1grp {
569 fsl,pins = <
570 IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0
571 IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0
572 IMX8DXL_ENET0_MDC_CONN_ENET0_MDC 0x06000020
573 IMX8DXL_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
574 IMX8DXL_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060
575 IMX8DXL_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060
576 IMX8DXL_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060
577 IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060
578 IMX8DXL_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060
579 IMX8DXL_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060
580 IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060
581 IMX8DXL_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060
582 IMX8DXL_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060
583 IMX8DXL_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060
584 IMX8DXL_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060
585 IMX8DXL_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060
586 >;
587 };
588
589 pinctrl_lpspi3: lpspi3grp {
590 fsl,pins = <
591 IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK 0x6000040
592 IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO 0x6000040
593 IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI 0x6000040
594 IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1 0x6000040
595 >;
596 };
597
598 pinctrl_i2c2: i2c2grp {
599 fsl,pins = <
600 IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA 0x06000021
601 IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL 0x06000021
602 >;
603 };
604
605 pinctrl_cm40_lpuart: cm40lpuartgrp {
606 fsl,pins = <
607 IMX8DXL_ADC_IN2_M40_UART0_RX 0x06000020
608 IMX8DXL_ADC_IN3_M40_UART0_TX 0x06000020
609 >;
610 };
611
612 pinctrl_i2c3: i2c3grp {
613 fsl,pins = <
614 IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA 0x06000021
615 IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL 0x06000021
616 >;
617 };
618
619 pinctrl_lpuart0: lpuart0grp {
620 fsl,pins = <
621 IMX8DXL_UART0_RX_ADMA_UART0_RX 0x06000020
622 IMX8DXL_UART0_TX_ADMA_UART0_TX 0x06000020
623 >;
624 };
625
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]626 pinctrl_lpuart1: lpuart1grp {
627 fsl,pins = <
628 IMX8DXL_UART1_TX_ADMA_UART1_TX 0x06000020
629 IMX8DXL_UART1_RX_ADMA_UART1_RX 0x06000020
630 IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B 0x06000020
631 IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B 0x06000020
632 >;
633 };
634
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]635 pinctrl_usdhc1: usdhc1grp {
636 fsl,pins = <
637 IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
638 IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
639 IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
640 IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
641 IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
642 IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
643 IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
644 IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
645 IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
646 IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
647 IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
648 >;
649 };
650
651 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
652 fsl,pins = <
653 IMX8DXL_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x00000040 /* RESET_B */
654 IMX8DXL_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x00000021 /* WP */
655 IMX8DXL_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x00000021 /* CD */
656 >;
657 };
658
659 pinctrl_usdhc2: usdhc2grp {
660 fsl,pins = <
661 IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041
662 IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021
663 IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021
664 IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021
665 IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021
666 IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021
667 IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021
668 >;
669 };
670};