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git01.mediatek.com / filogic / uboot / c31f901b7c095a32d4809608d6598ecd8fee50e4 / . / dts / upstream / src / arm / st / stm32mp13-pinctrl.dtsi
blob: 32c5d8a1e06acdf0074ab4c6ce0c2e62c80526f0 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com>
5 */
6#include <dt-bindings/pinctrl/stm32-pinfunc.h>
7
8&pinctrl {
9 adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 {
10 pins {
11 pinmux = <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */
12 <STM32_PINMUX('A', 3, ANALOG)>; /* ADC1 in12 */
13 };
14 };
15
16 i2c1_pins_a: i2c1-0 {
17 pins {
18 pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
19 <STM32_PINMUX('E', 8, AF5)>; /* I2C1_SDA */
20 bias-disable;
21 drive-open-drain;
22 slew-rate = <0>;
23 };
24 };
25
26 i2c1_sleep_pins_a: i2c1-sleep-0 {
27 pins {
28 pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
29 <STM32_PINMUX('E', 8, ANALOG)>; /* I2C1_SDA */
30 };
31 };
32
33 i2c5_pins_a: i2c5-0 {
34 pins {
35 pinmux = <STM32_PINMUX('D', 1, AF4)>, /* I2C5_SCL */
36 <STM32_PINMUX('H', 6, AF4)>; /* I2C5_SDA */
37 bias-disable;
38 drive-open-drain;
39 slew-rate = <0>;
40 };
41 };
42
43 i2c5_sleep_pins_a: i2c5-sleep-0 {
44 pins {
45 pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* I2C5_SCL */
46 <STM32_PINMUX('H', 6, ANALOG)>; /* I2C5_SDA */
47 };
48 };
49
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]50 ltdc_pins_a: ltdc-0 {
51 pins {
52 pinmux = <STM32_PINMUX('D', 9, AF13)>, /* LCD_CLK */
53 <STM32_PINMUX('C', 6, AF14)>, /* LCD_HSYNC */
54 <STM32_PINMUX('G', 4, AF11)>, /* LCD_VSYNC */
55 <STM32_PINMUX('H', 9, AF11)>, /* LCD_DE */
56 <STM32_PINMUX('G', 7, AF14)>, /* LCD_R2 */
57 <STM32_PINMUX('B', 12, AF13)>, /* LCD_R3 */
58 <STM32_PINMUX('D', 14, AF14)>, /* LCD_R4 */
59 <STM32_PINMUX('E', 7, AF14)>, /* LCD_R5 */
60 <STM32_PINMUX('E', 13, AF14)>, /* LCD_R6 */
61 <STM32_PINMUX('E', 9, AF14)>, /* LCD_R7 */
62 <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */
63 <STM32_PINMUX('F', 3, AF14)>, /* LCD_G3 */
64 <STM32_PINMUX('D', 5, AF14)>, /* LCD_G4 */
65 <STM32_PINMUX('G', 0, AF14)>, /* LCD_G5 */
66 <STM32_PINMUX('C', 7, AF14)>, /* LCD_G6 */
67 <STM32_PINMUX('A', 15, AF11)>, /* LCD_G7 */
68 <STM32_PINMUX('D', 10, AF14)>, /* LCD_B2 */
69 <STM32_PINMUX('F', 2, AF14)>, /* LCD_B3 */
70 <STM32_PINMUX('H', 14, AF11)>, /* LCD_B4 */
71 <STM32_PINMUX('E', 0, AF14)>, /* LCD_B5 */
72 <STM32_PINMUX('B', 6, AF7)>, /* LCD_B6 */
73 <STM32_PINMUX('F', 1, AF13)>; /* LCD_B7 */
74 bias-disable;
75 drive-push-pull;
76 slew-rate = <0>;
77 };
78 };
79
80 ltdc_sleep_pins_a: ltdc-sleep-0 {
81 pins {
82 pinmux = <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_CLK */
83 <STM32_PINMUX('C', 6, ANALOG)>, /* LCD_HSYNC */
84 <STM32_PINMUX('G', 4, ANALOG)>, /* LCD_VSYNC */
85 <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_DE */
86 <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_R2 */
87 <STM32_PINMUX('B', 12, ANALOG)>, /* LCD_R3 */
88 <STM32_PINMUX('D', 14, ANALOG)>, /* LCD_R4 */
89 <STM32_PINMUX('E', 7, ANALOG)>, /* LCD_R5 */
90 <STM32_PINMUX('E', 13, ANALOG)>, /* LCD_R6 */
91 <STM32_PINMUX('E', 9, ANALOG)>, /* LCD_R7 */
92 <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */
93 <STM32_PINMUX('F', 3, ANALOG)>, /* LCD_G3 */
94 <STM32_PINMUX('D', 5, ANALOG)>, /* LCD_G4 */
95 <STM32_PINMUX('G', 0, ANALOG)>, /* LCD_G5 */
96 <STM32_PINMUX('C', 7, ANALOG)>, /* LCD_G6 */
97 <STM32_PINMUX('A', 15, ANALOG)>, /* LCD_G7 */
98 <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B2 */
99 <STM32_PINMUX('F', 2, ANALOG)>, /* LCD_B3 */
100 <STM32_PINMUX('H', 14, ANALOG)>, /* LCD_B4 */
101 <STM32_PINMUX('E', 0, ANALOG)>, /* LCD_B5 */
102 <STM32_PINMUX('B', 6, ANALOG)>, /* LCD_B6 */
103 <STM32_PINMUX('F', 1, ANALOG)>; /* LCD_B7 */
104 };
105 };
106
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]107 mcp23017_pins_a: mcp23017-0 {
108 pins {
109 pinmux = <STM32_PINMUX('G', 12, GPIO)>;
110 bias-pull-up;
111 };
112 };
113
114 pwm3_pins_a: pwm3-0 {
115 pins {
116 pinmux = <STM32_PINMUX('B', 1, AF2)>; /* TIM3_CH4 */
117 bias-pull-down;
118 drive-push-pull;
119 slew-rate = <0>;
120 };
121 };
122
123 pwm3_sleep_pins_a: pwm3-sleep-0 {
124 pins {
125 pinmux = <STM32_PINMUX('B', 1, ANALOG)>; /* TIM3_CH4 */
126 };
127 };
128
129 pwm4_pins_a: pwm4-0 {
130 pins {
131 pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */
132 bias-pull-down;
133 drive-push-pull;
134 slew-rate = <0>;
135 };
136 };
137
138 pwm4_sleep_pins_a: pwm4-sleep-0 {
139 pins {
140 pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */
141 };
142 };
143
144 pwm8_pins_a: pwm8-0 {
145 pins {
146 pinmux = <STM32_PINMUX('E', 5, AF3)>; /* TIM8_CH3 */
147 bias-pull-down;
148 drive-push-pull;
149 slew-rate = <0>;
150 };
151 };
152
153 pwm8_sleep_pins_a: pwm8-sleep-0 {
154 pins {
155 pinmux = <STM32_PINMUX('E', 5, ANALOG)>; /* TIM8_CH3 */
156 };
157 };
158
159 pwm14_pins_a: pwm14-0 {
160 pins {
161 pinmux = <STM32_PINMUX('F', 9, AF9)>; /* TIM14_CH1 */
162 bias-pull-down;
163 drive-push-pull;
164 slew-rate = <0>;
165 };
166 };
167
168 pwm14_sleep_pins_a: pwm14-sleep-0 {
169 pins {
170 pinmux = <STM32_PINMUX('F', 9, ANALOG)>; /* TIM14_CH1 */
171 };
172 };
173
174 sdmmc1_b4_pins_a: sdmmc1-b4-0 {
175 pins {
176 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
177 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
178 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
179 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
180 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
181 slew-rate = <1>;
182 drive-push-pull;
183 bias-disable;
184 };
185 };
186
187 sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
188 pins1 {
189 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
190 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
191 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
192 <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
193 slew-rate = <1>;
194 drive-push-pull;
195 bias-disable;
196 };
197 pins2 {
198 pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
199 slew-rate = <1>;
200 drive-open-drain;
201 bias-disable;
202 };
203 };
204
205 sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
206 pins {
207 pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
208 <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
209 <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
210 <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
211 <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
212 <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
213 };
214 };
215
216 sdmmc1_clk_pins_a: sdmmc1-clk-0 {
217 pins {
218 pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
219 slew-rate = <1>;
220 drive-push-pull;
221 bias-disable;
222 };
223 };
224
225 sdmmc2_b4_pins_a: sdmmc2-b4-0 {
226 pins {
227 pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */
228 <STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */
229 <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */
230 <STM32_PINMUX('B', 4, AF10)>, /* SDMMC2_D3 */
231 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
232 slew-rate = <1>;
233 drive-push-pull;
234 bias-pull-up;
235 };
236 };
237
238 sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
239 pins1 {
240 pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */
241 <STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */
242 <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */
243 <STM32_PINMUX('B', 4, AF10)>; /* SDMMC2_D3 */
244 slew-rate = <1>;
245 drive-push-pull;
246 bias-pull-up;
247 };
248 pins2 {
249 pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
250 slew-rate = <1>;
251 drive-open-drain;
252 bias-pull-up;
253 };
254 };
255
256 sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
257 pins {
258 pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */
259 <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */
260 <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
261 <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */
262 <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */
263 <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
264 };
265 };
266
267 sdmmc2_clk_pins_a: sdmmc2-clk-0 {
268 pins {
269 pinmux = <STM32_PINMUX('E', 3, AF10)>; /* SDMMC2_CK */
270 slew-rate = <1>;
271 drive-push-pull;
272 bias-pull-up;
273 };
274 };
275
276 spi5_pins_a: spi5-0 {
277 pins1 {
278 pinmux = <STM32_PINMUX('H', 7, AF6)>, /* SPI5_SCK */
279 <STM32_PINMUX('H', 3, AF5)>; /* SPI5_MOSI */
280 bias-disable;
281 drive-push-pull;
282 slew-rate = <1>;
283 };
284
285 pins2 {
286 pinmux = <STM32_PINMUX('A', 8, AF5)>; /* SPI5_MISO */
287 bias-disable;
288 };
289 };
290
291 spi5_sleep_pins_a: spi5-sleep-0 {
292 pins {
293 pinmux = <STM32_PINMUX('H', 7, ANALOG)>, /* SPI5_SCK */
294 <STM32_PINMUX('A', 8, ANALOG)>, /* SPI5_MISO */
295 <STM32_PINMUX('H', 3, ANALOG)>; /* SPI5_MOSI */
296 };
297 };
298
299 stm32g0_intn_pins_a: stm32g0-intn-0 {
300 pins {
301 pinmux = <STM32_PINMUX('I', 2, GPIO)>;
302 bias-pull-up;
303 };
304 };
305
306 uart4_pins_a: uart4-0 {
307 pins1 {
308 pinmux = <STM32_PINMUX('D', 6, AF8)>; /* UART4_TX */
309 bias-disable;
310 drive-push-pull;
311 slew-rate = <0>;
312 };
313 pins2 {
314 pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
315 bias-disable;
316 };
317 };
318
319 uart4_idle_pins_a: uart4-idle-0 {
320 pins1 {
321 pinmux = <STM32_PINMUX('D', 6, ANALOG)>; /* UART4_TX */
322 };
323 pins2 {
324 pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
325 bias-disable;
326 };
327 };
328
329 uart4_sleep_pins_a: uart4-sleep-0 {
330 pins {
331 pinmux = <STM32_PINMUX('D', 6, ANALOG)>, /* UART4_TX */
332 <STM32_PINMUX('D', 8, ANALOG)>; /* UART4_RX */
333 };
334 };
335
336 uart8_pins_a: uart8-0 {
337 pins1 {
338 pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
339 bias-disable;
340 drive-push-pull;
341 slew-rate = <0>;
342 };
343 pins2 {
344 pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */
345 bias-pull-up;
346 };
347 };
348
349 uart8_idle_pins_a: uart8-idle-0 {
350 pins1 {
351 pinmux = <STM32_PINMUX('E', 1, ANALOG)>; /* UART8_TX */
352 };
353 pins2 {
354 pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */
355 bias-pull-up;
356 };
357 };
358
359 uart8_sleep_pins_a: uart8-sleep-0 {
360 pins {
361 pinmux = <STM32_PINMUX('E', 1, ANALOG)>, /* UART8_TX */
362 <STM32_PINMUX('F', 9, ANALOG)>; /* UART8_RX */
363 };
364 };
365
366 usart1_pins_a: usart1-0 {
367 pins1 {
368 pinmux = <STM32_PINMUX('C', 0, AF7)>, /* USART1_TX */
369 <STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */
370 bias-disable;
371 drive-push-pull;
372 slew-rate = <0>;
373 };
374 pins2 {
375 pinmux = <STM32_PINMUX('B', 0, AF4)>, /* USART1_RX */
376 <STM32_PINMUX('A', 7, AF7)>; /* USART1_CTS_NSS */
377 bias-pull-up;
378 };
379 };
380
381 usart1_idle_pins_a: usart1-idle-0 {
382 pins1 {
383 pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
384 <STM32_PINMUX('A', 7, ANALOG)>; /* USART1_CTS_NSS */
385 };
386 pins2 {
387 pinmux = <STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */
388 bias-disable;
389 drive-push-pull;
390 slew-rate = <0>;
391 };
392 pins3 {
393 pinmux = <STM32_PINMUX('B', 0, AF4)>; /* USART1_RX */
394 bias-pull-up;
395 };
396 };
397
398 usart1_sleep_pins_a: usart1-sleep-0 {
399 pins {
400 pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
401 <STM32_PINMUX('C', 2, ANALOG)>, /* USART1_RTS */
402 <STM32_PINMUX('A', 7, ANALOG)>, /* USART1_CTS_NSS */
403 <STM32_PINMUX('B', 0, ANALOG)>; /* USART1_RX */
404 };
405 };
406
407 usart2_pins_a: usart2-0 {
408 pins1 {
409 pinmux = <STM32_PINMUX('H', 12, AF1)>, /* USART2_TX */
410 <STM32_PINMUX('D', 4, AF3)>; /* USART2_RTS */
411 bias-disable;
412 drive-push-pull;
413 slew-rate = <0>;
414 };
415 pins2 {
416 pinmux = <STM32_PINMUX('D', 15, AF1)>, /* USART2_RX */
417 <STM32_PINMUX('E', 11, AF2)>; /* USART2_CTS_NSS */
418 bias-disable;
419 };
420 };
421
422 usart2_idle_pins_a: usart2-idle-0 {
423 pins1 {
424 pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */
425 <STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */
426 };
427 pins2 {
428 pinmux = <STM32_PINMUX('D', 4, AF3)>; /* USART2_RTS */
429 bias-disable;
430 drive-push-pull;
431 slew-rate = <0>;
432 };
433 pins3 {
434 pinmux = <STM32_PINMUX('D', 15, AF1)>; /* USART2_RX */
435 bias-disable;
436 };
437 };
438
439 usart2_sleep_pins_a: usart2-sleep-0 {
440 pins {
441 pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */
442 <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
443 <STM32_PINMUX('D', 15, ANALOG)>, /* USART2_RX */
444 <STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */
445 };
446 };
447};