Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / c31f901b7c095a32d4809608d6598ecd8fee50e4 / . / dts / upstream / src / arm / qcom / qcom-ipq4019-ap.dk01.1.dtsi
blob: f7ac8f9d0b6fc00e6363f2f42e8356591fed9cc5 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
2 *
3 * Permission to use, copy, modify, and/or distribute this software for any
4 * purpose with or without fee is hereby granted, provided that the above
5 * copyright notice and this permission notice appear in all copies.
6 *
7 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
8 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
9 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
10 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
11 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
12 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
13 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
14 *
15 */
16
17#include <dt-bindings/gpio/gpio.h>
18#include "qcom-ipq4019.dtsi"
19
20/ {
21 model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
22
23 aliases {
24 serial0 = &blsp1_uart1;
25 };
26
27 chosen {
28 stdout-path = "serial0:115200n8";
29 };
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]30};
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]31
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]32&prng {
33 status = "okay";
34};
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]35
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]36&tlmm {
37 serial_pins: serial_pinmux {
38 mux {
39 pins = "gpio60", "gpio61";
40 function = "blsp_uart0";
41 bias-disable;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]42 };
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]43 };
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]44
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]45 spi_0_pins: spi_0_pinmux {
46 pinmux {
47 function = "blsp_spi0";
48 pins = "gpio55", "gpio56", "gpio57";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]49 };
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]50 pinmux_cs {
51 function = "gpio";
52 pins = "gpio54";
53 };
54 pinconf {
55 pins = "gpio55", "gpio56", "gpio57";
56 drive-strength = <12>;
57 bias-disable;
58 };
59 pinconf_cs {
60 pins = "gpio54";
61 drive-strength = <2>;
62 bias-disable;
63 output-high;
64 };
65 };
66};
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]67
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]68&blsp_dma {
69 status = "okay";
70};
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]71
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]72&blsp1_spi1 {
73 pinctrl-0 = <&spi_0_pins>;
74 pinctrl-names = "default";
75 status = "okay";
76 cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]77
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]78 flash@0 {
79 reg = <0>;
80 compatible = "jedec,spi-nor";
81 spi-max-frequency = <24000000>;
82 };
83};
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]84
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]85&blsp1_uart1 {
86 pinctrl-0 = <&serial_pins>;
87 pinctrl-names = "default";
88 status = "okay";
89};
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]90
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]91&cryptobam {
92 status = "okay";
93};
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]94
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]95&crypto {
96 status = "okay";
97};
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]98
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]99&watchdog {
100 status = "okay";
101};
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]102
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]103&wifi0 {
104 status = "okay";
105};
106
107&wifi1 {
108 status = "okay";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]109};