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git01.mediatek.com / filogic / uboot / c31f901b7c095a32d4809608d6598ecd8fee50e4 / . / dts / upstream / src / arm / nxp / imx / imx6sl-tolino-shine3.dts
blob: db5d8509935f16d6e0a2b9c7132cd18c1f86718e [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0)
2/*
3 * Device tree for the Tolino Shine 3 ebook reader
4 *
5 * Name on mainboard is: 37NB-E60K00+4A4
6 * Serials start with: E60K02 (a number also seen in
7 * vendor kernel sources)
8 *
9 * This mainboard seems to be equipped with different SoCs.
10 * In the Toline Shine 3 ebook reader it is a i.MX6SL
11 *
12 * Copyright 2019 Andreas Kemnade
13 * based on works
14 * Copyright 2016 Freescale Semiconductor, Inc.
15 */
16
17/dts-v1/;
18
19#include <dt-bindings/input/input.h>
20#include <dt-bindings/gpio/gpio.h>
21#include "imx6sl.dtsi"
22#include "e60k02.dtsi"
23
24/ {
25 model = "Tolino Shine 3";
26 compatible = "kobo,tolino-shine3", "fsl,imx6sl";
27};
28
29&gpio_keys {
30 pinctrl-names = "default";
31 pinctrl-0 = <&pinctrl_gpio_keys>;
32};
33
34&i2c1 {
35 pinctrl-names = "default","sleep";
36 pinctrl-0 = <&pinctrl_i2c1>;
37 pinctrl-1 = <&pinctrl_i2c1_sleep>;
38};
39
40&i2c2 {
41 pinctrl-names = "default","sleep";
42 pinctrl-0 = <&pinctrl_i2c2>;
43 pinctrl-1 = <&pinctrl_i2c2_sleep>;
44};
45
46&i2c3 {
47 pinctrl-names = "default";
48 pinctrl-0 = <&pinctrl_i2c3>;
49};
50
51&iomuxc {
52 pinctrl-names = "default";
53 pinctrl-0 = <&pinctrl_hog>;
54
55 pinctrl_cyttsp5_gpio: cyttsp5-gpiogrp {
56 fsl,pins = <
57 MX6SL_PAD_SD1_DAT3__GPIO5_IO06 0x17059 /* TP_INT */
58 MX6SL_PAD_SD1_DAT2__GPIO5_IO13 0x10059 /* TP_RST */
59 >;
60 };
61
62 pinctrl_gpio_keys: gpio-keysgrp {
63 fsl,pins = <
64 MX6SL_PAD_SD1_DAT1__GPIO5_IO08 0x17059 /* PWR_SW */
65 MX6SL_PAD_SD1_DAT4__GPIO5_IO12 0x17059 /* HALL_EN */
66 >;
67 };
68
69 pinctrl_hog: hoggrp {
70 fsl,pins = <
71 MX6SL_PAD_LCD_DAT0__GPIO2_IO20 0x79
72 MX6SL_PAD_LCD_DAT1__GPIO2_IO21 0x79
73 MX6SL_PAD_LCD_DAT2__GPIO2_IO22 0x79
74 MX6SL_PAD_LCD_DAT3__GPIO2_IO23 0x79
75 MX6SL_PAD_LCD_DAT4__GPIO2_IO24 0x79
76 MX6SL_PAD_LCD_DAT5__GPIO2_IO25 0x79
77 MX6SL_PAD_LCD_DAT6__GPIO2_IO26 0x79
78 MX6SL_PAD_LCD_DAT7__GPIO2_IO27 0x79
79 MX6SL_PAD_LCD_DAT8__GPIO2_IO28 0x79
80 MX6SL_PAD_LCD_DAT9__GPIO2_IO29 0x79
81 MX6SL_PAD_LCD_DAT10__GPIO2_IO30 0x79
82 MX6SL_PAD_LCD_DAT11__GPIO2_IO31 0x79
83 MX6SL_PAD_LCD_DAT12__GPIO3_IO00 0x79
84 MX6SL_PAD_LCD_DAT13__GPIO3_IO01 0x79
85 MX6SL_PAD_LCD_DAT14__GPIO3_IO02 0x79
86 MX6SL_PAD_LCD_DAT15__GPIO3_IO03 0x79
87 MX6SL_PAD_LCD_DAT16__GPIO3_IO04 0x79
88 MX6SL_PAD_LCD_DAT17__GPIO3_IO05 0x79
89 MX6SL_PAD_LCD_DAT18__GPIO3_IO06 0x79
90 MX6SL_PAD_LCD_DAT19__GPIO3_IO07 0x79
91 MX6SL_PAD_LCD_DAT20__GPIO3_IO08 0x79
92 MX6SL_PAD_LCD_DAT21__GPIO3_IO09 0x79
93 MX6SL_PAD_LCD_DAT22__GPIO3_IO10 0x79
94 MX6SL_PAD_LCD_DAT23__GPIO3_IO11 0x79
95 MX6SL_PAD_LCD_CLK__GPIO2_IO15 0x79
96 MX6SL_PAD_LCD_ENABLE__GPIO2_IO16 0x79
97 MX6SL_PAD_LCD_HSYNC__GPIO2_IO17 0x79
98 MX6SL_PAD_LCD_VSYNC__GPIO2_IO18 0x79
99 MX6SL_PAD_LCD_RESET__GPIO2_IO19 0x79
100 MX6SL_PAD_KEY_COL3__GPIO3_IO30 0x79
101 MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x79
102 MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x79
103 MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x79
104 >;
105 };
106
107 pinctrl_i2c1: i2c1grp {
108 fsl,pins = <
109 MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001f8b1
110 MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001f8b1
111 >;
112 };
113
114 pinctrl_i2c1_sleep: i2c1grp-sleep {
115 fsl,pins = <
116 MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1
117 MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1
118 >;
119 };
120
121 pinctrl_i2c2: i2c2grp {
122 fsl,pins = <
123 MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001f8b1
124 MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001f8b1
125 >;
126 };
127
128 pinctrl_i2c2_sleep: i2c2grp-sleep {
129 fsl,pins = <
130 MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1
131 MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1
132 >;
133 };
134
135 pinctrl_i2c3: i2c3grp {
136 fsl,pins = <
137 MX6SL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1
138 MX6SL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1
139 >;
140 };
141
142 pinctrl_led: ledgrp {
143 fsl,pins = <
144 MX6SL_PAD_SD1_DAT6__GPIO5_IO07 0x17059
145 >;
146 };
147
148 pinctrl_lm3630a_bl_gpio: lm3630a-bl-gpiogrp {
149 fsl,pins = <
150 MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x10059 /* HWEN */
151 >;
152 };
153
154 pinctrl_ricoh_gpio: ricoh_gpiogrp {
155 fsl,pins = <
156 MX6SL_PAD_SD1_CLK__GPIO5_IO15 0x1b8b1 /* ricoh619 chg */
157 MX6SL_PAD_SD1_DAT0__GPIO5_IO11 0x1b8b1 /* ricoh619 irq */
158 MX6SL_PAD_KEY_COL2__GPIO3_IO28 0x1b8b1 /* ricoh619 bat_low_int */
159 >;
160 };
161
162 pinctrl_uart1: uart1grp {
163 fsl,pins = <
164 MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
165 MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
166 >;
167 };
168
169 pinctrl_uart4: uart4grp {
170 fsl,pins = <
171 MX6SL_PAD_KEY_ROW6__UART4_TX_DATA 0x1b0b1
172 MX6SL_PAD_KEY_COL6__UART4_RX_DATA 0x1b0b1
173 >;
174 };
175
176 pinctrl_usbotg1: usbotg1grp {
177 fsl,pins = <
178 MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059
179 >;
180 };
181
182 pinctrl_usdhc2: usdhc2grp {
183 fsl,pins = <
184 MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059
185 MX6SL_PAD_SD2_CLK__SD2_CLK 0x13059
186 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059
187 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059
188 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059
189 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
190 >;
191 };
192
193 pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
194 fsl,pins = <
195 MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9
196 MX6SL_PAD_SD2_CLK__SD2_CLK 0x130b9
197 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
198 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
199 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
200 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
201 >;
202 };
203
204 pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
205 fsl,pins = <
206 MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9
207 MX6SL_PAD_SD2_CLK__SD2_CLK 0x130f9
208 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
209 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
210 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
211 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
212 >;
213 };
214
215 pinctrl_usdhc2_sleep: usdhc2grp-sleep {
216 fsl,pins = <
217 MX6SL_PAD_SD2_CMD__GPIO5_IO04 0x100f9
218 MX6SL_PAD_SD2_CLK__GPIO5_IO05 0x100f9
219 MX6SL_PAD_SD2_DAT0__GPIO5_IO01 0x100f9
220 MX6SL_PAD_SD2_DAT1__GPIO4_IO30 0x100f9
221 MX6SL_PAD_SD2_DAT2__GPIO5_IO03 0x100f9
222 MX6SL_PAD_SD2_DAT3__GPIO4_IO28 0x100f9
223 >;
224 };
225
226 pinctrl_usdhc3: usdhc3grp {
227 fsl,pins = <
228 MX6SL_PAD_SD3_CMD__SD3_CMD 0x11059
229 MX6SL_PAD_SD3_CLK__SD3_CLK 0x11059
230 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x11059
231 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x11059
232 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x11059
233 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x11059
234 >;
235 };
236
237 pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
238 fsl,pins = <
239 MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9
240 MX6SL_PAD_SD3_CLK__SD3_CLK 0x170b9
241 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
242 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
243 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
244 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
245 >;
246 };
247
248 pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
249 fsl,pins = <
250 MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9
251 MX6SL_PAD_SD3_CLK__SD3_CLK 0x170f9
252 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
253 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
254 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
255 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
256 >;
257 };
258
259 pinctrl_usdhc3_sleep: usdhc3grp-sleep {
260 fsl,pins = <
261 MX6SL_PAD_SD3_CMD__GPIO5_IO21 0x100c1
262 MX6SL_PAD_SD3_CLK__GPIO5_IO18 0x100c1
263 MX6SL_PAD_SD3_DAT0__GPIO5_IO19 0x100c1
264 MX6SL_PAD_SD3_DAT1__GPIO5_IO20 0x100c1
265 MX6SL_PAD_SD3_DAT2__GPIO5_IO16 0x100c1
266 MX6SL_PAD_SD3_DAT3__GPIO5_IO17 0x100c1
267 >;
268 };
269
270 pinctrl_wifi_power: wifi-powergrp {
271 fsl,pins = <
272 MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x10059 /* WIFI_3V3_ON */
273 >;
274 };
275
276 pinctrl_wifi_reset: wifi-resetgrp {
277 fsl,pins = <
278 MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x10059 /* WIFI_RST */
279 >;
280 };
281};
282
283&leds {
284 pinctrl-names = "default";
285 pinctrl-0 = <&pinctrl_led>;
286};
287
288&lm3630a {
289 pinctrl-names = "default";
290 pinctrl-0 = <&pinctrl_lm3630a_bl_gpio>;
291};
292
293&reg_wifi {
294 pinctrl-names = "default";
295 pinctrl-0 = <&pinctrl_wifi_power>;
296};
297
298&reg_vdd1p1 {
299 vin-supply = <&dcdc2_reg>;
300};
301
302&reg_vdd2p5 {
303 vin-supply = <&dcdc2_reg>;
304};
305
306&ricoh619 {
307 pinctrl-names = "default";
308 pinctrl-0 = <&pinctrl_ricoh_gpio>;
309};
310
311&uart1 {
312 pinctrl-names = "default";
313 pinctrl-0 = <&pinctrl_uart1>;
314};
315
316&uart4 {
317 pinctrl-names = "default";
318 pinctrl-0 = <&pinctrl_uart4>;
319};
320
321&usdhc2 {
322 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
323 pinctrl-0 = <&pinctrl_usdhc2>;
324 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
325 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
326 pinctrl-3 = <&pinctrl_usdhc2_sleep>;
327};
328
329&usdhc3 {
330 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
331 pinctrl-0 = <&pinctrl_usdhc3>;
332 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
333 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
334 pinctrl-3 = <&pinctrl_usdhc3_sleep>;
335};
336
337&wifi_pwrseq {
338 pinctrl-names = "default";
339 pinctrl-0 = <&pinctrl_wifi_reset>;
340};