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git01.mediatek.com / filogic / uboot / c31f901b7c095a32d4809608d6598ecd8fee50e4 / . / dts / upstream / src / arm / nxp / imx / imx6qdl-ts7970.dtsi
blob: e2db875b61c4e4c12dd9bf380eb013ea7ef9ba2c [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1/*
2 * Copyright 2015 Technologic Systems
3 * Copyright 2017 Savoir-Faire Linux
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * version 2 as published by the Free Software Foundation.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#include <dt-bindings/gpio/gpio.h>
44#include <dt-bindings/interrupt-controller/irq.h>
45
46/ {
47 leds {
48 pinctrl-names = "default";
49 pinctrl-0 = <&pinctrl_leds1>;
50 compatible = "gpio-leds";
51
52 green-led {
53 label = "green-led";
54 gpios = <&gpio3 27 GPIO_ACTIVE_LOW>;
55 default-state = "on";
56 };
57
58 red-led {
59 label = "red-led";
60 gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
61 default-state = "off";
62 };
63
64 yel-led {
65 label = "yellow-led";
66 gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
67 default-state = "off";
68 };
69
70 blue-led {
71 label = "blue-led";
72 gpios = <&gpio4 25 GPIO_ACTIVE_LOW>;
73 default-state = "off";
74 };
75
76 en-usb-5v-led {
77 label = "en-usb-5v";
78 gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
79 default-state = "on";
80 };
81
82 sel-dc-usb-led {
83 label = "sel_dc_usb";
84 gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
85 default-state = "off";
86 };
87
88 };
89
90 reg_3p3v: regulator-3p3v {
91 compatible = "regulator-fixed";
92 regulator-name = "3p3v";
93 regulator-min-microvolt = <3300000>;
94 regulator-max-microvolt = <3300000>;
95 regulator-always-on;
96 };
97
98 reg_can1_3v3: reg_can1_3v3 {
99 compatible = "regulator-fixed";
100 regulator-name = "reg_can1_3v3";
101 regulator-min-microvolt = <3300000>;
102 regulator-max-microvolt = <3300000>;
103 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
104 enable-active-high;
105 };
106
107 reg_can2_3v3: en-reg_can2_3v3 {
108 compatible = "regulator-fixed";
109 regulator-name = "reg_can2_3v3";
110 regulator-min-microvolt = <3300000>;
111 regulator-max-microvolt = <3300000>;
112 gpio = <&gpio6 31 GPIO_ACTIVE_HIGH>;
113 enable-active-high;
114 };
115
116 reg_usb_otg_vbus: regulator-usb-otg-vbus {
117 compatible = "regulator-fixed";
118 regulator-name = "usb_otg_vbus";
119 regulator-min-microvolt = <5000000>;
120 regulator-max-microvolt = <5000000>;
121 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
122 enable-active-high;
123 };
124
125 reg_wlan_vmmc: regulator_wlan_vmmc {
126 compatible = "regulator-fixed";
127 regulator-name = "wlan_vmmc";
128 regulator-min-microvolt = <1800000>;
129 regulator-max-microvolt = <1800000>;
130 gpio = <&gpio8 14 GPIO_ACTIVE_HIGH>;
131 startup-delay-us = <70000>;
132 enable-active-high;
133 };
134
135 sound-sgtl5000 {
136 audio-codec = <&sgtl5000>;
137 audio-routing =
138 "MIC_IN", "Mic Jack",
139 "Mic Jack", "Mic Bias",
140 "Headphone Jack", "HP_OUT";
141 compatible = "fsl,imx-audio-sgtl5000";
142 model = "On-board Codec";
143 mux-ext-port = <3>;
144 mux-int-port = <1>;
145 ssi-controller = <&ssi1>;
146 };
147};
148
149&audmux {
150 status = "okay";
151};
152
153&can1 {
154 pinctrl-names = "default";
155 pinctrl-0 = <&pinctrl_flexcan1>;
156 xceiver-supply = <&reg_can1_3v3>;
157 status = "okay";
158};
159
160&can2 {
161 pinctrl-names = "default";
162 pinctrl-0 = <&pinctrl_flexcan2>;
163 xceiver-supply = <&reg_can2_3v3>;
164 status = "okay";
165};
166
167&ecspi1 {
168 cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
169 pinctrl-names = "default";
170 pinctrl-0 = <&pinctrl_ecspi1>;
171 status = "okay";
172
173 n25q064: flash@0 {
174 compatible = "micron,n25q064", "jedec,spi-nor";
175 reg = <0>;
176 spi-max-frequency = <20000000>;
177 };
178};
179
180&ecspi2 {
181 cs-gpios = <
182 &gpio5 31 GPIO_ACTIVE_LOW
183 &gpio7 12 GPIO_ACTIVE_LOW
184 &gpio5 18 GPIO_ACTIVE_LOW
185 >;
186 pinctrl-names = "default";
187 pinctrl-0 = <&pinctrl_ecspi2>;
188 status = "okay";
189};
190
191&fec {
192 pinctrl-names = "default";
193 pinctrl-0 = <&pinctrl_enet>;
194 phy-mode = "rgmii";
195 /delete-property/ interrupts;
196 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
197 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
198 fsl,err006687-workaround-present;
199 status = "okay";
200};
201
202&hdmi {
203 status = "okay";
204};
205
206&i2c1 {
207 clock-frequency = <100000>;
208 pinctrl-names = "default", "gpio";
209 pinctrl-0 = <&pinctrl_i2c1>;
210 pinctrl-1 = <&pinctrl_i2c1_gpio>;
211 scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
212 sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
213 status = "okay";
214
215 m41t00s: rtc@68 {
216 compatible = "m41t00";
217 reg = <0x68>;
218 };
219
220 isl12022: rtc@6f {
221 compatible = "isl,isl12022";
222 reg = <0x6f>;
223 };
224
225 gpio8: gpio@28 {
226 compatible = "technologic,ts7970-gpio";
227 reg = <0x28>;
228 #gpio-cells = <2>;
229 gpio-controller;
230 ngpios = <62>;
231 };
232
233 sgtl5000: codec@a {
234 compatible = "fsl,sgtl5000";
235 pinctrl-names = "default";
236 pinctrl-0 = <&pinctrl_sgtl5000>;
237 reg = <0x0a>;
238 #sound-dai-cells = <0>;
239 clocks = <&clks IMX6QDL_CLK_CKO>;
240 VDDA-supply = <&reg_3p3v>;
241 VDDIO-supply = <&reg_3p3v>;
242 };
243};
244
245&i2c2 {
246 clock-frequency = <100000>;
247 pinctrl-names = "default", "gpio";
248 pinctrl-0 = <&pinctrl_i2c2>;
249 pinctrl-1 = <&pinctrl_i2c2_gpio>;
250 scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
251 sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
252 status = "okay";
253};
254
255&iomuxc {
256 pinctrl-names = "default";
257 pinctrl-0 = <&pinctrl_hog>;
258
259 pinctrl_ecspi1: ecspi1grp {
260 fsl,pins = <
261 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
262 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
263 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
264 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x100b1 /* Onboard Flash CS */
265 >;
266 };
267
268 pinctrl_ecspi2: ecspi2 {
269 fsl,pins = <
270 MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1
271 MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1
272 MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1
273 MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x100b1 /* FPGA_SPI_CS0 */
274 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x100b1 /* FPGA_SPI_CS1 */
275 MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x100b1 /* HD1_SPI_CS */
276 MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b088 /* FPGA_RESET */
277 MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x10 /* FPGA 24MHZ */
278 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b088 /* FPGA_IRQ_0 */
279 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b088 /* FPGA_IRQ_1 */
280 >;
281 };
282
283 pinctrl_enet: enet {
284 fsl,pins = <
285 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
286 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
287 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
288 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
289 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
290 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
291 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
292 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
293 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
294 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
295 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
296 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
297 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
298 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
299 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
300 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b088
301 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b088 /* ETH_PHY_RESET */
302 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
303 >;
304 };
305
306 pinctrl_flexcan1: flexcan1grp {
307 fsl,pins = <
308 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b088
309 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b088
310 MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b088 /* EN_CAN_1 */
311 >;
312 };
313
314 pinctrl_flexcan2: flexcan2grp {
315 fsl,pins = <
316 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b088
317 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b088
318 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b088 /* EN_CAN_2 */
319 >;
320 };
321
322 pinctrl_hog: hoggrp {
323 fsl,pins = <
324 /* Onboard */
325 MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b088 /* USB_HUB_RESET */
326 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b088 /* SEL_DC_USB */
327 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b088 /* EN_USB_5V */
328 MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b088 /* JTAG_FPGA_TMS */
329 MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b088 /* JTAG_FPGA_TCK */
330 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b088 /* JTAG_FPGA_TDO */
331 MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b088 /* JTAG_FPGA_TDI */
332 MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b088 /* GYRO_INT */
333 MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x1b088 /* MODBUS_FAULT */
334 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b088 /* BUS_DIR/JP_SD_BOOT */
335 MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b088 /* EN_MODBUS_24V */
336 MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b088 /* EN_MODBUS_3V */
337 MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b088 /* I210_RESET */
338 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b088 /* EN_RTC_PWR */
339 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b088 /* REVSTRAP1 */
340
341 /* Offboard */
342 MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b088 /* LCD_D09 */
343 MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b088 /* HD1_IRQ */
344 MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b088 /* LCD_D10 */
345 MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x1b088 /* LCD_D11 */
346 MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b088 /* BUS_BHE */
347 MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b088 /* BUS_ALE */
348 MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b088 /* BUS_CS */
349 MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b088 /* DIO_20 */
350 MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b088 /* BUS_WAIT */
351 MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b088 /* MUX_AD_00 */
352 MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b088 /* MUX_AD_01 */
353 MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b088 /* MUX_AD_02 */
354 MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b088 /* MUX_AD_03 */
355 MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b088 /* MUX_AD_04 */
356 MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b088 /* MUX_AD_05 */
357 MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b088 /* MUX_AD_06 */
358 MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b088 /* MUX_AD_07 */
359 MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1b088 /* MUX_AD_08 */
360 MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b088 /* MUX_AD_09 */
361 MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b088 /* MUX_AD_10 */
362 MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x1b088 /* MUX_AD_11 */
363 MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x1b088 /* MUX_AD_12 */
364 MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b088 /* MUX_AD_13 */
365 MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x1b088 /* MUX_AD_14 */
366 MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1b088 /* MUX_AD_15 */
367
368 /* Strapping only */
369 MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b088
370 MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x1b088
371 >;
372 };
373
374 pinctrl_i2c1: i2c1grp {
375 fsl,pins = <
376 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
377 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
378 >;
379 };
380
381 pinctrl_i2c1_gpio: i2c1gpiogrp {
382 fsl,pins = <
383 MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1
384 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1
385 >;
386 };
387
388 pinctrl_i2c2: i2c2grp {
389 fsl,pins = <
390 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
391 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
392 >;
393 };
394
395 pinctrl_i2c2_gpio: i2c2gpiogrp {
396 fsl,pins = <
397 MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1
398 MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1
399 >;
400 };
401
402 pinctrl_leds1: leds1grp {
403 fsl,pins = <
404 MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b088 /* GREEN_LED */
405 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b088 /* RED_LED */
406 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b088 /* YEL_LED */
407 MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b088 /* IMX6_BLUE_LED */
408 >;
409 };
410
411 pinctrl_sgtl5000: sgtl5000grp {
412 fsl,pins = <
413 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
414 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
415 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
416 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
417 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* Audio CLK */
418 >;
419 };
420
421 pinctrl_uart1: uart1grp {
422 fsl,pins = <
423 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b088
424 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b088
425 >;
426 };
427
428 pinctrl_uart2: uart2grp {
429 fsl,pins = <
430 MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b088
431 MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b088
432 MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b088
433 MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b088
434 >;
435 };
436
437 pinctrl_uart3: uart3grp {
438 fsl,pins = <
439 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b088
440 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b088
441 MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x1b088
442 MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b088
443 >;
444 };
445
446 pinctrl_uart4: uart4grp {
447 fsl,pins = <
448 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b088
449 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b088
450 >;
451 };
452
453 pinctrl_uart5: uart5grp {
454 fsl,pins = <
455 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b088
456 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b088
457 >;
458 };
459
460 pinctrl_usbotg: usbotggrp {
461 fsl,pins = <
462 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
463 >;
464 };
465
466 pinctrl_usdhc1: usdhc1grp {
467 fsl,pins = <
468 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
469 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
470 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
471 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
472 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
473 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
474 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x17059 /* WIFI IRQ */
475 >;
476 };
477
478 pinctrl_usdhc2: usdhc2grp {
479 fsl,pins = <
480 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
481 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
482 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
483 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
484 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
485 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
486 MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b088 /* EN_SD_POWER */
487 >;
488 };
489
490 pinctrl_usdhc3: usdhc3grp {
491 fsl,pins = <
492 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
493 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
494 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
495 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
496 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
497 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
498 >;
499 };
500};
501
502&pcie {
503 status = "okay";
504};
505
506&snvs_rtc {
507 status = "disabled";
508};
509
510&ssi1 {
511 status = "okay";
512};
513
514&uart1 {
515 pinctrl-names = "default";
516 pinctrl-0 = <&pinctrl_uart1>;
517 status = "okay";
518};
519
520&uart2 {
521 pinctrl-names = "default";
522 pinctrl-0 = <&pinctrl_uart2>;
523 uart-has-rtscts;
524 status = "okay";
525};
526
527&uart3 {
528 pinctrl-names = "default";
529 pinctrl-0 = <&pinctrl_uart3>;
530 status = "okay";
531};
532
533&uart4 {
534 pinctrl-names = "default";
535 pinctrl-0 = <&pinctrl_uart4>;
536 status = "okay";
537};
538
539&uart5 {
540 pinctrl-names = "default";
541 pinctrl-0 = <&pinctrl_uart5>;
542 status = "okay";
543};
544
545&usbh1 {
546 status = "okay";
547};
548
549&usbotg {
550 vbus-supply = <&reg_usb_otg_vbus>;
551 pinctrl-names = "default";
552 pinctrl-0 = <&pinctrl_usbotg>;
553 disable-over-current;
554 status = "okay";
555};
556
557/* WIFI */
558&usdhc1 {
559 pinctrl-names = "default";
560 pinctrl-0 = <&pinctrl_usdhc1>;
561 vmmc-supply = <&reg_wlan_vmmc>;
562 bus-width = <4>;
563 non-removable;
564 #address-cells = <1>;
565 #size-cells = <0>;
566 status = "okay";
567
568 wlcore: wlcore@2 {
569 compatible = "ti,wl1271";
570 reg = <2>;
571 interrupt-parent = <&gpio1>;
572 interrupts = <26 IRQ_TYPE_LEVEL_HIGH>;
573 ref-clock-frequency = <38400000>;
574 };
575};
576
577/* SD */
578&usdhc2 {
579 pinctrl-names = "default";
580 pinctrl-0 = <&pinctrl_usdhc2>;
581 vmmc-supply = <&reg_3p3v>;
582 bus-width = <4>;
583 fsl,wp-controller;
584 status = "okay";
585};
586
587/* eMMC */
588&usdhc3 {
589 pinctrl-names = "default";
590 pinctrl-0 = <&pinctrl_usdhc3>;
591 vmmc-supply = <&reg_3p3v>;
592 bus-width = <4>;
593 non-removable;
594 status = "okay";
595};