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git01.mediatek.com / filogic / uboot / c31f901b7c095a32d4809608d6598ecd8fee50e4 / . / dts / upstream / src / arm / nvidia / tegra20-acer-a500-picasso.dts
blob: a619ea83ed3b5f271c7e9ebd2642443f9bd6b4fd [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include <dt-bindings/input/atmel-maxtouch.h>
5#include <dt-bindings/input/gpio-keys.h>
6#include <dt-bindings/input/input.h>
7#include <dt-bindings/thermal/thermal.h>
8
9#include "tegra20.dtsi"
10#include "tegra20-cpu-opp.dtsi"
11#include "tegra20-cpu-opp-microvolt.dtsi"
12
13/ {
14 model = "Acer Iconia Tab A500";
15 compatible = "acer,picasso", "nvidia,tegra20";
16
17 aliases {
18 mmc0 = &sdmmc4; /* eMMC */
19 mmc1 = &sdmmc3; /* MicroSD */
20 mmc2 = &sdmmc1; /* WiFi */
21
22 rtc0 = &pmic;
23 rtc1 = "/rtc@7000e000";
24
25 serial0 = &uartd; /* Docking station */
26 serial1 = &uartc; /* Bluetooth */
27 serial2 = &uartb; /* GPS */
28 };
29
30 /*
31 * The decompressor and also some bootloaders rely on a
32 * pre-existing /chosen node to be available to insert the
33 * command line and merge other ATAGS info.
34 */
35 chosen {};
36
37 memory@0 {
38 reg = <0x00000000 0x40000000>;
39 };
40
41 reserved-memory {
42 #address-cells = <1>;
43 #size-cells = <1>;
44 ranges;
45
46 ramoops@2ffe0000 {
47 compatible = "ramoops";
48 reg = <0x2ffe0000 0x10000>; /* 64kB */
49 console-size = <0x8000>; /* 32kB */
50 record-size = <0x400>; /* 1kB */
51 ecc-size = <16>;
52 };
53
54 linux,cma@30000000 {
55 compatible = "shared-dma-pool";
56 alloc-ranges = <0x30000000 0x10000000>;
57 size = <0x10000000>; /* 256MiB */
58 linux,cma-default;
59 reusable;
60 };
61 };
62
63 host1x@50000000 {
64 dc@54200000 {
65 rgb {
66 status = "okay";
67
68 port {
69 lcd_output: endpoint {
70 remote-endpoint = <&lvds_encoder_input>;
71 bus-width = <18>;
72 };
73 };
74 };
75 };
76
77 hdmi@54280000 {
78 status = "okay";
79
80 vdd-supply = <&hdmi_vdd_reg>;
81 pll-supply = <&hdmi_pll_reg>;
82 hdmi-supply = <&vdd_5v0_sys>;
83
84 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
85 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
86 GPIO_ACTIVE_HIGH>;
87 };
88 };
89
90 pinmux@70000014 {
91 pinctrl-names = "default";
92 pinctrl-0 = <&state_default>;
93
94 state_default: pinmux {
95 ata {
96 nvidia,pins = "ata";
97 nvidia,function = "ide";
98 };
99 atb {
100 nvidia,pins = "atb", "gma", "gme";
101 nvidia,function = "sdio4";
102 };
103 atc {
104 nvidia,pins = "atc";
105 nvidia,function = "nand";
106 };
107 atd {
108 nvidia,pins = "atd", "ate", "gmb", "spia",
109 "spib", "spic";
110 nvidia,function = "gmi";
111 };
112 cdev1 {
113 nvidia,pins = "cdev1";
114 nvidia,function = "plla_out";
115 };
116 cdev2 {
117 nvidia,pins = "cdev2";
118 nvidia,function = "pllp_out4";
119 };
120 crtp {
121 nvidia,pins = "crtp", "lm1";
122 nvidia,function = "crt";
123 };
124 csus {
125 nvidia,pins = "csus";
126 nvidia,function = "vi_sensor_clk";
127 };
128 dap1 {
129 nvidia,pins = "dap1";
130 nvidia,function = "dap1";
131 };
132 dap2 {
133 nvidia,pins = "dap2";
134 nvidia,function = "dap2";
135 };
136 dap3 {
137 nvidia,pins = "dap3";
138 nvidia,function = "dap3";
139 };
140 dap4 {
141 nvidia,pins = "dap4";
142 nvidia,function = "dap4";
143 };
144 dta {
145 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
146 nvidia,function = "vi";
147 };
148 dtf {
149 nvidia,pins = "dtf";
150 nvidia,function = "i2c3";
151 };
152 gmc {
153 nvidia,pins = "gmc";
154 nvidia,function = "uartd";
155 };
156 gmd {
157 nvidia,pins = "gmd";
158 nvidia,function = "sflash";
159 };
160 gpu {
161 nvidia,pins = "gpu";
162 nvidia,function = "pwm";
163 };
164 gpu7 {
165 nvidia,pins = "gpu7";
166 nvidia,function = "rtck";
167 };
168 gpv {
169 nvidia,pins = "gpv", "slxa";
170 nvidia,function = "pcie";
171 };
172 hdint {
173 nvidia,pins = "hdint";
174 nvidia,function = "hdmi";
175 };
176 i2cp {
177 nvidia,pins = "i2cp";
178 nvidia,function = "i2cp";
179 };
180 irrx {
181 nvidia,pins = "irrx", "irtx";
182 nvidia,function = "uartb";
183 };
184 kbca {
185 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
186 "kbce", "kbcf";
187 nvidia,function = "kbc";
188 };
189 lcsn {
190 nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
191 "lsdi", "lvp0";
192 nvidia,function = "rsvd4";
193 };
194 ld0 {
195 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
196 "ld5", "ld6", "ld7", "ld8", "ld9",
197 "ld10", "ld11", "ld12", "ld13", "ld14",
198 "ld15", "ld16", "ld17", "ldi", "lhp0",
199 "lhp1", "lhp2", "lhs", "lpp", "lsc0",
200 "lsc1", "lsck", "lsda", "lspi", "lvp1",
201 "lvs";
202 nvidia,function = "displaya";
203 };
204 owc {
205 nvidia,pins = "owc", "spdi", "spdo", "uac";
206 nvidia,function = "rsvd2";
207 };
208 pmc {
209 nvidia,pins = "pmc";
210 nvidia,function = "pwr_on";
211 };
212 rm {
213 nvidia,pins = "rm";
214 nvidia,function = "i2c1";
215 };
216 sdb {
217 nvidia,pins = "sdb", "sdc", "sdd", "slxc", "slxk";
218 nvidia,function = "sdio3";
219 };
220 sdio1 {
221 nvidia,pins = "sdio1";
222 nvidia,function = "sdio1";
223 };
224 slxd {
225 nvidia,pins = "slxd";
226 nvidia,function = "spdif";
227 };
228 spid {
229 nvidia,pins = "spid", "spie", "spif";
230 nvidia,function = "spi1";
231 };
232 spig {
233 nvidia,pins = "spig", "spih";
234 nvidia,function = "spi2_alt";
235 };
236 uaa {
237 nvidia,pins = "uaa", "uab", "uda";
238 nvidia,function = "ulpi";
239 };
240 uad {
241 nvidia,pins = "uad";
242 nvidia,function = "irda";
243 };
244 uca {
245 nvidia,pins = "uca", "ucb";
246 nvidia,function = "uartc";
247 };
248 conf_ata {
249 nvidia,pins = "ata", "atb", "atc", "atd",
250 "cdev1", "cdev2", "csus", "dap1",
251 "dap4", "dte", "dtf", "gma", "gmc",
252 "gme", "gpu", "gpu7", "gpv", "i2cp",
253 "irrx", "irtx", "pta", "rm",
254 "sdc", "sdd", "slxc", "slxd", "slxk",
255 "spdi", "spdo", "uac", "uad", "uda";
256 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
257 nvidia,tristate = <TEGRA_PIN_DISABLE>;
258 };
259 conf_ate {
260 nvidia,pins = "ate", "dap2", "dap3",
261 "gmd", "owc", "spia", "spib", "spic",
262 "spid", "spie";
263 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
264 nvidia,tristate = <TEGRA_PIN_ENABLE>;
265 };
266 conf_ck32 {
267 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
268 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
269 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
270 };
271 conf_crtp {
272 nvidia,pins = "crtp", "gmb", "slxa", "spig",
273 "spih";
274 nvidia,pull = <TEGRA_PIN_PULL_UP>;
275 nvidia,tristate = <TEGRA_PIN_ENABLE>;
276 };
277 conf_dta {
278 nvidia,pins = "dta", "dtb", "dtc", "dtd", "kbcb";
279 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
280 nvidia,tristate = <TEGRA_PIN_DISABLE>;
281 };
282 conf_dte {
283 nvidia,pins = "spif";
284 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
285 nvidia,tristate = <TEGRA_PIN_ENABLE>;
286 };
287 conf_hdint {
288 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
289 "lpw1", "lsck", "lsda", "lsdi",
290 "lvp0";
291 nvidia,tristate = <TEGRA_PIN_ENABLE>;
292 };
293 conf_kbca {
294 nvidia,pins = "kbca", "kbcc", "kbcd",
295 "kbce", "kbcf", "sdio1", "uaa",
296 "uab", "uca", "ucb";
297 nvidia,pull = <TEGRA_PIN_PULL_UP>;
298 nvidia,tristate = <TEGRA_PIN_DISABLE>;
299 };
300 conf_lc {
301 nvidia,pins = "lc", "ls";
302 nvidia,pull = <TEGRA_PIN_PULL_UP>;
303 };
304 conf_ld0 {
305 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
306 "ld5", "ld6", "ld7", "ld8", "ld9",
307 "ld10", "ld11", "ld12", "ld13", "ld14",
308 "ld15", "ld16", "ld17", "ldi", "lhp0",
309 "lhp1", "lhp2", "lhs", "lm0", "lpp",
310 "lpw0", "lpw2", "lsc0", "lsc1", "lspi",
311 "lvp1", "lvs", "pmc", "sdb";
312 nvidia,tristate = <TEGRA_PIN_DISABLE>;
313 };
314 conf_ld17_0 {
315 nvidia,pins = "ld17_0";
316 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
317 };
318 drive_ddc {
319 nvidia,pins = "drive_ddc",
320 "drive_vi1",
321 "drive_sdio1";
322 nvidia,pull-up-strength = <31>;
323 nvidia,pull-down-strength = <31>;
324 nvidia,schmitt = <TEGRA_PIN_ENABLE>;
325 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
326 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
327 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
328 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
329 };
330 drive_dbg {
331 nvidia,pins = "drive_dbg",
332 "drive_vi2",
333 "drive_at1",
334 "drive_ao1";
335 nvidia,pull-up-strength = <31>;
336 nvidia,pull-down-strength = <31>;
337 nvidia,schmitt = <TEGRA_PIN_ENABLE>;
338 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
339 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
340 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
341 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
342 };
343 };
344
345 state_i2cmux_ddc: pinmux-i2cmux-ddc {
346 ddc {
347 nvidia,pins = "ddc";
348 nvidia,function = "i2c2";
349 };
350
351 pta {
352 nvidia,pins = "pta";
353 nvidia,function = "rsvd4";
354 };
355 };
356
357 state_i2cmux_idle: pinmux-i2cmux-idle {
358 ddc {
359 nvidia,pins = "ddc";
360 nvidia,function = "rsvd4";
361 };
362
363 pta {
364 nvidia,pins = "pta";
365 nvidia,function = "rsvd4";
366 };
367 };
368
369 state_i2cmux_pta: pinmux-i2cmux-pta {
370 ddc {
371 nvidia,pins = "ddc";
372 nvidia,function = "rsvd4";
373 };
374
375 pta {
376 nvidia,pins = "pta";
377 nvidia,function = "i2c2";
378 };
379 };
380 };
381
382 tegra_spdif: spdif@70002400 {
383 status = "okay";
384
385 nvidia,fixed-parent-rate;
386 };
387
388 tegra_i2s1: i2s@70002800 {
389 status = "okay";
390
391 nvidia,fixed-parent-rate;
392 };
393
394 uartb: serial@70006040 {
395 compatible = "nvidia,tegra20-hsuart";
396 reset-names = "serial";
397 /delete-property/ reg-shift;
398 /* GPS BCM4751 */
399 };
400
401 uartc: serial@70006200 {
402 compatible = "nvidia,tegra20-hsuart";
403 reset-names = "serial";
404 /delete-property/ reg-shift;
405 status = "okay";
406
407 /* Azurewave AW-NH665 BCM4329B1 */
408 bluetooth {
409 compatible = "brcm,bcm4329-bt";
410
411 interrupt-parent = <&gpio>;
412 interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_EDGE_RISING>;
413 interrupt-names = "host-wakeup";
414
415 /* PLLP 216MHz / 16 / 4 */
416 max-speed = <3375000>;
417
418 clocks = <&rtc_32k_wifi>;
419 clock-names = "txco";
420
421 vbat-supply = <&vdd_3v3_sys>;
422 vddio-supply = <&vdd_1v8_sys>;
423
424 device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>;
425 shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
426 };
427 };
428
429 uartd: serial@70006300 {
430 /* Docking station */
431 };
432
433 pwm: pwm@7000a000 {
434 status = "okay";
435 };
436
437 i2c@7000c000 {
438 clock-frequency = <400000>;
439 status = "okay";
440
441 wm8903: audio-codec@1a {
442 compatible = "wlf,wm8903";
443 reg = <0x1a>;
444
445 interrupt-parent = <&gpio>;
446 interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_EDGE_BOTH>;
447
448 gpio-controller;
449 #gpio-cells = <2>;
450
451 micdet-cfg = <0>;
452 micdet-delay = <100>;
453
454 gpio-cfg = <
455 0x0000 /* MIC_LR_OUT# GPIO, output, low */
456 0x0000 /* FM2018-enable GPIO, output, low */
457 0x0000 /* Speaker-enable GPIO, output, low */
458 0x0200 /* Interrupt, output */
459 0x01a0 /* BCLK, input, active high */
460 >;
461
462 AVDD-supply = <&vdd_1v8_sys>;
463 CPVDD-supply = <&vdd_1v8_sys>;
464 DBVDD-supply = <&vdd_1v8_sys>;
465 DCVDD-supply = <&vdd_1v8_sys>;
466 };
467
468 touchscreen@4c {
469 compatible = "atmel,maxtouch";
470 reg = <0x4c>;
471
472 interrupt-parent = <&gpio>;
473 interrupts = <TEGRA_GPIO(V, 6) IRQ_TYPE_LEVEL_LOW>;
474
475 reset-gpios = <&gpio TEGRA_GPIO(Q, 7) GPIO_ACTIVE_LOW>;
476
477 vdda-supply = <&vdd_3v3_sys>;
478 vdd-supply = <&vdd_3v3_sys>;
479
480 atmel,wakeup-method = <ATMEL_MXT_WAKEUP_I2C_SCL>;
481 };
482
483 gyroscope@68 {
484 compatible = "invensense,mpu3050";
485 reg = <0x68>;
486
487 interrupt-parent = <&gpio>;
488 interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_EDGE_RISING>;
489
490 vdd-supply = <&vdd_3v3_sys>;
491 vlogic-supply = <&vdd_1v8_sys>;
492
493 mount-matrix = "0", "1", "0",
494 "1", "0", "0",
495 "0", "0", "-1";
496
497 i2c-gate {
498 #address-cells = <1>;
499 #size-cells = <0>;
500
501 accelerometer@f {
502 compatible = "kionix,kxtf9";
503 reg = <0x0f>;
504
505 interrupt-parent = <&gpio>;
506 interrupts = <TEGRA_GPIO(S, 7) IRQ_TYPE_EDGE_RISING>;
507
508 vdd-supply = <&vdd_1v8_sys>;
509 vddio-supply = <&vdd_1v8_sys>;
510
511 mount-matrix = "0", "1", "0",
512 "1", "0", "0",
513 "0", "0", "-1";
514 };
515 };
516 };
517 };
518
519 i2c@7000c400 {
520 clock-frequency = <10000>;
521 status = "okay";
522 };
523
524 i2c@7000d000 {
525 clock-frequency = <100000>;
526 status = "okay";
527
528 magnetometer@c {
529 compatible = "asahi-kasei,ak8975";
530 reg = <0x0c>;
531
532 interrupt-parent = <&gpio>;
533 interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_EDGE_RISING>;
534
535 vdd-supply = <&vdd_3v3_sys>;
536 vid-supply = <&vdd_1v8_sys>;
537
538 mount-matrix = "1", "0", "0",
539 "0", "-1", "0",
540 "0", "0", "-1";
541 };
542
543 pmic: pmic@34 {
544 compatible = "ti,tps6586x";
545 reg = <0x34>;
546
547 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
548
549 #gpio-cells = <2>;
550 gpio-controller;
551
552 sys-supply = <&vdd_5v0_sys>;
553 vin-sm0-supply = <&sys_reg>;
554 vin-sm1-supply = <&sys_reg>;
555 vin-sm2-supply = <&sys_reg>;
556 vinldo01-supply = <&sm2_reg>;
557 vinldo23-supply = <&sm2_reg>;
558 vinldo4-supply = <&sm2_reg>;
559 vinldo678-supply = <&sm2_reg>;
560 vinldo9-supply = <&sm2_reg>;
561
562 regulators {
563 sys_reg: sys {
564 regulator-name = "vdd_sys";
565 regulator-always-on;
566 };
567
568 vdd_core: sm0 {
569 regulator-name = "vdd_sm0,vdd_core";
570 regulator-min-microvolt = <950000>;
571 regulator-max-microvolt = <1300000>;
572 regulator-coupled-with = <&rtc_vdd &vdd_cpu>;
573 regulator-coupled-max-spread = <170000 550000>;
574 regulator-always-on;
575 regulator-boot-on;
576
577 nvidia,tegra-core-regulator;
578 };
579
580 vdd_cpu: sm1 {
581 regulator-name = "vdd_sm1,vdd_cpu";
582 regulator-min-microvolt = <750000>;
583 regulator-max-microvolt = <1125000>;
584 regulator-coupled-with = <&vdd_core &rtc_vdd>;
585 regulator-coupled-max-spread = <550000 550000>;
586 regulator-always-on;
587 regulator-boot-on;
588
589 nvidia,tegra-cpu-regulator;
590 };
591
592 sm2_reg: sm2 {
593 regulator-name = "vdd_sm2,vin_ldo*";
594 regulator-min-microvolt = <3700000>;
595 regulator-max-microvolt = <3700000>;
596 regulator-always-on;
597 };
598
599 /* LDO0 is not connected to anything */
600
601 ldo1 {
602 regulator-name = "vdd_ldo1,avdd_pll*";
603 regulator-min-microvolt = <1100000>;
604 regulator-max-microvolt = <1100000>;
605 regulator-always-on;
606 regulator-boot-on;
607 };
608
609 rtc_vdd: ldo2 {
610 regulator-name = "vdd_ldo2,vdd_rtc";
611 regulator-min-microvolt = <950000>;
612 regulator-max-microvolt = <1300000>;
613 regulator-coupled-with = <&vdd_core &vdd_cpu>;
614 regulator-coupled-max-spread = <170000 550000>;
615 regulator-always-on;
616 regulator-boot-on;
617
618 nvidia,tegra-rtc-regulator;
619 };
620
621 ldo3 {
622 regulator-name = "vdd_ldo3,avdd_usb*";
623 regulator-min-microvolt = <3300000>;
624 regulator-max-microvolt = <3300000>;
625 regulator-always-on;
626 };
627
628 ldo4 {
629 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
630 regulator-min-microvolt = <1800000>;
631 regulator-max-microvolt = <1800000>;
632 regulator-always-on;
633 regulator-boot-on;
634 };
635
636 vcore_emmc: ldo5 {
637 regulator-name = "vdd_ldo5,vcore_mmc";
638 regulator-min-microvolt = <2850000>;
639 regulator-max-microvolt = <2850000>;
640 regulator-always-on;
641 };
642
643 avdd_vdac_reg: ldo6 {
644 regulator-name = "vdd_ldo6,avdd_vdac";
645 regulator-min-microvolt = <2850000>;
646 regulator-max-microvolt = <2850000>;
647 };
648
649 hdmi_vdd_reg: ldo7 {
650 regulator-name = "vdd_ldo7,avdd_hdmi";
651 regulator-min-microvolt = <3300000>;
652 regulator-max-microvolt = <3300000>;
653 };
654
655 hdmi_pll_reg: ldo8 {
656 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
657 regulator-min-microvolt = <1800000>;
658 regulator-max-microvolt = <1800000>;
659 };
660
661 ldo9 {
662 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
663 regulator-min-microvolt = <2850000>;
664 regulator-max-microvolt = <2850000>;
665 regulator-always-on;
666 regulator-boot-on;
667 };
668
669 ldo_rtc {
670 regulator-name = "vdd_rtc_out,vdd_cell";
671 regulator-min-microvolt = <3300000>;
672 regulator-max-microvolt = <3300000>;
673 regulator-always-on;
674 regulator-boot-on;
675 };
676 };
677 };
678
679 nct1008: temperature-sensor@4c {
680 compatible = "onnn,nct1008";
681 reg = <0x4c>;
682 vcc-supply = <&vdd_3v3_sys>;
683
684 interrupt-parent = <&gpio>;
685 interrupts = <TEGRA_GPIO(N, 6) IRQ_TYPE_EDGE_FALLING>;
686
687 #thermal-sensor-cells = <1>;
688 };
689 };
690
691 pmc@7000e400 {
692 nvidia,invert-interrupt;
693 nvidia,suspend-mode = <1>;
694 nvidia,cpu-pwr-good-time = <2000>;
695 nvidia,cpu-pwr-off-time = <100>;
696 nvidia,core-pwr-good-time = <3845 3845>;
697 nvidia,core-pwr-off-time = <458>;
698 nvidia,sys-clock-req-active-high;
699 core-supply = <&vdd_core>;
700 };
701
702 memory-controller@7000f400 {
703 nvidia,use-ram-code;
704
705 emc-tables@0 {
706 nvidia,ram-code = <0>; /* elpida-8gb */
707 reg = <0>;
708
709 #address-cells = <1>;
710 #size-cells = <0>;
711
712 emc-table@25000 {
713 reg = <25000>;
714 compatible = "nvidia,tegra20-emc-table";
715 clock-frequency = <25000>;
716 nvidia,emc-registers = <0x00000002 0x00000006
717 0x00000003 0x00000003 0x00000006 0x00000004
718 0x00000002 0x00000009 0x00000003 0x00000003
719 0x00000002 0x00000002 0x00000002 0x00000004
720 0x00000003 0x00000008 0x0000000b 0x0000004d
721 0x00000000 0x00000003 0x00000003 0x00000003
722 0x00000008 0x00000001 0x0000000a 0x00000004
723 0x00000003 0x00000008 0x00000004 0x00000006
724 0x00000002 0x00000068 0x00000000 0x00000003
725 0x00000000 0x00000000 0x00000282 0xa0ae04ae
726 0x00070000 0x00000000 0x00000000 0x00000003
727 0x00000000 0x00000000 0x00000000 0x00000000>;
728 };
729
730 emc-table@50000 {
731 reg = <50000>;
732 compatible = "nvidia,tegra20-emc-table";
733 clock-frequency = <50000>;
734 nvidia,emc-registers = <0x00000003 0x00000007
735 0x00000003 0x00000003 0x00000006 0x00000004
736 0x00000002 0x00000009 0x00000003 0x00000003
737 0x00000002 0x00000002 0x00000002 0x00000005
738 0x00000003 0x00000008 0x0000000b 0x0000009f
739 0x00000000 0x00000003 0x00000003 0x00000003
740 0x00000008 0x00000001 0x0000000a 0x00000007
741 0x00000003 0x00000008 0x00000004 0x00000006
742 0x00000002 0x000000d0 0x00000000 0x00000000
743 0x00000000 0x00000000 0x00000282 0xa0ae04ae
744 0x00070000 0x00000000 0x00000000 0x00000005
745 0x00000000 0x00000000 0x00000000 0x00000000>;
746 };
747
748 emc-table@75000 {
749 reg = <75000>;
750 compatible = "nvidia,tegra20-emc-table";
751 clock-frequency = <75000>;
752 nvidia,emc-registers = <0x00000005 0x0000000a
753 0x00000004 0x00000003 0x00000006 0x00000004
754 0x00000002 0x00000009 0x00000003 0x00000003
755 0x00000002 0x00000002 0x00000002 0x00000005
756 0x00000003 0x00000008 0x0000000b 0x000000ff
757 0x00000000 0x00000003 0x00000003 0x00000003
758 0x00000008 0x00000001 0x0000000a 0x0000000b
759 0x00000003 0x00000008 0x00000004 0x00000006
760 0x00000002 0x00000138 0x00000000 0x00000000
761 0x00000000 0x00000000 0x00000282 0xa0ae04ae
762 0x00070000 0x00000000 0x00000000 0x00000007
763 0x00000000 0x00000000 0x00000000 0x00000000>;
764 };
765
766 emc-table@150000 {
767 reg = <150000>;
768 compatible = "nvidia,tegra20-emc-table";
769 clock-frequency = <150000>;
770 nvidia,emc-registers = <0x00000009 0x00000014
771 0x00000007 0x00000003 0x00000006 0x00000004
772 0x00000002 0x00000009 0x00000003 0x00000003
773 0x00000002 0x00000002 0x00000002 0x00000005
774 0x00000003 0x00000008 0x0000000b 0x0000021f
775 0x00000000 0x00000003 0x00000003 0x00000003
776 0x00000008 0x00000001 0x0000000a 0x00000015
777 0x00000003 0x00000008 0x00000004 0x00000006
778 0x00000002 0x00000270 0x00000000 0x00000001
779 0x00000000 0x00000000 0x00000282 0xa07c04ae
780 0x007dd510 0x00000000 0x00000000 0x0000000e
781 0x00000000 0x00000000 0x00000000 0x00000000>;
782 };
783
784 emc-table@300000 {
785 reg = <300000>;
786 compatible = "nvidia,tegra20-emc-table";
787 clock-frequency = <300000>;
788 nvidia,emc-registers = <0x00000012 0x00000027
789 0x0000000d 0x00000006 0x00000007 0x00000005
790 0x00000003 0x00000009 0x00000006 0x00000006
791 0x00000003 0x00000003 0x00000002 0x00000006
792 0x00000003 0x00000009 0x0000000c 0x0000045f
793 0x00000000 0x00000004 0x00000004 0x00000006
794 0x00000008 0x00000001 0x0000000e 0x0000002a
795 0x00000003 0x0000000f 0x00000007 0x00000005
796 0x00000002 0x000004e1 0x00000005 0x00000002
797 0x00000000 0x00000000 0x00000282 0xe059048b
798 0x007e1510 0x00000000 0x00000000 0x0000001b
799 0x00000000 0x00000000 0x00000000 0x00000000>;
800 };
801 };
802
803 emc-tables@1 {
804 nvidia,ram-code = <1>; /* elpida-4gb */
805 reg = <1>;
806
807 #address-cells = <1>;
808 #size-cells = <0>;
809
810 emc-table@25000 {
811 reg = <25000>;
812 compatible = "nvidia,tegra20-emc-table";
813 clock-frequency = <25000>;
814 nvidia,emc-registers = <0x00000002 0x00000006
815 0x00000003 0x00000003 0x00000006 0x00000004
816 0x00000002 0x00000009 0x00000003 0x00000003
817 0x00000002 0x00000002 0x00000002 0x00000004
818 0x00000003 0x00000008 0x0000000b 0x0000004d
819 0x00000000 0x00000003 0x00000003 0x00000003
820 0x00000008 0x00000001 0x0000000a 0x00000004
821 0x00000003 0x00000008 0x00000004 0x00000006
822 0x00000002 0x00000068 0x00000000 0x00000003
823 0x00000000 0x00000000 0x00000282 0xa0ae04ae
824 0x0007c000 0x00000000 0x00000000 0x00000003
825 0x00000000 0x00000000 0x00000000 0x00000000>;
826 };
827
828 emc-table@50000 {
829 reg = <50000>;
830 compatible = "nvidia,tegra20-emc-table";
831 clock-frequency = <50000>;
832 nvidia,emc-registers = <0x00000003 0x00000007
833 0x00000003 0x00000003 0x00000006 0x00000004
834 0x00000002 0x00000009 0x00000003 0x00000003
835 0x00000002 0x00000002 0x00000002 0x00000005
836 0x00000003 0x00000008 0x0000000b 0x0000009f
837 0x00000000 0x00000003 0x00000003 0x00000003
838 0x00000008 0x00000001 0x0000000a 0x00000007
839 0x00000003 0x00000008 0x00000004 0x00000006
840 0x00000002 0x000000d0 0x00000000 0x00000000
841 0x00000000 0x00000000 0x00000282 0xa0ae04ae
842 0x0007c000 0x00000000 0x00000000 0x00000005
843 0x00000000 0x00000000 0x00000000 0x00000000>;
844 };
845
846 emc-table@75000 {
847 reg = <75000>;
848 compatible = "nvidia,tegra20-emc-table";
849 clock-frequency = <75000>;
850 nvidia,emc-registers = <0x00000005 0x0000000a
851 0x00000004 0x00000003 0x00000006 0x00000004
852 0x00000002 0x00000009 0x00000003 0x00000003
853 0x00000002 0x00000002 0x00000002 0x00000005
854 0x00000003 0x00000008 0x0000000b 0x000000ff
855 0x00000000 0x00000003 0x00000003 0x00000003
856 0x00000008 0x00000001 0x0000000a 0x0000000b
857 0x00000003 0x00000008 0x00000004 0x00000006
858 0x00000002 0x00000138 0x00000000 0x00000000
859 0x00000000 0x00000000 0x00000282 0xa0ae04ae
860 0x0007c000 0x00000000 0x00000000 0x00000007
861 0x00000000 0x00000000 0x00000000 0x00000000>;
862 };
863
864 emc-table@150000 {
865 reg = <150000>;
866 compatible = "nvidia,tegra20-emc-table";
867 clock-frequency = <150000>;
868 nvidia,emc-registers = <0x00000009 0x00000014
869 0x00000007 0x00000003 0x00000006 0x00000004
870 0x00000002 0x00000009 0x00000003 0x00000003
871 0x00000002 0x00000002 0x00000002 0x00000005
872 0x00000003 0x00000008 0x0000000b 0x0000021f
873 0x00000000 0x00000003 0x00000003 0x00000003
874 0x00000008 0x00000001 0x0000000a 0x00000015
875 0x00000003 0x00000008 0x00000004 0x00000006
876 0x00000002 0x00000270 0x00000000 0x00000001
877 0x00000000 0x00000000 0x00000282 0xa07c04ae
878 0x007e4010 0x00000000 0x00000000 0x0000000e
879 0x00000000 0x00000000 0x00000000 0x00000000>;
880 };
881
882 emc-table@300000 {
883 reg = <300000>;
884 compatible = "nvidia,tegra20-emc-table";
885 clock-frequency = <300000>;
886 nvidia,emc-registers = <0x00000012 0x00000027
887 0x0000000d 0x00000006 0x00000007 0x00000005
888 0x00000003 0x00000009 0x00000006 0x00000006
889 0x00000003 0x00000003 0x00000002 0x00000006
890 0x00000003 0x00000009 0x0000000c 0x0000045f
891 0x00000000 0x00000004 0x00000004 0x00000006
892 0x00000008 0x00000001 0x0000000e 0x0000002a
893 0x00000003 0x0000000f 0x00000007 0x00000005
894 0x00000002 0x000004e1 0x00000005 0x00000002
895 0x00000000 0x00000000 0x00000282 0xe059048b
896 0x007e0010 0x00000000 0x00000000 0x0000001b
897 0x00000000 0x00000000 0x00000000 0x00000000>;
898 };
899 };
900
901 emc-tables@2 {
902 nvidia,ram-code = <2>; /* hynix-8gb */
903 reg = <2>;
904
905 #address-cells = <1>;
906 #size-cells = <0>;
907
908 emc-table@25000 {
909 reg = <25000>;
910 compatible = "nvidia,tegra20-emc-table";
911 clock-frequency = <25000>;
912 nvidia,emc-registers = <0x00000002 0x00000006
913 0x00000003 0x00000003 0x00000006 0x00000004
914 0x00000002 0x00000009 0x00000003 0x00000003
915 0x00000002 0x00000002 0x00000002 0x00000004
916 0x00000003 0x00000008 0x0000000b 0x0000004d
917 0x00000000 0x00000003 0x00000003 0x00000003
918 0x00000008 0x00000001 0x0000000a 0x00000004
919 0x00000003 0x00000008 0x00000004 0x00000006
920 0x00000002 0x00000068 0x00000000 0x00000003
921 0x00000000 0x00000000 0x00000282 0xa0ae04ae
922 0x00070000 0x00000000 0x00000000 0x00000003
923 0x00000000 0x00000000 0x00000000 0x00000000>;
924 };
925
926 emc-table@50000 {
927 reg = <50000>;
928 compatible = "nvidia,tegra20-emc-table";
929 clock-frequency = <50000>;
930 nvidia,emc-registers = <0x00000003 0x00000007
931 0x00000003 0x00000003 0x00000006 0x00000004
932 0x00000002 0x00000009 0x00000003 0x00000003
933 0x00000002 0x00000002 0x00000002 0x00000005
934 0x00000003 0x00000008 0x0000000b 0x0000009f
935 0x00000000 0x00000003 0x00000003 0x00000003
936 0x00000008 0x00000001 0x0000000a 0x00000007
937 0x00000003 0x00000008 0x00000004 0x00000006
938 0x00000002 0x000000d0 0x00000000 0x00000000
939 0x00000000 0x00000000 0x00000282 0xa0ae04ae
940 0x00070000 0x00000000 0x00000000 0x00000005
941 0x00000000 0x00000000 0x00000000 0x00000000>;
942 };
943
944 emc-table@75000 {
945 reg = <75000>;
946 compatible = "nvidia,tegra20-emc-table";
947 clock-frequency = <75000>;
948 nvidia,emc-registers = <0x00000005 0x0000000a
949 0x00000004 0x00000003 0x00000006 0x00000004
950 0x00000002 0x00000009 0x00000003 0x00000003
951 0x00000002 0x00000002 0x00000002 0x00000005
952 0x00000003 0x00000008 0x0000000b 0x000000ff
953 0x00000000 0x00000003 0x00000003 0x00000003
954 0x00000008 0x00000001 0x0000000a 0x0000000b
955 0x00000003 0x00000008 0x00000004 0x00000006
956 0x00000002 0x00000138 0x00000000 0x00000000
957 0x00000000 0x00000000 0x00000282 0xa0ae04ae
958 0x00070000 0x00000000 0x00000000 0x00000007
959 0x00000000 0x00000000 0x00000000 0x00000000>;
960 };
961
962 emc-table@150000 {
963 reg = <150000>;
964 compatible = "nvidia,tegra20-emc-table";
965 clock-frequency = <150000>;
966 nvidia,emc-registers = <0x00000009 0x00000014
967 0x00000007 0x00000003 0x00000006 0x00000004
968 0x00000002 0x00000009 0x00000003 0x00000003
969 0x00000002 0x00000002 0x00000002 0x00000005
970 0x00000003 0x00000008 0x0000000b 0x0000021f
971 0x00000000 0x00000003 0x00000003 0x00000003
972 0x00000008 0x00000001 0x0000000a 0x00000015
973 0x00000003 0x00000008 0x00000004 0x00000006
974 0x00000002 0x00000270 0x00000000 0x00000001
975 0x00000000 0x00000000 0x00000282 0xa07c04ae
976 0x007dd010 0x00000000 0x00000000 0x0000000e
977 0x00000000 0x00000000 0x00000000 0x00000000>;
978 };
979
980 emc-table@300000 {
981 reg = <300000>;
982 compatible = "nvidia,tegra20-emc-table";
983 clock-frequency = <300000>;
984 nvidia,emc-registers = <0x00000012 0x00000027
985 0x0000000d 0x00000006 0x00000007 0x00000005
986 0x00000003 0x00000009 0x00000006 0x00000006
987 0x00000003 0x00000003 0x00000002 0x00000006
988 0x00000003 0x00000009 0x0000000c 0x0000045f
989 0x00000000 0x00000004 0x00000004 0x00000006
990 0x00000008 0x00000001 0x0000000e 0x0000002a
991 0x00000003 0x0000000f 0x00000007 0x00000005
992 0x00000002 0x000004e1 0x00000005 0x00000002
993 0x00000000 0x00000000 0x00000282 0xe059048b
994 0x007e2010 0x00000000 0x00000000 0x0000001b
995 0x00000000 0x00000000 0x00000000 0x00000000>;
996 };
997 };
998
999 emc-tables@3 {
1000 nvidia,ram-code = <3>; /* hynix-4gb */
1001 reg = <3>;
1002
1003 #address-cells = <1>;
1004 #size-cells = <0>;
1005
1006 emc-table@25000 {
1007 reg = <25000>;
1008 compatible = "nvidia,tegra20-emc-table";
1009 clock-frequency = <25000>;
1010 nvidia,emc-registers = <0x00000002 0x00000006
1011 0x00000003 0x00000003 0x00000006 0x00000004
1012 0x00000002 0x00000009 0x00000003 0x00000003
1013 0x00000002 0x00000002 0x00000002 0x00000004
1014 0x00000003 0x00000008 0x0000000b 0x0000004d
1015 0x00000000 0x00000003 0x00000003 0x00000003
1016 0x00000008 0x00000001 0x0000000a 0x00000004
1017 0x00000003 0x00000008 0x00000004 0x00000006
1018 0x00000002 0x00000068 0x00000000 0x00000003
1019 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1020 0x0007c000 0x00000000 0x00000000 0x00000003
1021 0x00000000 0x00000000 0x00000000 0x00000000>;
1022 };
1023
1024 emc-table@50000 {
1025 reg = <50000>;
1026 compatible = "nvidia,tegra20-emc-table";
1027 clock-frequency = <50000>;
1028 nvidia,emc-registers = <0x00000003 0x00000007
1029 0x00000003 0x00000003 0x00000006 0x00000004
1030 0x00000002 0x00000009 0x00000003 0x00000003
1031 0x00000002 0x00000002 0x00000002 0x00000005
1032 0x00000003 0x00000008 0x0000000b 0x0000009f
1033 0x00000000 0x00000003 0x00000003 0x00000003
1034 0x00000008 0x00000001 0x0000000a 0x00000007
1035 0x00000003 0x00000008 0x00000004 0x00000006
1036 0x00000002 0x000000d0 0x00000000 0x00000000
1037 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1038 0x0007c000 0x00078000 0x00000000 0x00000005
1039 0x00000000 0x00000000 0x00000000 0x00000000>;
1040 };
1041
1042 emc-table@75000 {
1043 reg = <75000>;
1044 compatible = "nvidia,tegra20-emc-table";
1045 clock-frequency = <75000>;
1046 nvidia,emc-registers = <0x00000005 0x0000000a
1047 0x00000004 0x00000003 0x00000006 0x00000004
1048 0x00000002 0x00000009 0x00000003 0x00000003
1049 0x00000002 0x00000002 0x00000002 0x00000005
1050 0x00000003 0x00000008 0x0000000b 0x000000ff
1051 0x00000000 0x00000003 0x00000003 0x00000003
1052 0x00000008 0x00000001 0x0000000a 0x0000000b
1053 0x00000003 0x00000008 0x00000004 0x00000006
1054 0x00000002 0x00000138 0x00000000 0x00000000
1055 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1056 0x0007c000 0x00000000 0x00000000 0x00000007
1057 0x00000000 0x00000000 0x00000000 0x00000000>;
1058 };
1059
1060 emc-table@150000 {
1061 reg = <150000>;
1062 compatible = "nvidia,tegra20-emc-table";
1063 clock-frequency = <150000>;
1064 nvidia,emc-registers = <0x00000009 0x00000014
1065 0x00000007 0x00000003 0x00000006 0x00000004
1066 0x00000002 0x00000009 0x00000003 0x00000003
1067 0x00000002 0x00000002 0x00000002 0x00000005
1068 0x00000003 0x00000008 0x0000000b 0x0000021f
1069 0x00000000 0x00000003 0x00000003 0x00000003
1070 0x00000008 0x00000001 0x0000000a 0x00000015
1071 0x00000003 0x00000008 0x00000004 0x00000006
1072 0x00000002 0x00000270 0x00000000 0x00000001
1073 0x00000000 0x00000000 0x00000282 0xa07c04ae
1074 0x007e4010 0x00000000 0x00000000 0x0000000e
1075 0x00000000 0x00000000 0x00000000 0x00000000>;
1076 };
1077
1078 emc-table@300000 {
1079 reg = <300000>;
1080 compatible = "nvidia,tegra20-emc-table";
1081 clock-frequency = <300000>;
1082 nvidia,emc-registers = <0x00000012 0x00000027
1083 0x0000000d 0x00000006 0x00000007 0x00000005
1084 0x00000003 0x00000009 0x00000006 0x00000006
1085 0x00000003 0x00000003 0x00000002 0x00000006
1086 0x00000003 0x00000009 0x0000000c 0x0000045f
1087 0x00000000 0x00000004 0x00000004 0x00000006
1088 0x00000008 0x00000001 0x0000000e 0x0000002a
1089 0x00000003 0x0000000f 0x00000007 0x00000005
1090 0x00000002 0x000004e1 0x00000005 0x00000002
1091 0x00000000 0x00000000 0x00000282 0xe059048b
1092 0x007e0010 0x00000000 0x00000000 0x0000001b
1093 0x00000000 0x00000000 0x00000000 0x00000000>;
1094 };
1095 };
1096 };
1097
1098 usb@c5000000 {
1099 compatible = "nvidia,tegra20-udc";
1100 status = "okay";
1101 dr_mode = "peripheral";
1102 };
1103
1104 usb-phy@c5000000 {
1105 status = "okay";
1106 dr_mode = "peripheral";
1107 nvidia,xcvr-setup-use-fuses;
1108 nvidia,xcvr-lsfslew = <2>;
1109 nvidia,xcvr-lsrslew = <2>;
1110 };
1111
1112 usb@c5008000 {
1113 status = "okay";
1114 };
1115
1116 usb-phy@c5008000 {
1117 status = "okay";
1118 nvidia,xcvr-setup-use-fuses;
1119 nvidia,xcvr-lsfslew = <2>;
1120 nvidia,xcvr-lsrslew = <2>;
1121 vbus-supply = <&vdd_5v0_sys>;
1122 };
1123
1124 sdmmc1: mmc@c8000000 {
1125 status = "okay";
1126
1127 #address-cells = <1>;
1128 #size-cells = <0>;
1129
1130 assigned-clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
1131 assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>;
1132 assigned-clock-rates = <50000000>;
1133
1134 max-frequency = <50000000>;
1135 keep-power-in-suspend;
1136 bus-width = <4>;
1137 non-removable;
1138
1139 mmc-pwrseq = <&brcm_wifi_pwrseq>;
1140 vmmc-supply = <&vdd_3v3_sys>;
1141 vqmmc-supply = <&vdd_1v8_sys>;
1142
1143 /* Azurewave AW-NH611 BCM4329 */
1144 wifi@1 {
1145 reg = <1>;
1146 compatible = "brcm,bcm4329-fmac";
1147 interrupt-parent = <&gpio>;
1148 interrupts = <TEGRA_GPIO(S, 0) IRQ_TYPE_LEVEL_HIGH>;
1149 interrupt-names = "host-wake";
1150 };
1151 };
1152
1153 sdmmc3: mmc@c8000400 {
1154 status = "okay";
1155 bus-width = <4>;
1156 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
1157 power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
1158 vmmc-supply = <&vdd_3v3_sys>;
1159 vqmmc-supply = <&vdd_3v3_sys>;
1160 };
1161
1162 sdmmc4: mmc@c8000600 {
1163 status = "okay";
1164 bus-width = <8>;
1165 vmmc-supply = <&vcore_emmc>;
1166 vqmmc-supply = <&vdd_3v3_sys>;
1167 non-removable;
1168 };
1169
1170 mains: ac-adapter-detect {
1171 compatible = "gpio-charger";
1172 charger-type = "mains";
1173 gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>;
1174 };
1175
1176 backlight: backlight {
1177 compatible = "pwm-backlight";
1178
1179 enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
1180 power-supply = <&vdd_3v3_sys>;
1181 pwms = <&pwm 2 41667>;
1182
1183 brightness-levels = <7 255>;
1184 num-interpolated-steps = <248>;
1185 default-brightness-level = <20>;
1186 };
1187
1188 bat1010: battery-2s1p {
1189 compatible = "simple-battery";
1190 charge-full-design-microamp-hours = <3260000>;
1191 energy-full-design-microwatt-hours = <24000000>;
1192 operating-range-celsius = <0 40>;
1193 };
1194
1195 /* PMIC has a built-in 32KHz oscillator which is used by PMC */
1196 clk32k_in: clock-32k-in {
1197 compatible = "fixed-clock";
1198 #clock-cells = <0>;
1199 clock-frequency = <32768>;
1200 clock-output-names = "tps658621-out32k";
1201 };
1202
1203 /*
1204 * This standalone onboard fixed-clock always-ON 32KHz
1205 * oscillator is used as a reference clock-source by the
1206 * Azurewave WiFi/BT module.
1207 */
1208 rtc_32k_wifi: clock-32k-wifi {
1209 compatible = "fixed-clock";
1210 #clock-cells = <0>;
1211 clock-frequency = <32768>;
1212 clock-output-names = "kk3270032";
1213 };
1214
1215 cpus {
1216 cpu0: cpu@0 {
1217 cpu-supply = <&vdd_cpu>;
1218 operating-points-v2 = <&cpu0_opp_table>;
1219 #cooling-cells = <2>;
1220 };
1221
1222 cpu1: cpu@1 {
1223 cpu-supply = <&vdd_cpu>;
1224 operating-points-v2 = <&cpu0_opp_table>;
1225 #cooling-cells = <2>;
1226 };
1227 };
1228
1229 display-panel {
1230 compatible = "auo,b101ew05", "panel-lvds";
1231
1232 ddc-i2c-bus = <&panel_ddc>;
1233 power-supply = <&vdd_pnl>;
1234 backlight = <&backlight>;
1235
1236 width-mm = <218>;
1237 height-mm = <135>;
1238
1239 data-mapping = "jeida-18";
1240
1241 panel-timing {
1242 clock-frequency = <71200000>;
1243 hactive = <1280>;
1244 vactive = <800>;
1245 hfront-porch = <8>;
1246 hback-porch = <18>;
1247 hsync-len = <184>;
1248 vsync-len = <3>;
1249 vfront-porch = <4>;
1250 vback-porch = <8>;
1251 };
1252
1253 port {
1254 panel_input: endpoint {
1255 remote-endpoint = <&lvds_encoder_output>;
1256 };
1257 };
1258 };
1259
1260 gpio-keys {
1261 compatible = "gpio-keys";
1262
1263 key-power {
1264 label = "Power";
1265 gpios = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>;
1266 linux,code = <KEY_POWER>;
1267 debounce-interval = <10>;
1268 wakeup-event-action = <EV_ACT_ASSERTED>;
1269 wakeup-source;
1270 };
1271
1272 key-rotation-lock {
1273 label = "Rotate-lock";
1274 gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_HIGH>;
1275 linux,code = <SW_ROTATE_LOCK>;
1276 linux,input-type = <EV_SW>;
1277 debounce-interval = <10>;
1278 };
1279
1280 key-volume-down {
1281 label = "Volume Down";
1282 gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>;
1283 linux,code = <KEY_VOLUMEDOWN>;
1284 debounce-interval = <10>;
1285 wakeup-event-action = <EV_ACT_ASSERTED>;
1286 wakeup-source;
1287 };
1288
1289 key-volume-up {
1290 label = "Volume Up";
1291 gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
1292 linux,code = <KEY_VOLUMEUP>;
1293 debounce-interval = <10>;
1294 wakeup-event-action = <EV_ACT_ASSERTED>;
1295 wakeup-source;
1296 };
1297 };
1298
1299 haptic-feedback {
1300 compatible = "gpio-vibrator";
1301 enable-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
1302 vcc-supply = <&vdd_3v3_sys>;
1303 };
1304
1305 i2cmux {
1306 compatible = "i2c-mux-pinctrl";
1307 #address-cells = <1>;
1308 #size-cells = <0>;
1309
1310 i2c-parent = <&{/i2c@7000c400}>;
1311
1312 pinctrl-names = "ddc", "pta", "idle";
1313 pinctrl-0 = <&state_i2cmux_ddc>;
1314 pinctrl-1 = <&state_i2cmux_pta>;
1315 pinctrl-2 = <&state_i2cmux_idle>;
1316
1317 hdmi_ddc: i2c@0 {
1318 reg = <0>;
1319 #address-cells = <1>;
1320 #size-cells = <0>;
1321 };
1322
1323 panel_ddc: i2c@1 {
1324 reg = <1>;
1325 #address-cells = <1>;
1326 #size-cells = <0>;
1327
1328 embedded-controller@58 {
1329 compatible = "acer,a500-iconia-ec", "ene,kb930";
1330 reg = <0x58>;
1331
1332 system-power-controller;
1333
1334 monitored-battery = <&bat1010>;
1335 power-supplies = <&mains>;
1336 };
1337 };
1338 };
1339
1340 lvds-encoder {
1341 compatible = "ti,sn75lvds83", "lvds-encoder";
1342
1343 powerdown-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_LOW>;
1344 power-supply = <&vdd_3v3_sys>;
1345
1346 ports {
1347 #address-cells = <1>;
1348 #size-cells = <0>;
1349
1350 port@0 {
1351 reg = <0>;
1352
1353 lvds_encoder_input: endpoint {
1354 remote-endpoint = <&lcd_output>;
1355 };
1356 };
1357
1358 port@1 {
1359 reg = <1>;
1360
1361 lvds_encoder_output: endpoint {
1362 remote-endpoint = <&panel_input>;
1363 };
1364 };
1365 };
1366 };
1367
1368 opp-table-emc {
1369 /delete-node/ opp-666000000;
1370 /delete-node/ opp-760000000;
1371 };
1372
1373 vdd_5v0_sys: regulator-5v0 {
1374 compatible = "regulator-fixed";
1375 regulator-name = "vdd_5v0";
1376 regulator-min-microvolt = <5000000>;
1377 regulator-max-microvolt = <5000000>;
1378 regulator-always-on;
1379 };
1380
1381 vdd_3v3_sys: regulator-3v3 {
1382 compatible = "regulator-fixed";
1383 regulator-name = "vdd_3v3_vs";
1384 regulator-min-microvolt = <3300000>;
1385 regulator-max-microvolt = <3300000>;
1386 regulator-always-on;
1387 vin-supply = <&vdd_5v0_sys>;
1388 };
1389
1390 vdd_1v8_sys: regulator-1v8 {
1391 compatible = "regulator-fixed";
1392 regulator-name = "vdd_1v8_vs";
1393 regulator-min-microvolt = <1800000>;
1394 regulator-max-microvolt = <1800000>;
1395 regulator-always-on;
1396 vin-supply = <&vdd_5v0_sys>;
1397 };
1398
1399 vdd_pnl: regulator-panel {
1400 compatible = "regulator-fixed";
1401 regulator-name = "vdd_panel";
1402 regulator-min-microvolt = <3300000>;
1403 regulator-max-microvolt = <3300000>;
1404 regulator-enable-ramp-delay = <300000>;
1405 gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
1406 enable-active-high;
1407 vin-supply = <&vdd_5v0_sys>;
1408 };
1409
1410 sound {
1411 compatible = "nvidia,tegra-audio-wm8903-picasso",
1412 "nvidia,tegra-audio-wm8903";
1413 nvidia,model = "Acer Iconia Tab A500 WM8903";
1414
1415 nvidia,audio-routing =
1416 "Headphone Jack", "HPOUTR",
1417 "Headphone Jack", "HPOUTL",
1418 "Int Spk", "LINEOUTL",
1419 "Int Spk", "LINEOUTR",
1420 "Mic Jack", "MICBIAS",
1421 "IN2L", "Mic Jack",
1422 "IN2R", "Mic Jack",
1423 "IN1L", "Int Mic",
1424 "IN1R", "Int Mic";
1425
1426 nvidia,i2s-controller = <&tegra_i2s1>;
1427 nvidia,audio-codec = <&wm8903>;
1428
1429 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
1430 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
1431 nvidia,int-mic-en-gpios = <&wm8903 1 GPIO_ACTIVE_HIGH>;
1432 nvidia,headset;
1433
1434 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
1435 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
1436 <&tegra_car TEGRA20_CLK_CDEV1>;
1437 clock-names = "pll_a", "pll_a_out0", "mclk";
1438 };
1439
1440 thermal-zones {
1441 /*
1442 * NCT1008 has two sensors:
1443 *
1444 * 0: internal that monitors ambient/skin temperature
1445 * 1: external that is connected to the CPU's diode
1446 *
1447 * Ideally we should use userspace thermal governor,
1448 * but it's a much more complex solution. The "skin"
1449 * zone is a simpler solution which prevents A500 from
1450 * getting too hot from a user's tactile perspective.
1451 * The CPU zone is intended to protect silicon from damage.
1452 */
1453
1454 skin-thermal {
1455 polling-delay-passive = <1000>; /* milliseconds */
1456 polling-delay = <5000>; /* milliseconds */
1457
1458 thermal-sensors = <&nct1008 0>;
1459
1460 trips {
1461 trip0: skin-alert {
1462 /* start throttling at 60C */
1463 temperature = <60000>;
1464 hysteresis = <200>;
1465 type = "passive";
1466 };
1467
1468 trip1: skin-crit {
1469 /* shut down at 70C */
1470 temperature = <70000>;
1471 hysteresis = <2000>;
1472 type = "critical";
1473 };
1474 };
1475
1476 cooling-maps {
1477 map0 {
1478 trip = <&trip0>;
1479 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1480 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1481 };
1482 };
1483 };
1484
1485 cpu-thermal {
1486 polling-delay-passive = <1000>; /* milliseconds */
1487 polling-delay = <5000>; /* milliseconds */
1488
1489 thermal-sensors = <&nct1008 1>;
1490
1491 trips {
1492 trip2: cpu-alert {
1493 /* throttle at 85C until temperature drops to 84.8C */
1494 temperature = <85000>;
1495 hysteresis = <200>;
1496 type = "passive";
1497 };
1498
1499 trip3: cpu-crit {
1500 /* shut down at 90C */
1501 temperature = <90000>;
1502 hysteresis = <2000>;
1503 type = "critical";
1504 };
1505 };
1506
1507 cooling-maps {
1508 map1 {
1509 trip = <&trip2>;
1510 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1511 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1512 };
1513 };
1514 };
1515 };
1516
1517 brcm_wifi_pwrseq: wifi-pwrseq {
1518 compatible = "mmc-pwrseq-simple";
1519
1520 clocks = <&rtc_32k_wifi>;
1521 clock-names = "ext_clock";
1522
1523 reset-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_LOW>;
1524 post-power-on-delay-ms = <300>;
1525 power-off-delay-us = <300>;
1526 };
1527};