| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | // SPDX-License-Identifier: ISC |
| 2 | /* |
| 3 | * Device Tree file for the Intel KIXRP435 Control Plane |
| 4 | * processor reference design. |
| 5 | */ |
| 6 | |
| 7 | /dts-v1/; |
| 8 | |
| 9 | #include "intel-ixp43x.dtsi" |
| 10 | #include "intel-ixp4xx-reference-design.dtsi" |
| 11 | #include <dt-bindings/input/input.h> |
| 12 | |
| 13 | / { |
| 14 | model = "Intel KIXRP435 Reference Design"; |
| 15 | compatible = "intel,kixrp435", "intel,ixp43x"; |
| 16 | #address-cells = <1>; |
| 17 | #size-cells = <1>; |
| 18 | |
| 19 | soc { |
| 20 | bus@c4000000 { |
| 21 | flash@0,0 { |
| 22 | compatible = "intel,ixp4xx-flash", "cfi-flash"; |
| 23 | bank-width = <2>; |
| 24 | /* Enable writes on the expansion bus */ |
| 25 | intel,ixp4xx-eb-write-enable = <1>; |
| 26 | /* 16 MB of Flash mapped in at CS0 */ |
| 27 | reg = <0 0x00000000 0x1000000>; |
| 28 | |
| 29 | partitions { |
| 30 | compatible = "redboot-fis"; |
| 31 | /* Eraseblock at 0x0fe0000 */ |
| 32 | fis-index-block = <0x7f>; |
| 33 | }; |
| 34 | }; |
| 35 | }; |
| 36 | |
| 37 | /* CHECKME: ethernet set-up taken from Gateworks Cambria */ |
| 38 | ethernet@c800a000 { |
| 39 | status = "okay"; |
| 40 | queue-rx = <&qmgr 4>; |
| 41 | queue-txready = <&qmgr 21>; |
| 42 | phy-mode = "rgmii"; |
| 43 | phy-handle = <&phy1>; |
| 44 | |
| 45 | mdio { |
| 46 | #address-cells = <1>; |
| 47 | #size-cells = <0>; |
| 48 | |
| 49 | phy1: ethernet-phy@1 { |
| 50 | reg = <1>; |
| 51 | }; |
| 52 | |
| 53 | phy2: ethernet-phy@2 { |
| 54 | reg = <2>; |
| 55 | }; |
| 56 | }; |
| 57 | }; |
| 58 | |
| 59 | ethernet@c800c000 { |
| 60 | status = "okay"; |
| 61 | queue-rx = <&qmgr 2>; |
| 62 | queue-txready = <&qmgr 19>; |
| 63 | phy-mode = "rgmii"; |
| 64 | phy-handle = <&phy2>; |
| 65 | intel,npe-handle = <&npe 0>; |
| 66 | }; |
| 67 | }; |
| 68 | }; |