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git01.mediatek.com / filogic / uboot / c31f901b7c095a32d4809608d6598ecd8fee50e4 / . / arch / xtensa / include / asm / arch-dc232b / tie-asm.h
blob: 9c6b1eeacd00e02beea366fbcaebc1a4ccf7d145 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Chris Zankel20efd8c2016-08-10 18:36:45 +0300[diff] [blame]2/*
3 * This header file contains assembly-language definitions (assembly
4 * macros, etc.) for this specific Xtensa processor's TIE extensions
5 * and options. It is customized to this Xtensa processor configuration.
6 * This file is autogenerated, please do not edit.
7 *
8 * Copyright (C) 1999-2007 Tensilica Inc.
Chris Zankel20efd8c2016-08-10 18:36:45 +0300[diff] [blame]9 */
10
11#ifndef _XTENSA_CORE_TIE_ASM_H
12#define _XTENSA_CORE_TIE_ASM_H
13
14/* Selection parameter values for save-area save/restore macros: */
15/* Option vs. TIE: */
16#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
17#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
18/* Whether used automatically by compiler: */
19#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
20#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
21/* ABI handling across function calls: */
22#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
23#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
24#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
25/* Misc */
26#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
27
Chris Zankel20efd8c2016-08-10 18:36:45 +0300[diff] [blame]28/* Macro to save all non-coprocessor (extra) custom TIE and optional state
29 * (not including zero-overhead loop registers).
30 * Save area ptr (clobbered): ptr (1 byte aligned)
31 * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed)
32 */
33 .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
34 xchal_sa_start \continue, \ofs
35 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~\select
36 xchal_sa_align \ptr, 0, 1024-8, 4, 4
37 rsr \at1, ACCLO // MAC16 accumulator
38 rsr \at2, ACCHI
39 s32i \at1, \ptr, .Lxchal_ofs_ + 0
40 s32i \at2, \ptr, .Lxchal_ofs_ + 4
41 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
42 .endif
43 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
44 xchal_sa_align \ptr, 0, 1024-16, 4, 4
45 rsr \at1, M0 // MAC16 registers
46 rsr \at2, M1
47 s32i \at1, \ptr, .Lxchal_ofs_ + 0
48 s32i \at2, \ptr, .Lxchal_ofs_ + 4
49 rsr \at1, M2
50 rsr \at2, M3
51 s32i \at1, \ptr, .Lxchal_ofs_ + 8
52 s32i \at2, \ptr, .Lxchal_ofs_ + 12
53 .set .Lxchal_ofs_, .Lxchal_ofs_ + 16
54 .endif
55 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
56 xchal_sa_align \ptr, 0, 1024-4, 4, 4
57 rsr \at1, SCOMPARE1 // conditional store option
58 s32i \at1, \ptr, .Lxchal_ofs_ + 0
59 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
60 .endif
61 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select
62 xchal_sa_align \ptr, 0, 1024-4, 4, 4
63 rur \at1, THREADPTR // threadptr option
64 s32i \at1, \ptr, .Lxchal_ofs_ + 0
65 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
66 .endif
67 .endm // xchal_ncp_store
68
69/* Macro to save all non-coprocessor (extra) custom TIE and optional state
70 * (not including zero-overhead loop registers).
71 * Save area ptr (clobbered): ptr (1 byte aligned)
72 * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed)
73 */
74 .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
75 xchal_sa_start \continue, \ofs
76 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~\select
77 xchal_sa_align \ptr, 0, 1024-8, 4, 4
78 l32i \at1, \ptr, .Lxchal_ofs_ + 0
79 l32i \at2, \ptr, .Lxchal_ofs_ + 4
80 wsr \at1, ACCLO // MAC16 accumulator
81 wsr \at2, ACCHI
82 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
83 .endif
84 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
85 xchal_sa_align \ptr, 0, 1024-16, 4, 4
86 l32i \at1, \ptr, .Lxchal_ofs_ + 0
87 l32i \at2, \ptr, .Lxchal_ofs_ + 4
88 wsr \at1, M0 // MAC16 registers
89 wsr \at2, M1
90 l32i \at1, \ptr, .Lxchal_ofs_ + 8
91 l32i \at2, \ptr, .Lxchal_ofs_ + 12
92 wsr \at1, M2
93 wsr \at2, M3
94 .set .Lxchal_ofs_, .Lxchal_ofs_ + 16
95 .endif
96 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
97 xchal_sa_align \ptr, 0, 1024-4, 4, 4
98 l32i \at1, \ptr, .Lxchal_ofs_ + 0
99 wsr \at1, SCOMPARE1 // conditional store option
100 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
101 .endif
102 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select
103 xchal_sa_align \ptr, 0, 1024-4, 4, 4
104 l32i \at1, \ptr, .Lxchal_ofs_ + 0
105 wur \at1, THREADPTR // threadptr option
106 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
107 .endif
108 .endm // xchal_ncp_load
109
Chris Zankel20efd8c2016-08-10 18:36:45 +0300[diff] [blame]110#define XCHAL_NCP_NUM_ATMPS 2
111
Chris Zankel20efd8c2016-08-10 18:36:45 +0300[diff] [blame]112#define XCHAL_SA_NUM_ATMPS 2
113
114#endif /*_XTENSA_CORE_TIE_ASM_H*/