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git01.mediatek.com / filogic / uboot / c31f901b7c095a32d4809608d6598ecd8fee50e4 / . / arch / arm / mach-k3 / r5 / j722s / clk-data.c
blob: b4f27af333db3612ef2bc801a16a53442944c7e3 [file] [log] [blame]
Jayesh Choudhary9332a6372024-06-12 14:41:16 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * J722S specific clock platform data
4 *
5 * This file is auto generated. Please do not hand edit and report any issues
6 * to Bryan Brattlof <bb@ti.com>.
7 *
8 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
9 */
10
11#include <linux/clk-provider.h>
12#include "k3-clk.h"
13
14static const char * const gluelogic_hfosc0_clkout_parents[] = {
15 NULL,
16 NULL,
17 "osc_24_mhz",
18 "osc_25_mhz",
19 "osc_26_mhz",
20 NULL,
21};
22
23static const char * const clk_32k_rc_sel_out0_parents[] = {
24 "gluelogic_rcosc_clk_1p0v_97p65k",
25 "gluelogic_hfosc0_clkout",
26 "gluelogic_rcosc_clk_1p0v_97p65k",
27 "gluelogic_lfosc0_clkout",
28};
29
30static const char * const main_emmcsd1_io_clklb_sel_out0_parents[] = {
31 "board_0_mmc1_clklb_out",
32 "board_0_mmc1_clk_out",
33};
34
35static const char * const main_ospi_loopback_clk_sel_out0_parents[] = {
36 "board_0_ospi0_dqs_out",
37 "board_0_ospi0_lbclko_out",
38};
39
40static const char * const main_usb0_refclk_sel_out0_parents[] = {
41 "gluelogic_hfosc0_clkout",
42 "postdiv4_16ff_main_0_hsdivout8_clk",
43};
44
45static const char * const sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = {
46 "gluelogic_hfosc0_clkout",
47 "hsdiv4_16fft_main_0_hsdivout0_clk",
48};
49
50static const char * const sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents[] = {
51 "gluelogic_hfosc0_clkout",
52 "hsdiv4_16fft_mcu_0_hsdivout0_clk",
53};
54
55static const char * const clkout0_ctrl_out0_parents[] = {
56 "hsdiv4_16fft_main_2_hsdivout1_clk",
57 "hsdiv4_16fft_main_2_hsdivout1_clk",
58};
59
60static const char * const main_emmcsd0_refclk_sel_out0_parents[] = {
61 "postdiv4_16ff_main_0_hsdivout5_clk",
62 "hsdiv4_16fft_main_2_hsdivout2_clk",
63};
64
65static const char * const main_emmcsd1_refclk_sel_out0_parents[] = {
66 "postdiv4_16ff_main_0_hsdivout5_clk",
67 "hsdiv4_16fft_main_2_hsdivout2_clk",
68};
69
70static const char * const main_gtcclk_sel_out0_parents[] = {
71 "postdiv4_16ff_main_2_hsdivout5_clk",
72 "postdiv4_16ff_main_0_hsdivout6_clk",
73 "board_0_cp_gemac_cpts0_rft_clk_out",
74 NULL,
75 "board_0_mcu_ext_refclk0_out",
76 "board_0_ext_refclk1_out",
77 "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk",
78 "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
79};
80
81static const char * const main_ospi_ref_clk_sel_out0_parents[] = {
82 "hsdiv4_16fft_main_0_hsdivout1_clk",
83 "postdiv1_16fft_main_1_hsdivout5_clk",
84};
85
86static const char * const main_timerclkn_sel_out0_parents[] = {
87 "gluelogic_hfosc0_clkout",
88 "clk_32k_rc_sel_out0",
89 "postdiv4_16ff_main_0_hsdivout7_clk",
90 "gluelogic_rcosc_clkout",
91 "board_0_mcu_ext_refclk0_out",
92 "board_0_ext_refclk1_out",
93 NULL,
94 "board_0_cp_gemac_cpts0_rft_clk_out",
95 "hsdiv4_16fft_main_1_hsdivout3_clk",
96 "postdiv4_16ff_main_2_hsdivout6_clk",
97 NULL,
98 NULL,
99 NULL,
100 NULL,
101 NULL,
102 NULL,
103};
104
105static const char * const wkup_clkout_sel_out0_parents[] = {
106 NULL,
107 "gluelogic_lfosc0_clkout",
108 "hsdiv4_16fft_main_0_hsdivout2_clk",
109 "hsdiv4_16fft_main_1_hsdivout2_clk",
110 "postdiv4_16ff_main_2_hsdivout9_clk",
111 "clk_32k_rc_sel_out0",
112 "gluelogic_rcosc_clkout",
113 "gluelogic_hfosc0_clkout",
114};
115
116static const char * const wkup_clkout_sel_io_out0_parents[] = {
117 "wkup_clkout_sel_out0",
118 "gluelogic_hfosc0_clkout",
119};
120
121static const char * const wkup_clksel_out0_parents[] = {
122 "hsdiv3_16fft_main_15_hsdivout0_clk",
123 "hsdiv4_16fft_mcu_0_hsdivout0_clk",
124};
125
126static const char * const main_usart0_fclk_sel_out0_parents[] = {
127 "usart_programmable_clock_divider_out0",
128 "hsdiv4_16fft_main_1_hsdivout1_clk",
129};
130
131static const struct clk_data clk_list[] = {
132 CLK_FIXED_RATE("osc_26_mhz", 26000000, 0),
133 CLK_FIXED_RATE("osc_25_mhz", 25000000, 0),
134 CLK_FIXED_RATE("osc_24_mhz", 24000000, 0),
135 CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0),
136 CLK_FIXED_RATE("gluelogic_rcosc_clkout", 12500000, 0),
137 CLK_FIXED_RATE("gluelogic_rcosc_clk_1p0v_97p65k", 97656, 0),
138 CLK_FIXED_RATE("board_0_cp_gemac_cpts0_rft_clk_out", 0, 0),
139 CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0),
140 CLK_FIXED_RATE("board_0_i2c0_scl_out", 0, 0),
141 CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0),
142 CLK_FIXED_RATE("board_0_mmc1_clklb_out", 0, 0),
143 CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0),
144 CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0),
145 CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0),
146 CLK_FIXED_RATE("board_0_tck_out", 0, 0),
147 CLK_FIXED_RATE("dmtimer_dmc1ms_main_0_timer_pwm", 0, 0),
148 CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
149 CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0),
150 CLK_FIXED_RATE("mshsi2c_main_0_porscl", 0, 0),
151 CLK_PLL("pllfracf2_ssmod_16fft_main_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x680000, 0),
152 CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
153 CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
154 CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_main_1_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x681000, 0, 1920000000),
155 CLK_DIV("pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
156 CLK_DIV("pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
157 CLK_PLL("pllfracf2_ssmod_16fft_main_12_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68c000, 0),
158 CLK_PLL("pllfracf2_ssmod_16fft_main_15_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68f000, 0),
159 CLK_PLL("pllfracf2_ssmod_16fft_main_2_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x682000, 0),
160 CLK_DIV("pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
161 CLK_DIV("pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", 0x682038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
162 CLK_PLL("pllfracf2_ssmod_16fft_main_8_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x688000, 0),
163 CLK_PLL("pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x4040000, 0),
164 CLK_DIV("postdiv1_16fft_main_1_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0),
165 CLK_DIV("postdiv4_16ff_main_0_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x680094, 0, 7, 0, 0),
166 CLK_DIV("postdiv4_16ff_main_0_hsdivout6_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0, 0),
167 CLK_DIV("postdiv4_16ff_main_0_hsdivout7_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x68009c, 0, 7, 0, 0),
168 CLK_DIV("postdiv4_16ff_main_0_hsdivout8_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x6800a0, 0, 7, 0, 0),
169 CLK_DIV("postdiv4_16ff_main_2_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", 0x682094, 0, 7, 0, 0),
170 CLK_DIV("postdiv4_16ff_main_2_hsdivout6_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", 0x682098, 0, 7, 0, 0),
171 CLK_DIV("postdiv4_16ff_main_2_hsdivout8_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a0, 0, 7, 0, 0),
172 CLK_DIV("postdiv4_16ff_main_2_hsdivout9_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a4, 0, 7, 0, 0),
173 CLK_MUX("clk_32k_rc_sel_out0", clk_32k_rc_sel_out0_parents, 4, 0x4508058, 0, 2, 0),
174 CLK_MUX("main_emmcsd1_io_clklb_sel_out0", main_emmcsd1_io_clklb_sel_out0_parents, 2, 0x108168, 16, 1, 0),
175 CLK_MUX("main_ospi_loopback_clk_sel_out0", main_ospi_loopback_clk_sel_out0_parents, 2, 0x108500, 4, 1, 0),
176 CLK_MUX("main_usb0_refclk_sel_out0", main_usb0_refclk_sel_out0_parents, 2, 0x43008190, 0, 1, 0),
177 CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0),
178 CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0),
179 CLK_DIV("hsdiv3_16fft_main_15_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_15_foutvcop_clk", 0x68f080, 0, 7, 0, 0),
180 CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0),
181 CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0, 0),
182 CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0),
183 CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0, 0),
184 CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0, 0),
185 CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000),
186 CLK_DIV("hsdiv4_16fft_main_1_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681084, 0, 7, 0, 0),
187 CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0),
188 CLK_DIV("hsdiv4_16fft_main_1_hsdivout3_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x68108c, 0, 7, 0, 0),
189 CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0),
190 CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0),
191 CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040080, 0, 7, 0, 0),
192 CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_main_0_sysclkout_clk", sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0),
193 CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0),
194 CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0),
195 CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0),
196 CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0),
197 CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0),
198 CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0),
199 CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0),
200 CLK_MUX("main_ospi_ref_clk_sel_out0", main_ospi_ref_clk_sel_out0_parents, 2, 0x108500, 0, 1, 0),
201 CLK_MUX("main_timerclkn_sel_out0", main_timerclkn_sel_out0_parents, 16, 0x1081b0, 0, 4, 0),
202 CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x108240, 0, 2, 0, 0, 48000000),
203 CLK_MUX("wkup_clkout_sel_out0", wkup_clkout_sel_out0_parents, 8, 0x43008020, 0, 3, 0),
204 CLK_MUX("wkup_clkout_sel_io_out0", wkup_clkout_sel_io_out0_parents, 2, 0x43008020, 24, 1, 0),
205 CLK_MUX("wkup_clksel_out0", wkup_clksel_out0_parents, 2, 0x43008010, 0, 1, 0),
206 CLK_MUX("main_usart0_fclk_sel_out0", main_usart0_fclk_sel_out0_parents, 2, 0x108280, 0, 1, 0),
207 CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0),
208 CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x402011c, 0, 5, 0, 0),
209};
210
211static const struct dev_clk soc_dev_clk_data[] = {
212 DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"),
213 DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"),
214 DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
215 DEV_CLK(16, 3, "hsdiv4_16fft_main_0_hsdivout4_clk"),
216 DEV_CLK(16, 4, "gluelogic_hfosc0_clkout"),
217 DEV_CLK(16, 5, "board_0_ext_refclk1_out"),
218 DEV_CLK(16, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
219 DEV_CLK(16, 7, "postdiv4_16ff_main_2_hsdivout8_clk"),
220 DEV_CLK(16, 8, "gluelogic_hfosc0_clkout"),
221 DEV_CLK(16, 9, "board_0_ext_refclk1_out"),
222 DEV_CLK(16, 10, "gluelogic_rcosc_clkout"),
223 DEV_CLK(16, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
224 DEV_CLK(16, 12, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
225 DEV_CLK(36, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
226 DEV_CLK(36, 2, "main_timerclkn_sel_out0"),
227 DEV_CLK(36, 3, "gluelogic_hfosc0_clkout"),
228 DEV_CLK(36, 4, "clk_32k_rc_sel_out0"),
229 DEV_CLK(36, 5, "postdiv4_16ff_main_0_hsdivout7_clk"),
230 DEV_CLK(36, 6, "gluelogic_rcosc_clkout"),
231 DEV_CLK(36, 7, "board_0_mcu_ext_refclk0_out"),
232 DEV_CLK(36, 8, "board_0_ext_refclk1_out"),
233 DEV_CLK(36, 10, "board_0_cp_gemac_cpts0_rft_clk_out"),
234 DEV_CLK(36, 11, "hsdiv4_16fft_main_1_hsdivout3_clk"),
235 DEV_CLK(36, 12, "postdiv4_16ff_main_2_hsdivout6_clk"),
236 DEV_CLK(57, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
237 DEV_CLK(57, 2, "main_emmcsd0_refclk_sel_out0"),
238 DEV_CLK(57, 3, "postdiv4_16ff_main_0_hsdivout5_clk"),
239 DEV_CLK(57, 4, "hsdiv4_16fft_main_2_hsdivout2_clk"),
240 DEV_CLK(58, 0, "main_emmcsd1_io_clklb_sel_out0"),
241 DEV_CLK(58, 1, "board_0_mmc1_clklb_out"),
242 DEV_CLK(58, 2, "board_0_mmc1_clk_out"),
243 DEV_CLK(58, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
244 DEV_CLK(58, 6, "main_emmcsd1_refclk_sel_out0"),
245 DEV_CLK(58, 7, "postdiv4_16ff_main_0_hsdivout5_clk"),
246 DEV_CLK(58, 8, "hsdiv4_16fft_main_2_hsdivout2_clk"),
247 DEV_CLK(61, 0, "main_gtcclk_sel_out0"),
248 DEV_CLK(61, 1, "postdiv4_16ff_main_2_hsdivout5_clk"),
249 DEV_CLK(61, 2, "postdiv4_16ff_main_0_hsdivout6_clk"),
250 DEV_CLK(61, 3, "board_0_cp_gemac_cpts0_rft_clk_out"),
251 DEV_CLK(61, 5, "board_0_mcu_ext_refclk0_out"),
252 DEV_CLK(61, 6, "board_0_ext_refclk1_out"),
253 DEV_CLK(61, 7, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
254 DEV_CLK(61, 8, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
255 DEV_CLK(61, 9, "wkup_clksel_out0"),
256 DEV_CLK(61, 10, "hsdiv3_16fft_main_15_hsdivout0_clk"),
257 DEV_CLK(61, 11, "hsdiv4_16fft_mcu_0_hsdivout0_clk"),
258 DEV_CLK(75, 0, "board_0_ospi0_dqs_out"),
259 DEV_CLK(75, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
260 DEV_CLK(75, 2, "main_ospi_loopback_clk_sel_out0"),
261 DEV_CLK(75, 3, "board_0_ospi0_dqs_out"),
262 DEV_CLK(75, 4, "board_0_ospi0_lbclko_out"),
263 DEV_CLK(75, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
264 DEV_CLK(75, 7, "main_ospi_ref_clk_sel_out0"),
265 DEV_CLK(75, 8, "hsdiv4_16fft_main_0_hsdivout1_clk"),
266 DEV_CLK(75, 9, "postdiv1_16fft_main_1_hsdivout5_clk"),
267 DEV_CLK(77, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
268 DEV_CLK(102, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
269 DEV_CLK(102, 1, "board_0_i2c0_scl_out"),
270 DEV_CLK(102, 2, "hsdiv4_16fft_main_1_hsdivout0_clk"),
271 DEV_CLK(135, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
272 DEV_CLK(146, 0, "main_usart0_fclk_sel_out0"),
273 DEV_CLK(146, 1, "usart_programmable_clock_divider_out0"),
274 DEV_CLK(146, 2, "hsdiv4_16fft_main_1_hsdivout1_clk"),
275 DEV_CLK(146, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
276 DEV_CLK(157, 54, "clkout0_ctrl_out0"),
277 DEV_CLK(157, 55, "hsdiv4_16fft_main_2_hsdivout1_clk"),
278 DEV_CLK(157, 56, "hsdiv4_16fft_main_2_hsdivout1_clk"),
279 DEV_CLK(157, 62, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
280 DEV_CLK(157, 74, "mshsi2c_main_0_porscl"),
281 DEV_CLK(157, 135, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"),
282 DEV_CLK(157, 143, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
283 DEV_CLK(157, 145, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
284 DEV_CLK(157, 157, "fss_ul_main_0_ospi_0_ospi_oclk_clk"),
285 DEV_CLK(157, 159, "fss_ul_main_0_ospi_0_ospi_oclk_clk"),
286 DEV_CLK(157, 173, "sam62_pll_ctrl_wrap_main_0_sysclkout_clk"),
287 DEV_CLK(157, 174, "wkup_clkout_sel_io_out0"),
288 DEV_CLK(157, 175, "wkup_clkout_sel_out0"),
289 DEV_CLK(157, 176, "gluelogic_hfosc0_clkout"),
290 DEV_CLK(157, 178, "dmtimer_dmc1ms_main_0_timer_pwm"),
291 DEV_CLK(161, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
292 DEV_CLK(161, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
293 DEV_CLK(161, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
294 DEV_CLK(161, 3, "main_usb0_refclk_sel_out0"),
295 DEV_CLK(161, 4, "gluelogic_hfosc0_clkout"),
296 DEV_CLK(161, 5, "postdiv4_16ff_main_0_hsdivout8_clk"),
297 DEV_CLK(161, 10, "board_0_tck_out"),
298 DEV_CLK(166, 3, "hsdiv0_16fft_main_8_hsdivout0_clk"),
299 DEV_CLK(166, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
300 DEV_CLK(169, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
301 DEV_CLK(169, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
302 DEV_CLK(170, 1, "hsdiv0_16fft_main_12_hsdivout0_clk"),
303 DEV_CLK(170, 2, "board_0_tck_out"),
304 DEV_CLK(170, 3, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
305};
306
307const struct ti_k3_clk_platdata j722s_clk_platdata = {
308 .clk_list = clk_list,
309 .clk_list_cnt = ARRAY_SIZE(clk_list),
310 .soc_dev_clk_data = soc_dev_clk_data,
311 .soc_dev_clk_data_cnt = ARRAY_SIZE(soc_dev_clk_data),
312};