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git01.mediatek.com / filogic / uboot / c3169bd028fa44ae793b02c211f98a55957758ca / . / arch / arm / dts / stm32mp15xx-dhcor-u-boot.dtsi
blob: 5de7b87b9a1b30c6362322a27b6ad8915ef173db [file] [log] [blame]
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2/*
3 * Copyright : STMicroelectronics 2018
4 *
5 * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
6 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Marek Vasut526c9512020-03-31 19:51:36 +0200[diff] [blame]7 * Copyright (C) 2020 Marek Vasut <marex@denx.de>
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]8 */
9
10#include <dt-bindings/clock/stm32mp1-clksrc.h>
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]11#include "stm32mp15-u-boot.dtsi"
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]12#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
13
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]14&i2c4 {
15 u-boot,dm-pre-reloc;
16};
17
18&i2c4_pins_a {
19 u-boot,dm-pre-reloc;
20 pins {
21 u-boot,dm-pre-reloc;
22 };
23};
24
25&pmic {
26 u-boot,dm-pre-reloc;
27};
28
Marek Vasut526c9512020-03-31 19:51:36 +0200[diff] [blame]29&qspi {
30 u-boot,dm-spl;
31};
32
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]33&rcc {
34 st,clksrc = <
35 CLK_MPU_PLL1P
36 CLK_AXI_PLL2P
37 CLK_MCU_PLL3P
38 CLK_PLL12_HSE
39 CLK_PLL3_HSE
40 CLK_PLL4_HSE
41 CLK_RTC_LSE
42 CLK_MCO1_DISABLED
43 CLK_MCO2_DISABLED
44 >;
45
46 st,clkdiv = <
47 1 /*MPU*/
48 0 /*AXI*/
49 0 /*MCU*/
50 1 /*APB1*/
51 1 /*APB2*/
52 1 /*APB3*/
53 1 /*APB4*/
54 2 /*APB5*/
55 23 /*RTC*/
56 0 /*MCO1*/
57 0 /*MCO2*/
58 >;
59
60 st,pkcs = <
61 CLK_CKPER_HSE
62 CLK_FMC_ACLK
63 CLK_QSPI_ACLK
64 CLK_ETH_DISABLED
65 CLK_SDMMC12_PLL4P
66 CLK_DSI_DSIPLL
67 CLK_STGEN_HSE
68 CLK_USBPHY_HSE
69 CLK_SPI2S1_PLL3Q
70 CLK_SPI2S23_PLL3Q
71 CLK_SPI45_HSI
72 CLK_SPI6_HSI
73 CLK_I2C46_HSI
74 CLK_SDMMC3_PLL4P
75 CLK_USBO_USBPHY
76 CLK_ADC_CKPER
77 CLK_CEC_LSE
78 CLK_I2C12_HSI
79 CLK_I2C35_HSI
80 CLK_UART1_HSI
81 CLK_UART24_HSI
82 CLK_UART35_HSI
83 CLK_UART6_HSI
84 CLK_UART78_HSI
85 CLK_SPDIF_PLL4P
Antonio Borneo84159e82020-01-28 10:11:01 +0100[diff] [blame]86 CLK_FDCAN_PLL4R
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]87 CLK_SAI1_PLL3Q
88 CLK_SAI2_PLL3Q
89 CLK_SAI3_PLL3Q
90 CLK_SAI4_PLL3Q
91 CLK_RNG1_LSI
92 CLK_RNG2_LSI
93 CLK_LPTIM1_PCLK1
94 CLK_LPTIM23_PCLK3
95 CLK_LPTIM45_LSE
96 >;
97
98 /* VCO = 1300.0 MHz => P = 650 (CPU) */
99 pll1: st,pll@0 {
Patrick Delaunayc22caac2020-01-28 10:11:03 +0100[diff] [blame]100 compatible = "st,stm32mp1-pll";
101 reg = <0>;
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]102 cfg = < 2 80 0 0 0 PQR(1,0,0) >;
103 frac = < 0x800 >;
104 u-boot,dm-pre-reloc;
105 };
106
107 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
108 pll2: st,pll@1 {
Patrick Delaunayc22caac2020-01-28 10:11:03 +0100[diff] [blame]109 compatible = "st,stm32mp1-pll";
110 reg = <1>;
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]111 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
112 frac = < 0x1400 >;
113 u-boot,dm-pre-reloc;
114 };
115
116 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
117 pll3: st,pll@2 {
Patrick Delaunayc22caac2020-01-28 10:11:03 +0100[diff] [blame]118 compatible = "st,stm32mp1-pll";
119 reg = <2>;
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]120 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
121 frac = < 0x1a04 >;
122 u-boot,dm-pre-reloc;
123 };
124
Marek Vasut787b17c2020-03-31 19:51:35 +0200[diff] [blame]125 /* VCO = 600.0 MHz => P = 100, Q = 50, R = 100 */
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]126 pll4: st,pll@3 {
Patrick Delaunayc22caac2020-01-28 10:11:03 +0100[diff] [blame]127 compatible = "st,stm32mp1-pll";
128 reg = <3>;
Marek Vasut787b17c2020-03-31 19:51:35 +0200[diff] [blame]129 cfg = < 1 49 5 11 5 PQR(1,1,1) >;
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]130 u-boot,dm-pre-reloc;
131 };
132};