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git01.mediatek.com / filogic / uboot / c30a1a12ad55956e3708586d77dbbe305fabb2d2 / . / arch / mips / mach-octeon / include / mach / cvmx-sli-defs.h
blob: 221ed1bcde810f1f4daf9d62279bb097521c9e5e [file] [log] [blame]
Aaron Williams7394f552020-12-11 17:05:50 +0100[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2020 Marvell International Ltd.
4 *
5 * Configuration and status register (CSR) type definitions for
6 * Octeon sli.
7 */
8
9#ifndef __CVMX_SLI_DEFS_H__
10#define __CVMX_SLI_DEFS_H__
11
12#define CVMX_SLI_BIST_STATUS CVMX_SLI_BIST_STATUS_FUNC()
13static inline u64 CVMX_SLI_BIST_STATUS_FUNC(void)
14{
15 switch (cvmx_get_octeon_family()) {
16 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
17 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
18 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
19 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
20 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
21 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
22 return 0x0000000000000580ull;
23 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
24 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
25 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
26 return 0x0000000000000580ull;
27 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
28 return 0x0000000000028580ull;
29 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
30 return 0x0000000000028580ull;
31 }
32 return 0x0000000000028580ull;
33}
34
35#define CVMX_SLI_CIU_INT_ENB (0x00011F0000027110ull)
36#define CVMX_SLI_CIU_INT_SUM (0x00011F0000027100ull)
37static inline u64 CVMX_SLI_CTL_PORTX(unsigned long offset)
38{
39 switch (cvmx_get_octeon_family()) {
40 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
41 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
42 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
43 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
44 return 0x0000000000000050ull + (offset) * 16;
45 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
46 return 0x0000000000010050ull + (offset) * 16;
47 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
48 return 0x0000000000000050ull + (offset) * 16;
49
50 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
51 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
52 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
53 return 0x00000000000006E0ull + (offset) * 16;
54 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
55 return 0x00000000000286E0ull + (offset) * 16;
56 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
57 return 0x00000000000286E0ull + (offset) * 16;
58 }
59 return 0x00000000000286E0ull + (offset) * 16;
60}
61
62#define CVMX_SLI_CTL_STATUS CVMX_SLI_CTL_STATUS_FUNC()
63static inline u64 CVMX_SLI_CTL_STATUS_FUNC(void)
64{
65 switch (cvmx_get_octeon_family()) {
66 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
67 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
68 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
69 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
70 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
71 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
72 return 0x0000000000000570ull;
73 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
74 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
75 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
76 return 0x0000000000000570ull;
77 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
78 return 0x0000000000028570ull;
79 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
80 return 0x0000000000028570ull;
81 }
82 return 0x0000000000028570ull;
83}
84
85#define CVMX_SLI_DATA_OUT_CNT CVMX_SLI_DATA_OUT_CNT_FUNC()
86static inline u64 CVMX_SLI_DATA_OUT_CNT_FUNC(void)
87{
88 switch (cvmx_get_octeon_family()) {
89 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
90 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
91 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
92 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
93 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
94 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
95 return 0x00000000000005F0ull;
96 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
97 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
98 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
99 return 0x00000000000005F0ull;
100 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
101 return 0x00000000000285F0ull;
102 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
103 return 0x00000000000285F0ull;
104 }
105 return 0x00000000000285F0ull;
106}
107
108#define CVMX_SLI_DBG_DATA (0x0000000000000310ull)
109#define CVMX_SLI_DBG_SELECT (0x0000000000000300ull)
110static inline u64 CVMX_SLI_DMAX_CNT(unsigned long offset)
111{
112 switch (cvmx_get_octeon_family()) {
113 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
114 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
115 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
116 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
117 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
118 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
119 return 0x0000000000000400ull + (offset) * 16;
120 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
121 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
122 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
123 return 0x0000000000000400ull + (offset) * 16;
124 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
125 return 0x0000000000028400ull + (offset) * 16;
126 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
127 return 0x0000000000028400ull + (offset) * 16;
128 }
129 return 0x0000000000028400ull + (offset) * 16;
130}
131
132static inline u64 CVMX_SLI_DMAX_INT_LEVEL(unsigned long offset)
133{
134 switch (cvmx_get_octeon_family()) {
135 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
136 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
137 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
138 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
139 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
140 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
141 return 0x00000000000003E0ull + (offset) * 16;
142 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
143 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
144 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
145 return 0x00000000000003E0ull + (offset) * 16;
146 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
147 return 0x00000000000283E0ull + (offset) * 16;
148 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
149 return 0x00000000000283E0ull + (offset) * 16;
150 }
151 return 0x00000000000283E0ull + (offset) * 16;
152}
153
154static inline u64 CVMX_SLI_DMAX_TIM(unsigned long offset)
155{
156 switch (cvmx_get_octeon_family()) {
157 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
158 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
159 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
160 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
161 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
162 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
163 return 0x0000000000000420ull + (offset) * 16;
164 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
165 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
166 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
167 return 0x0000000000000420ull + (offset) * 16;
168 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
169 return 0x0000000000028420ull + (offset) * 16;
170 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
171 return 0x0000000000028420ull + (offset) * 16;
172 }
173 return 0x0000000000028420ull + (offset) * 16;
174}
175
176#define CVMX_SLI_INT_ENB_CIU (0x0000000000003CD0ull)
177#define CVMX_SLI_INT_ENB_PORTX(offset) (0x0000000000000340ull + ((offset) & 3) * 16)
178#define CVMX_SLI_INT_SUM (0x0000000000000330ull)
179#define CVMX_SLI_LAST_WIN_RDATA0 (0x0000000000000600ull)
180#define CVMX_SLI_LAST_WIN_RDATA1 (0x0000000000000610ull)
181#define CVMX_SLI_LAST_WIN_RDATA2 (0x00000000000006C0ull)
182#define CVMX_SLI_LAST_WIN_RDATA3 (0x00000000000006D0ull)
183#define CVMX_SLI_MACX_PFX_DMA_VF_INT(offset, block_id) \
184 (0x0000000000027280ull + (((offset) & 1) + ((block_id) & 3) * 0x2ull) * 16)
185#define CVMX_SLI_MACX_PFX_DMA_VF_INT_ENB(offset, block_id) \
186 (0x0000000000027500ull + (((offset) & 1) + ((block_id) & 3) * 0x2ull) * 16)
187#define CVMX_SLI_MACX_PFX_FLR_VF_INT(offset, block_id) \
188 (0x0000000000027400ull + (((offset) & 1) + ((block_id) & 3) * 0x2ull) * 16)
189#define CVMX_SLI_MACX_PFX_INT_ENB(offset, block_id) \
190 (0x0000000000027080ull + (((offset) & 1) + ((block_id) & 3) * 0x2ull) * 16)
191#define CVMX_SLI_MACX_PFX_INT_SUM(offset, block_id) \
192 (0x0000000000027000ull + (((offset) & 1) + ((block_id) & 3) * 0x2ull) * 16)
193#define CVMX_SLI_MACX_PFX_MBOX_INT(offset, block_id) \
194 (0x0000000000027380ull + (((offset) & 1) + ((block_id) & 3) * 0x2ull) * 16)
195#define CVMX_SLI_MACX_PFX_PKT_VF_INT(offset, block_id) \
196 (0x0000000000027300ull + (((offset) & 1) + ((block_id) & 3) * 0x2ull) * 16)
197#define CVMX_SLI_MACX_PFX_PKT_VF_INT_ENB(offset, block_id) \
198 (0x0000000000027580ull + (((offset) & 1) + ((block_id) & 3) * 0x2ull) * 16)
199#define CVMX_SLI_MACX_PFX_PP_VF_INT(offset, block_id) \
200 (0x0000000000027200ull + (((offset) & 1) + ((block_id) & 3) * 0x2ull) * 16)
201#define CVMX_SLI_MACX_PFX_PP_VF_INT_ENB(offset, block_id) \
202 (0x0000000000027480ull + (((offset) & 1) + ((block_id) & 3) * 0x2ull) * 16)
203#define CVMX_SLI_MAC_CREDIT_CNT CVMX_SLI_MAC_CREDIT_CNT_FUNC()
204static inline u64 CVMX_SLI_MAC_CREDIT_CNT_FUNC(void)
205{
206 switch (cvmx_get_octeon_family()) {
207 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
208 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
209 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
210 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
211 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
212 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
213 return 0x0000000000003D70ull;
214 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
215 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
216 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
217 return 0x0000000000003D70ull;
218 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
219 return 0x0000000000023D70ull;
220 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
221 return 0x0000000000023D70ull;
222 }
223 return 0x0000000000023D70ull;
224}
225
226#define CVMX_SLI_MAC_CREDIT_CNT2 CVMX_SLI_MAC_CREDIT_CNT2_FUNC()
227static inline u64 CVMX_SLI_MAC_CREDIT_CNT2_FUNC(void)
228{
229 switch (cvmx_get_octeon_family()) {
230 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
231 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
232 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
233 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
234 return 0x0000000000013E10ull;
235 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
236 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
237 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
238 return 0x0000000000003E10ull;
239 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
240 return 0x0000000000023E10ull;
241 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
242 return 0x0000000000023E10ull;
243 }
244 return 0x0000000000023E10ull;
245}
246
247#define CVMX_SLI_MAC_NUMBER CVMX_SLI_MAC_NUMBER_FUNC()
248static inline u64 CVMX_SLI_MAC_NUMBER_FUNC(void)
249{
250 switch (cvmx_get_octeon_family()) {
251 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
252 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
253 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
254 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
255 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
256 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
257 return 0x0000000000003E00ull;
258 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
259 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
260 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
261 return 0x0000000000003E00ull;
262 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
263 return 0x0000000000020050ull;
264 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
265 return 0x0000000000020050ull;
266 }
267 return 0x0000000000020050ull;
268}
269
270#define CVMX_SLI_MEM_ACCESS_CTL CVMX_SLI_MEM_ACCESS_CTL_FUNC()
271static inline u64 CVMX_SLI_MEM_ACCESS_CTL_FUNC(void)
272{
273 switch (cvmx_get_octeon_family()) {
274 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
275 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
276 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
277 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
278 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
279 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
280 return 0x00000000000002F0ull;
281 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
282 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
283 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
284 return 0x00000000000002F0ull;
285 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
286 return 0x00000000000282F0ull;
287 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
288 return 0x00000000000282F0ull;
289 }
290 return 0x00000000000282F0ull;
291}
292
293static inline u64 CVMX_SLI_MEM_ACCESS_SUBIDX(unsigned long offset)
294{
295 switch (cvmx_get_octeon_family()) {
296 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
297 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
298 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
299 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
300 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
301 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
302 return 0x00000000000000E0ull + (offset) * 16 - 16 * 12;
303 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
304 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
305 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
306 return 0x00000000000000E0ull + (offset) * 16 - 16 * 12;
307 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
308 return 0x00000000000280E0ull + (offset) * 16 - 16 * 12;
309 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
310 return 0x00000000000280E0ull + (offset) * 16 - 16 * 12;
311 }
312 return 0x00000000000280E0ull + (offset) * 16 - 16 * 12;
313}
314
315#define CVMX_SLI_MEM_CTL CVMX_SLI_MEM_CTL_FUNC()
316static inline u64 CVMX_SLI_MEM_CTL_FUNC(void)
317{
318 switch (cvmx_get_octeon_family()) {
319 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
320 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
321 return 0x00000000000005E0ull;
322 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
323 return 0x00000000000285E0ull;
324 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
325 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
326 return 0x00000000000285E0ull;
327 }
328 return 0x00000000000285E0ull;
329}
330
331#define CVMX_SLI_MEM_INT_SUM CVMX_SLI_MEM_INT_SUM_FUNC()
332static inline u64 CVMX_SLI_MEM_INT_SUM_FUNC(void)
333{
334 switch (cvmx_get_octeon_family()) {
335 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
336 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
337 return 0x00000000000005D0ull;
338 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
339 return 0x00000000000285D0ull;
340 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
341 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
342 return 0x00000000000285D0ull;
343 }
344 return 0x00000000000285D0ull;
345}
346
347static inline u64 CVMX_SLI_MSIXX_TABLE_ADDR(unsigned long offset)
348{
349 switch (cvmx_get_octeon_family()) {
350 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
351 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
352 return 0x0000000000006000ull + (offset) * 16;
353 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
354 return 0x0000000000000000ull + (offset) * 16;
355 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
356 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
357 return 0x0000000000000000ull + (offset) * 16;
358 }
359 return 0x0000000000000000ull + (offset) * 16;
360}
361
362static inline u64 CVMX_SLI_MSIXX_TABLE_DATA(unsigned long offset)
363{
364 switch (cvmx_get_octeon_family()) {
365 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
366 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
367 return 0x0000000000006008ull + (offset) * 16;
368 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
369 return 0x0000000000000008ull + (offset) * 16;
370 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
371 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
372 return 0x0000000000000008ull + (offset) * 16;
373 }
374 return 0x0000000000000008ull + (offset) * 16;
375}
376
377#define CVMX_SLI_MSIX_MACX_PF_TABLE_ADDR(offset) (0x0000000000007C00ull + ((offset) & 3) * 16)
378#define CVMX_SLI_MSIX_MACX_PF_TABLE_DATA(offset) (0x0000000000007C08ull + ((offset) & 3) * 16)
379#define CVMX_SLI_MSIX_PBA0 CVMX_SLI_MSIX_PBA0_FUNC()
380static inline u64 CVMX_SLI_MSIX_PBA0_FUNC(void)
381{
382 switch (cvmx_get_octeon_family()) {
383 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
384 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
385 return 0x0000000000007000ull;
386 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
387 return 0x0000000000001000ull;
388 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
389 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
390 return 0x0000000000001000ull;
391 }
392 return 0x0000000000001000ull;
393}
394
395#define CVMX_SLI_MSIX_PBA1 CVMX_SLI_MSIX_PBA1_FUNC()
396static inline u64 CVMX_SLI_MSIX_PBA1_FUNC(void)
397{
398 switch (cvmx_get_octeon_family()) {
399 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
400 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
401 return 0x0000000000007010ull;
402 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
403 return 0x0000000000001008ull;
404 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
405 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
406 return 0x0000000000001008ull;
407 }
408 return 0x0000000000001008ull;
409}
410
411#define CVMX_SLI_MSI_ENB0 (0x0000000000003C50ull)
412#define CVMX_SLI_MSI_ENB1 (0x0000000000003C60ull)
413#define CVMX_SLI_MSI_ENB2 (0x0000000000003C70ull)
414#define CVMX_SLI_MSI_ENB3 (0x0000000000003C80ull)
415#define CVMX_SLI_MSI_RCV0 CVMX_SLI_MSI_RCV0_FUNC()
416static inline u64 CVMX_SLI_MSI_RCV0_FUNC(void)
417{
418 switch (cvmx_get_octeon_family()) {
419 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
420 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
421 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
422 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
423 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
424 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
425 return 0x0000000000003C10ull;
426 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
427 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
428 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
429 return 0x0000000000003C10ull;
430 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
431 return 0x0000000000023C10ull;
432 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
433 return 0x0000000000023C10ull;
434 }
435 return 0x0000000000023C10ull;
436}
437
438#define CVMX_SLI_MSI_RCV1 CVMX_SLI_MSI_RCV1_FUNC()
439static inline u64 CVMX_SLI_MSI_RCV1_FUNC(void)
440{
441 switch (cvmx_get_octeon_family()) {
442 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
443 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
444 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
445 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
446 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
447 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
448 return 0x0000000000003C20ull;
449 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
450 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
451 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
452 return 0x0000000000003C20ull;
453 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
454 return 0x0000000000023C20ull;
455 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
456 return 0x0000000000023C20ull;
457 }
458 return 0x0000000000023C20ull;
459}
460
461#define CVMX_SLI_MSI_RCV2 CVMX_SLI_MSI_RCV2_FUNC()
462static inline u64 CVMX_SLI_MSI_RCV2_FUNC(void)
463{
464 switch (cvmx_get_octeon_family()) {
465 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
466 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
467 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
468 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
469 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
470 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
471 return 0x0000000000003C30ull;
472 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
473 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
474 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
475 return 0x0000000000003C30ull;
476 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
477 return 0x0000000000023C30ull;
478 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
479 return 0x0000000000023C30ull;
480 }
481 return 0x0000000000023C30ull;
482}
483
484#define CVMX_SLI_MSI_RCV3 CVMX_SLI_MSI_RCV3_FUNC()
485static inline u64 CVMX_SLI_MSI_RCV3_FUNC(void)
486{
487 switch (cvmx_get_octeon_family()) {
488 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
489 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
490 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
491 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
492 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
493 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
494 return 0x0000000000003C40ull;
495 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
496 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
497 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
498 return 0x0000000000003C40ull;
499 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
500 return 0x0000000000023C40ull;
501 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
502 return 0x0000000000023C40ull;
503 }
504 return 0x0000000000023C40ull;
505}
506
507#define CVMX_SLI_MSI_RD_MAP CVMX_SLI_MSI_RD_MAP_FUNC()
508static inline u64 CVMX_SLI_MSI_RD_MAP_FUNC(void)
509{
510 switch (cvmx_get_octeon_family()) {
511 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
512 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
513 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
514 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
515 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
516 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
517 return 0x0000000000003CA0ull;
518 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
519 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
520 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
521 return 0x0000000000003CA0ull;
522 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
523 return 0x0000000000023CA0ull;
524 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
525 return 0x0000000000023CA0ull;
526 }
527 return 0x0000000000023CA0ull;
528}
529
530#define CVMX_SLI_MSI_W1C_ENB0 (0x0000000000003CF0ull)
531#define CVMX_SLI_MSI_W1C_ENB1 (0x0000000000003D00ull)
532#define CVMX_SLI_MSI_W1C_ENB2 (0x0000000000003D10ull)
533#define CVMX_SLI_MSI_W1C_ENB3 (0x0000000000003D20ull)
534#define CVMX_SLI_MSI_W1S_ENB0 (0x0000000000003D30ull)
535#define CVMX_SLI_MSI_W1S_ENB1 (0x0000000000003D40ull)
536#define CVMX_SLI_MSI_W1S_ENB2 (0x0000000000003D50ull)
537#define CVMX_SLI_MSI_W1S_ENB3 (0x0000000000003D60ull)
538#define CVMX_SLI_MSI_WR_MAP CVMX_SLI_MSI_WR_MAP_FUNC()
539static inline u64 CVMX_SLI_MSI_WR_MAP_FUNC(void)
540{
541 switch (cvmx_get_octeon_family()) {
542 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
543 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
544 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
545 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
546 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
547 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
548 return 0x0000000000003C90ull;
549 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
550 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
551 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
552 return 0x0000000000003C90ull;
553 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
554 return 0x0000000000023C90ull;
555 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
556 return 0x0000000000023C90ull;
557 }
558 return 0x0000000000023C90ull;
559}
560
561#define CVMX_SLI_NQM_RSP_ERR_SND_DBG (0x00011F0000028800ull)
562#define CVMX_SLI_PCIE_MSI_RCV CVMX_SLI_PCIE_MSI_RCV_FUNC()
563static inline u64 CVMX_SLI_PCIE_MSI_RCV_FUNC(void)
564{
565 switch (cvmx_get_octeon_family()) {
566 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
567 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
568 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
569 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
570 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
571 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
572 return 0x0000000000003CB0ull;
573 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
574 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
575 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
576 return 0x0000000000003CB0ull;
577 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
578 return 0x0000000000023CB0ull;
579 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
580 return 0x0000000000023CB0ull;
581 }
582 return 0x0000000000023CB0ull;
583}
584
585#define CVMX_SLI_PCIE_MSI_RCV_B1 CVMX_SLI_PCIE_MSI_RCV_B1_FUNC()
586static inline u64 CVMX_SLI_PCIE_MSI_RCV_B1_FUNC(void)
587{
588 switch (cvmx_get_octeon_family()) {
589 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
590 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
591 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
592 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
593 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
594 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
595 return 0x0000000000000650ull;
596 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
597 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
598 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
599 return 0x0000000000000650ull;
600 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
601 return 0x0000000000028650ull;
602 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
603 return 0x0000000000028650ull;
604 }
605 return 0x0000000000028650ull;
606}
607
608#define CVMX_SLI_PCIE_MSI_RCV_B2 CVMX_SLI_PCIE_MSI_RCV_B2_FUNC()
609static inline u64 CVMX_SLI_PCIE_MSI_RCV_B2_FUNC(void)
610{
611 switch (cvmx_get_octeon_family()) {
612 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
613 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
614 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
615 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
616 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
617 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
618 return 0x0000000000000660ull;
619 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
620 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
621 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
622 return 0x0000000000000660ull;
623 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
624 return 0x0000000000028660ull;
625 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
626 return 0x0000000000028660ull;
627 }
628 return 0x0000000000028660ull;
629}
630
631#define CVMX_SLI_PCIE_MSI_RCV_B3 CVMX_SLI_PCIE_MSI_RCV_B3_FUNC()
632static inline u64 CVMX_SLI_PCIE_MSI_RCV_B3_FUNC(void)
633{
634 switch (cvmx_get_octeon_family()) {
635 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
636 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
637 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
638 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
639 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
640 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
641 return 0x0000000000000670ull;
642 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
643 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
644 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
645 return 0x0000000000000670ull;
646 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
647 return 0x0000000000028670ull;
648 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
649 return 0x0000000000028670ull;
650 }
651 return 0x0000000000028670ull;
652}
653
654static inline u64 CVMX_SLI_PKTX_CNTS(unsigned long offset)
655{
656 switch (cvmx_get_octeon_family()) {
657 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
658 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
659 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
660 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
661 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
662 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
663 return 0x0000000000002400ull + (offset) * 16;
664
665 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
666 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
667 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
668 return 0x0000000000002400ull + (offset) * 16;
669 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
670 return 0x00000000000100B0ull + (offset) * 0x20000ull;
671 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
672 return 0x00000000000100B0ull + (offset) * 0x20000ull;
673 }
674 return 0x00000000000100B0ull + (offset) * 0x20000ull;
675}
676
677#define CVMX_SLI_PKTX_ERROR_INFO(offset) (0x00000000000100C0ull + ((offset) & 63) * 0x20000ull)
678static inline u64 CVMX_SLI_PKTX_INPUT_CONTROL(unsigned long offset)
679{
680 switch (cvmx_get_octeon_family()) {
681 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
682 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
683 return 0x0000000000004000ull + (offset) * 16;
684 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
685 return 0x0000000000010000ull + (offset) * 0x20000ull;
686 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
687 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
688 return 0x0000000000010000ull + (offset) * 0x20000ull;
689 }
690 return 0x0000000000010000ull + (offset) * 0x20000ull;
691}
692
693static inline u64 CVMX_SLI_PKTX_INSTR_BADDR(unsigned long offset)
694{
695 switch (cvmx_get_octeon_family()) {
696 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
697 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
698 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
699 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
700 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
701 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
702 return 0x0000000000002800ull + (offset) * 16;
703
704 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
705 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
706 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
707 return 0x0000000000002800ull + (offset) * 16;
708 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
709 return 0x0000000000010010ull + (offset) * 0x20000ull;
710 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
711 return 0x0000000000010010ull + (offset) * 0x20000ull;
712 }
713 return 0x0000000000010010ull + (offset) * 0x20000ull;
714}
715
716static inline u64 CVMX_SLI_PKTX_INSTR_BAOFF_DBELL(unsigned long offset)
717{
718 switch (cvmx_get_octeon_family()) {
719 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
720 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
721 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
722 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
723 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
724 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
725 return 0x0000000000002C00ull + (offset) * 16;
726
727 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
728 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
729 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
730 return 0x0000000000002C00ull + (offset) * 16;
731 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
732 return 0x0000000000010020ull + (offset) * 0x20000ull;
733 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
734 return 0x0000000000010020ull + (offset) * 0x20000ull;
735 }
736 return 0x0000000000010020ull + (offset) * 0x20000ull;
737}
738
739static inline u64 CVMX_SLI_PKTX_INSTR_FIFO_RSIZE(unsigned long offset)
740{
741 switch (cvmx_get_octeon_family()) {
742 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
743 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
744 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
745 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
746 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
747 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
748 return 0x0000000000003000ull + (offset) * 16;
749
750 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
751 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
752 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
753 return 0x0000000000003000ull + (offset) * 16;
754 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
755 return 0x0000000000010030ull + (offset) * 0x20000ull;
756 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
757 return 0x0000000000010030ull + (offset) * 0x20000ull;
758 }
759 return 0x0000000000010030ull + (offset) * 0x20000ull;
760}
761
762#define CVMX_SLI_PKTX_INSTR_HEADER(offset) (0x0000000000003400ull + ((offset) & 31) * 16)
763static inline u64 CVMX_SLI_PKTX_INT_LEVELS(unsigned long offset)
764{
765 switch (cvmx_get_octeon_family()) {
766 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
767 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
768 return 0x0000000000004400ull + (offset) * 16;
769 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
770 return 0x00000000000100A0ull + (offset) * 0x20000ull;
771 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
772 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
773 return 0x00000000000100A0ull + (offset) * 0x20000ull;
774 }
775 return 0x00000000000100A0ull + (offset) * 0x20000ull;
776}
777
778#define CVMX_SLI_PKTX_IN_BP(offset) (0x0000000000003800ull + ((offset) & 31) * 16)
779#define CVMX_SLI_PKTX_MBOX_INT(offset) (0x0000000000010210ull + ((offset) & 63) * 0x20000ull)
780static inline u64 CVMX_SLI_PKTX_OUTPUT_CONTROL(unsigned long offset)
781{
782 switch (cvmx_get_octeon_family()) {
783 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
784 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
785 return 0x0000000000004800ull + (offset) * 16;
786 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
787 return 0x0000000000010050ull + (offset) * 0x20000ull;
788 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
789 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
790 return 0x0000000000010050ull + (offset) * 0x20000ull;
791 }
792 return 0x0000000000010050ull + (offset) * 0x20000ull;
793}
794
795static inline u64 CVMX_SLI_PKTX_OUT_SIZE(unsigned long offset)
796{
797 switch (cvmx_get_octeon_family()) {
798 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
799 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
800 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
801 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
802 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
803 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
804 return 0x0000000000000C00ull + (offset) * 16;
805
806 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
807 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
808 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
809 return 0x0000000000000C00ull + (offset) * 16;
810 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
811 return 0x0000000000010060ull + (offset) * 0x20000ull;
812 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
813 return 0x0000000000010060ull + (offset) * 0x20000ull;
814 }
815 return 0x0000000000010060ull + (offset) * 0x20000ull;
816}
817
818#define CVMX_SLI_PKTX_PF_VF_MBOX_SIGX(offset, block_id) \
819 (0x0000000000010200ull + (((offset) & 1) + ((block_id) & 63) * 0x4000ull) * 8)
820static inline u64 CVMX_SLI_PKTX_SLIST_BADDR(unsigned long offset)
821{
822 switch (cvmx_get_octeon_family()) {
823 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
824 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
825 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
826 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
827 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
828 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
829 return 0x0000000000001400ull + (offset) * 16;
830
831 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
832 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
833 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
834 return 0x0000000000001400ull + (offset) * 16;
835 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
836 return 0x0000000000010070ull + (offset) * 0x20000ull;
837 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
838 return 0x0000000000010070ull + (offset) * 0x20000ull;
839 }
840 return 0x0000000000010070ull + (offset) * 0x20000ull;
841}
842
843static inline u64 CVMX_SLI_PKTX_SLIST_BAOFF_DBELL(unsigned long offset)
844{
845 switch (cvmx_get_octeon_family()) {
846 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
847 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
848 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
849 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
850 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
851 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
852 return 0x0000000000001800ull + (offset) * 16;
853
854 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
855 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
856 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
857 return 0x0000000000001800ull + (offset) * 16;
858 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
859 return 0x0000000000010080ull + (offset) * 0x20000ull;
860 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
861 return 0x0000000000010080ull + (offset) * 0x20000ull;
862 }
863 return 0x0000000000010080ull + (offset) * 0x20000ull;
864}
865
866static inline u64 CVMX_SLI_PKTX_SLIST_FIFO_RSIZE(unsigned long offset)
867{
868 switch (cvmx_get_octeon_family()) {
869 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
870 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
871 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
872 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
873 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
874 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
875 return 0x0000000000001C00ull + (offset) * 16;
876
877 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
878 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
879 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
880 return 0x0000000000001C00ull + (offset) * 16;
881 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
882 return 0x0000000000010090ull + (offset) * 0x20000ull;
883 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
884 return 0x0000000000010090ull + (offset) * 0x20000ull;
885 }
886 return 0x0000000000010090ull + (offset) * 0x20000ull;
887}
888
889#define CVMX_SLI_PKTX_VF_INT_SUM(offset) (0x00000000000100D0ull + ((offset) & 63) * 0x20000ull)
890#define CVMX_SLI_PKTX_VF_SIG(offset) (0x0000000000004C00ull + ((offset) & 63) * 16)
891#define CVMX_SLI_PKT_BIST_STATUS (0x0000000000029220ull)
892#define CVMX_SLI_PKT_CNT_INT CVMX_SLI_PKT_CNT_INT_FUNC()
893static inline u64 CVMX_SLI_PKT_CNT_INT_FUNC(void)
894{
895 switch (cvmx_get_octeon_family()) {
896 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
897 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
898 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
899 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
900 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
901 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
902 return 0x0000000000001130ull;
903 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
904 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
905 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
906 return 0x0000000000001130ull;
907 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
908 return 0x0000000000029130ull;
909 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
910 return 0x0000000000029130ull;
911 }
912 return 0x0000000000029130ull;
913}
914
915#define CVMX_SLI_PKT_CNT_INT_ENB (0x0000000000001150ull)
916#define CVMX_SLI_PKT_CTL (0x0000000000001220ull)
917#define CVMX_SLI_PKT_DATA_OUT_ES (0x00000000000010B0ull)
918#define CVMX_SLI_PKT_DATA_OUT_NS (0x00000000000010A0ull)
919#define CVMX_SLI_PKT_DATA_OUT_ROR (0x0000000000001090ull)
920#define CVMX_SLI_PKT_DPADDR (0x0000000000001080ull)
921#define CVMX_SLI_PKT_GBL_CONTROL (0x0000000000029210ull)
922#define CVMX_SLI_PKT_INPUT_CONTROL (0x0000000000001170ull)
923#define CVMX_SLI_PKT_INSTR_ENB (0x0000000000001000ull)
924#define CVMX_SLI_PKT_INSTR_RD_SIZE (0x00000000000011A0ull)
925#define CVMX_SLI_PKT_INSTR_SIZE (0x0000000000001020ull)
926#define CVMX_SLI_PKT_INT CVMX_SLI_PKT_INT_FUNC()
927static inline u64 CVMX_SLI_PKT_INT_FUNC(void)
928{
929 switch (cvmx_get_octeon_family()) {
930 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
931 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
932 return 0x0000000000001160ull;
933 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
934 return 0x0000000000029160ull;
935 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
936 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
937 return 0x0000000000029160ull;
938 }
939 return 0x0000000000029160ull;
940}
941
942#define CVMX_SLI_PKT_INT_LEVELS (0x0000000000001120ull)
943#define CVMX_SLI_PKT_IN_BP (0x0000000000001210ull)
944static inline u64 CVMX_SLI_PKT_IN_DONEX_CNTS(unsigned long offset)
945{
946 switch (cvmx_get_octeon_family()) {
947 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
948 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
949 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
950 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
951 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
952 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
953 return 0x0000000000002000ull + (offset) * 16;
954
955 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
956 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
957 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
958 return 0x0000000000002000ull + (offset) * 16;
959 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
960 return 0x0000000000010040ull + (offset) * 0x20000ull;
961 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
962 return 0x0000000000010040ull + (offset) * 0x20000ull;
963 }
964 return 0x0000000000010040ull + (offset) * 0x20000ull;
965}
966
967#define CVMX_SLI_PKT_IN_INSTR_COUNTS CVMX_SLI_PKT_IN_INSTR_COUNTS_FUNC()
968static inline u64 CVMX_SLI_PKT_IN_INSTR_COUNTS_FUNC(void)
969{
970 switch (cvmx_get_octeon_family()) {
971 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
972 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
973 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
974 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
975 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
976 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
977 return 0x0000000000001200ull;
978 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
979 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
980 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
981 return 0x0000000000001200ull;
982 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
983 return 0x0000000000029200ull;
984 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
985 return 0x0000000000029200ull;
986 }
987 return 0x0000000000029200ull;
988}
989
990#define CVMX_SLI_PKT_IN_INT CVMX_SLI_PKT_IN_INT_FUNC()
991static inline u64 CVMX_SLI_PKT_IN_INT_FUNC(void)
992{
993 switch (cvmx_get_octeon_family()) {
994 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
995 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
996 return 0x0000000000001150ull;
997 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
998 return 0x0000000000029150ull;
999 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1000 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1001 return 0x0000000000029150ull;
1002 }
1003 return 0x0000000000029150ull;
1004}
1005
1006#define CVMX_SLI_PKT_IN_JABBER (0x0000000000029170ull)
1007#define CVMX_SLI_PKT_IN_PCIE_PORT (0x00000000000011B0ull)
1008#define CVMX_SLI_PKT_IPTR (0x0000000000001070ull)
1009#define CVMX_SLI_PKT_MAC0_SIG0 (0x0000000000001300ull)
1010#define CVMX_SLI_PKT_MAC0_SIG1 (0x0000000000001310ull)
1011#define CVMX_SLI_PKT_MAC1_SIG0 (0x0000000000001320ull)
1012#define CVMX_SLI_PKT_MAC1_SIG1 (0x0000000000001330ull)
1013#define CVMX_SLI_PKT_MACX_PFX_RINFO(offset, block_id) \
1014 (0x0000000000029030ull + (((offset) & 1) + ((block_id) & 3) * 0x2ull) * 16)
1015#define CVMX_SLI_PKT_MACX_RINFO(offset) (0x0000000000001030ull + ((offset) & 3) * 16)
1016#define CVMX_SLI_PKT_MEM_CTL CVMX_SLI_PKT_MEM_CTL_FUNC()
1017static inline u64 CVMX_SLI_PKT_MEM_CTL_FUNC(void)
1018{
1019 switch (cvmx_get_octeon_family()) {
1020 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1021 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1022 return 0x0000000000001120ull;
1023 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1024 return 0x0000000000029120ull;
1025 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1026 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1027 return 0x0000000000029120ull;
1028 }
1029 return 0x0000000000029120ull;
1030}
1031
1032#define CVMX_SLI_PKT_OUTPUT_WMARK CVMX_SLI_PKT_OUTPUT_WMARK_FUNC()
1033static inline u64 CVMX_SLI_PKT_OUTPUT_WMARK_FUNC(void)
1034{
1035 switch (cvmx_get_octeon_family()) {
1036 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1037 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1038 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1039 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1040 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1041 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1042 return 0x0000000000001180ull;
1043 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1044 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1045 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1046 return 0x0000000000001180ull;
1047 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1048 return 0x0000000000029180ull;
1049 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1050 return 0x0000000000029180ull;
1051 }
1052 return 0x0000000000029180ull;
1053}
1054
1055#define CVMX_SLI_PKT_OUT_BMODE (0x00000000000010D0ull)
1056#define CVMX_SLI_PKT_OUT_BP_EN (0x0000000000001240ull)
1057#define CVMX_SLI_PKT_OUT_BP_EN2_W1C (0x0000000000029290ull)
1058#define CVMX_SLI_PKT_OUT_BP_EN2_W1S (0x0000000000029270ull)
1059#define CVMX_SLI_PKT_OUT_BP_EN_W1C (0x0000000000029280ull)
1060#define CVMX_SLI_PKT_OUT_BP_EN_W1S (0x0000000000029260ull)
1061#define CVMX_SLI_PKT_OUT_ENB (0x0000000000001010ull)
1062#define CVMX_SLI_PKT_PCIE_PORT (0x00000000000010E0ull)
1063#define CVMX_SLI_PKT_PKIND_VALID (0x0000000000029190ull)
1064#define CVMX_SLI_PKT_PORT_IN_RST (0x00000000000011F0ull)
1065#define CVMX_SLI_PKT_RING_RST CVMX_SLI_PKT_RING_RST_FUNC()
1066static inline u64 CVMX_SLI_PKT_RING_RST_FUNC(void)
1067{
1068 switch (cvmx_get_octeon_family()) {
1069 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1070 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1071 return 0x00000000000011E0ull;
1072 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1073 return 0x00000000000291E0ull;
1074 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1075 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1076 return 0x00000000000291E0ull;
1077 }
1078 return 0x00000000000291E0ull;
1079}
1080
1081#define CVMX_SLI_PKT_SLIST_ES (0x0000000000001050ull)
1082#define CVMX_SLI_PKT_SLIST_NS (0x0000000000001040ull)
1083#define CVMX_SLI_PKT_SLIST_ROR (0x0000000000001030ull)
1084#define CVMX_SLI_PKT_TIME_INT CVMX_SLI_PKT_TIME_INT_FUNC()
1085static inline u64 CVMX_SLI_PKT_TIME_INT_FUNC(void)
1086{
1087 switch (cvmx_get_octeon_family()) {
1088 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1089 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1090 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1091 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1092 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1093 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1094 return 0x0000000000001140ull;
1095 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1096 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1097 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1098 return 0x0000000000001140ull;
1099 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1100 return 0x0000000000029140ull;
1101 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1102 return 0x0000000000029140ull;
1103 }
1104 return 0x0000000000029140ull;
1105}
1106
1107#define CVMX_SLI_PKT_TIME_INT_ENB (0x0000000000001160ull)
1108#define CVMX_SLI_PORTX_PKIND(offset) (0x0000000000000800ull + ((offset) & 31) * 16)
1109#define CVMX_SLI_PP_PKT_CSR_CONTROL (0x00011F00000282D0ull)
1110#define CVMX_SLI_S2C_END_MERGE CVMX_SLI_S2C_END_MERGE_FUNC()
1111static inline u64 CVMX_SLI_S2C_END_MERGE_FUNC(void)
1112{
1113 switch (cvmx_get_octeon_family()) {
1114 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1115 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1116 return 0x00011F0000015000ull;
1117 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1118 return 0x00011F0000025000ull;
1119 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1120 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1121 return 0x00011F0000025000ull;
1122 }
1123 return 0x00011F0000025000ull;
1124}
1125
1126static inline u64 CVMX_SLI_S2M_PORTX_CTL(unsigned long offset)
1127{
1128 switch (cvmx_get_octeon_family()) {
1129 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1130 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1131 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1132 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1133 return 0x0000000000003D80ull + (offset) * 16;
1134 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1135 return 0x0000000000003D80ull + (offset) * 16;
1136 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1137 return 0x0000000000013D80ull + (offset) * 16;
1138 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1139 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1140 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1141 return 0x0000000000003D80ull + (offset) * 16;
1142 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1143 return 0x0000000000023D80ull + (offset) * 16;
1144 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1145 return 0x0000000000023D80ull + (offset) * 16;
1146 }
1147 return 0x0000000000023D80ull + (offset) * 16;
1148}
1149
1150#define CVMX_SLI_SCRATCH_1 CVMX_SLI_SCRATCH_1_FUNC()
1151static inline u64 CVMX_SLI_SCRATCH_1_FUNC(void)
1152{
1153 switch (cvmx_get_octeon_family()) {
1154 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1155 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1156 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1157 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1158 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1159 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1160 return 0x00000000000003C0ull;
1161 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1162 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1163 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1164 return 0x00000000000003C0ull;
1165 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1166 return 0x00000000000283C0ull;
1167 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1168 return 0x00000000000283C0ull;
1169 }
1170 return 0x00000000000283C0ull;
1171}
1172
1173#define CVMX_SLI_SCRATCH_2 CVMX_SLI_SCRATCH_2_FUNC()
1174static inline u64 CVMX_SLI_SCRATCH_2_FUNC(void)
1175{
1176 switch (cvmx_get_octeon_family()) {
1177 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1178 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1179 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1180 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1181 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1182 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1183 return 0x00000000000003D0ull;
1184 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1185 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1186 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1187 return 0x00000000000003D0ull;
1188 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1189 return 0x00000000000283D0ull;
1190 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1191 return 0x00000000000283D0ull;
1192 }
1193 return 0x00000000000283D0ull;
1194}
1195
1196#define CVMX_SLI_STATE1 CVMX_SLI_STATE1_FUNC()
1197static inline u64 CVMX_SLI_STATE1_FUNC(void)
1198{
1199 switch (cvmx_get_octeon_family()) {
1200 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1201 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1202 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1203 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1204 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1205 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1206 return 0x0000000000000620ull;
1207 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1208 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1209 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1210 return 0x0000000000000620ull;
1211 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1212 return 0x0000000000028620ull;
1213 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1214 return 0x0000000000028620ull;
1215 }
1216 return 0x0000000000028620ull;
1217}
1218
1219#define CVMX_SLI_STATE2 CVMX_SLI_STATE2_FUNC()
1220static inline u64 CVMX_SLI_STATE2_FUNC(void)
1221{
1222 switch (cvmx_get_octeon_family()) {
1223 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1224 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1225 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1226 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1227 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1228 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1229 return 0x0000000000000630ull;
1230 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1231 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1232 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1233 return 0x0000000000000630ull;
1234 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1235 return 0x0000000000028630ull;
1236 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1237 return 0x0000000000028630ull;
1238 }
1239 return 0x0000000000028630ull;
1240}
1241
1242#define CVMX_SLI_STATE3 CVMX_SLI_STATE3_FUNC()
1243static inline u64 CVMX_SLI_STATE3_FUNC(void)
1244{
1245 switch (cvmx_get_octeon_family()) {
1246 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1247 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1248 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1249 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1250 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1251 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1252 return 0x0000000000000640ull;
1253 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1254 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1255 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1256 return 0x0000000000000640ull;
1257 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1258 return 0x0000000000028640ull;
1259 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1260 return 0x0000000000028640ull;
1261 }
1262 return 0x0000000000028640ull;
1263}
1264
1265#define CVMX_SLI_TX_PIPE (0x0000000000001230ull)
1266#define CVMX_SLI_WINDOW_CTL CVMX_SLI_WINDOW_CTL_FUNC()
1267static inline u64 CVMX_SLI_WINDOW_CTL_FUNC(void)
1268{
1269 switch (cvmx_get_octeon_family()) {
1270 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1271 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1272 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1273 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1274 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1275 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1276 return 0x00000000000002E0ull;
1277 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1278 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1279 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1280 return 0x00000000000002E0ull;
1281 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1282 return 0x00000000000282E0ull;
1283 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1284 return 0x00000000000282E0ull;
1285 }
1286 return 0x00000000000282E0ull;
1287}
1288
1289#define CVMX_SLI_WIN_RD_ADDR CVMX_SLI_WIN_RD_ADDR_FUNC()
1290static inline u64 CVMX_SLI_WIN_RD_ADDR_FUNC(void)
1291{
1292 switch (cvmx_get_octeon_family()) {
1293 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1294 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1295 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1296 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1297 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1298 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1299 return 0x0000000000000010ull;
1300 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1301 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1302 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1303 return 0x0000000000000010ull;
1304 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1305 return 0x0000000000020010ull;
1306 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1307 return 0x0000000000020010ull;
1308 }
1309 return 0x0000000000020010ull;
1310}
1311
1312#define CVMX_SLI_WIN_RD_DATA CVMX_SLI_WIN_RD_DATA_FUNC()
1313static inline u64 CVMX_SLI_WIN_RD_DATA_FUNC(void)
1314{
1315 switch (cvmx_get_octeon_family()) {
1316 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1317 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1318 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1319 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1320 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1321 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1322 return 0x0000000000000040ull;
1323 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1324 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1325 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1326 return 0x0000000000000040ull;
1327 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1328 return 0x0000000000020040ull;
1329 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1330 return 0x0000000000020040ull;
1331 }
1332 return 0x0000000000020040ull;
1333}
1334
1335#define CVMX_SLI_WIN_WR_ADDR CVMX_SLI_WIN_WR_ADDR_FUNC()
1336static inline u64 CVMX_SLI_WIN_WR_ADDR_FUNC(void)
1337{
1338 switch (cvmx_get_octeon_family()) {
1339 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1340 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1341 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1342 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1343 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1344 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1345 return 0x0000000000000000ull;
1346 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1347 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1348 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1349 return 0x0000000000000000ull;
1350 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1351 return 0x0000000000020000ull;
1352 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1353 return 0x0000000000020000ull;
1354 }
1355 return 0x0000000000020000ull;
1356}
1357
1358#define CVMX_SLI_WIN_WR_DATA CVMX_SLI_WIN_WR_DATA_FUNC()
1359static inline u64 CVMX_SLI_WIN_WR_DATA_FUNC(void)
1360{
1361 switch (cvmx_get_octeon_family()) {
1362 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1363 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1364 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1365 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1366 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1367 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1368 return 0x0000000000000020ull;
1369 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1370 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1371 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1372 return 0x0000000000000020ull;
1373 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1374 return 0x0000000000020020ull;
1375 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1376 return 0x0000000000020020ull;
1377 }
1378 return 0x0000000000020020ull;
1379}
1380
1381#define CVMX_SLI_WIN_WR_MASK CVMX_SLI_WIN_WR_MASK_FUNC()
1382static inline u64 CVMX_SLI_WIN_WR_MASK_FUNC(void)
1383{
1384 switch (cvmx_get_octeon_family()) {
1385 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1386 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1387 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1388 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1389 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1390 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1391 return 0x0000000000000030ull;
1392 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
1393 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
1394 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
1395 return 0x0000000000000030ull;
1396 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
1397 return 0x0000000000020030ull;
1398 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
1399 return 0x0000000000020030ull;
1400 }
1401 return 0x0000000000020030ull;
1402}
1403
1404/**
1405 * cvmx_sli_bist_status
1406 *
1407 * This register contains results from BIST runs of MAC's memories: 0 = pass (or BIST in
1408 * progress/never run), 1 = fail.
1409 */
1410union cvmx_sli_bist_status {
1411 u64 u64;
1412 struct cvmx_sli_bist_status_s {
1413 u64 reserved_32_63 : 32;
1414 u64 ncb_req : 1;
1415 u64 n2p0_c : 1;
1416 u64 n2p0_o : 1;
1417 u64 n2p1_c : 1;
1418 u64 n2p1_o : 1;
1419 u64 cpl_p0 : 1;
1420 u64 cpl_p1 : 1;
1421 u64 reserved_19_24 : 6;
1422 u64 p2n0_c0 : 1;
1423 u64 p2n0_c1 : 1;
1424 u64 p2n0_n : 1;
1425 u64 p2n0_p0 : 1;
1426 u64 p2n0_p1 : 1;
1427 u64 p2n1_c0 : 1;
1428 u64 p2n1_c1 : 1;
1429 u64 p2n1_n : 1;
1430 u64 p2n1_p0 : 1;
1431 u64 p2n1_p1 : 1;
1432 u64 reserved_6_8 : 3;
1433 u64 dsi1_1 : 1;
1434 u64 dsi1_0 : 1;
1435 u64 dsi0_1 : 1;
1436 u64 dsi0_0 : 1;
1437 u64 msi : 1;
1438 u64 ncb_cmd : 1;
1439 } s;
1440 struct cvmx_sli_bist_status_cn61xx {
1441 u64 reserved_31_63 : 33;
1442 u64 n2p0_c : 1;
1443 u64 n2p0_o : 1;
1444 u64 reserved_27_28 : 2;
1445 u64 cpl_p0 : 1;
1446 u64 cpl_p1 : 1;
1447 u64 reserved_19_24 : 6;
1448 u64 p2n0_c0 : 1;
1449 u64 p2n0_c1 : 1;
1450 u64 p2n0_n : 1;
1451 u64 p2n0_p0 : 1;
1452 u64 p2n0_p1 : 1;
1453 u64 p2n1_c0 : 1;
1454 u64 p2n1_c1 : 1;
1455 u64 p2n1_n : 1;
1456 u64 p2n1_p0 : 1;
1457 u64 p2n1_p1 : 1;
1458 u64 reserved_6_8 : 3;
1459 u64 dsi1_1 : 1;
1460 u64 dsi1_0 : 1;
1461 u64 dsi0_1 : 1;
1462 u64 dsi0_0 : 1;
1463 u64 msi : 1;
1464 u64 ncb_cmd : 1;
1465 } cn61xx;
1466 struct cvmx_sli_bist_status_cn63xx {
1467 u64 reserved_31_63 : 33;
1468 u64 n2p0_c : 1;
1469 u64 n2p0_o : 1;
1470 u64 n2p1_c : 1;
1471 u64 n2p1_o : 1;
1472 u64 cpl_p0 : 1;
1473 u64 cpl_p1 : 1;
1474 u64 reserved_19_24 : 6;
1475 u64 p2n0_c0 : 1;
1476 u64 p2n0_c1 : 1;
1477 u64 p2n0_n : 1;
1478 u64 p2n0_p0 : 1;
1479 u64 p2n0_p1 : 1;
1480 u64 p2n1_c0 : 1;
1481 u64 p2n1_c1 : 1;
1482 u64 p2n1_n : 1;
1483 u64 p2n1_p0 : 1;
1484 u64 p2n1_p1 : 1;
1485 u64 reserved_6_8 : 3;
1486 u64 dsi1_1 : 1;
1487 u64 dsi1_0 : 1;
1488 u64 dsi0_1 : 1;
1489 u64 dsi0_0 : 1;
1490 u64 msi : 1;
1491 u64 ncb_cmd : 1;
1492 } cn63xx;
1493 struct cvmx_sli_bist_status_cn63xx cn63xxp1;
1494 struct cvmx_sli_bist_status_cn61xx cn66xx;
1495 struct cvmx_sli_bist_status_s cn68xx;
1496 struct cvmx_sli_bist_status_s cn68xxp1;
1497 struct cvmx_sli_bist_status_cn70xx {
1498 u64 reserved_31_63 : 33;
1499 u64 n2p0_c : 1;
1500 u64 n2p0_o : 1;
1501 u64 reserved_27_28 : 2;
1502 u64 cpl_p0 : 1;
1503 u64 cpl_p1 : 1;
1504 u64 reserved_19_24 : 6;
1505 u64 p2n0_c0 : 1;
1506 u64 reserved_17_17 : 1;
1507 u64 p2n0_n : 1;
1508 u64 p2n0_p0 : 1;
1509 u64 reserved_14_14 : 1;
1510 u64 p2n1_c0 : 1;
1511 u64 reserved_12_12 : 1;
1512 u64 p2n1_n : 1;
1513 u64 p2n1_p0 : 1;
1514 u64 reserved_6_9 : 4;
1515 u64 dsi1_1 : 1;
1516 u64 dsi1_0 : 1;
1517 u64 dsi0_1 : 1;
1518 u64 dsi0_0 : 1;
1519 u64 msi : 1;
1520 u64 ncb_cmd : 1;
1521 } cn70xx;
1522 struct cvmx_sli_bist_status_cn70xx cn70xxp1;
1523 struct cvmx_sli_bist_status_s cn73xx;
1524 struct cvmx_sli_bist_status_s cn78xx;
1525 struct cvmx_sli_bist_status_s cn78xxp1;
1526 struct cvmx_sli_bist_status_cn61xx cnf71xx;
1527 struct cvmx_sli_bist_status_s cnf75xx;
1528};
1529
1530typedef union cvmx_sli_bist_status cvmx_sli_bist_status_t;
1531
1532/**
1533 * cvmx_sli_ciu_int_enb
1534 *
1535 * Interrupt enable register for a given SLI_CIU_INT_SUM register.
1536 *
1537 */
1538union cvmx_sli_ciu_int_enb {
1539 u64 u64;
1540 struct cvmx_sli_ciu_int_enb_s {
1541 u64 reserved_51_63 : 13;
1542 u64 m3_un_wi : 1;
1543 u64 m3_un_b0 : 1;
1544 u64 m3_up_wi : 1;
1545 u64 m3_up_b0 : 1;
1546 u64 m2_un_wi : 1;
1547 u64 m2_un_b0 : 1;
1548 u64 m2_up_wi : 1;
1549 u64 m2_up_b0 : 1;
1550 u64 m1_un_wi : 1;
1551 u64 m1_un_b0 : 1;
1552 u64 m1_up_wi : 1;
1553 u64 m1_up_b0 : 1;
1554 u64 m0_un_wi : 1;
1555 u64 m0_un_b0 : 1;
1556 u64 m0_up_wi : 1;
1557 u64 m0_up_b0 : 1;
1558 u64 m3p0_pppf_err : 1;
1559 u64 m3p0_pktpf_err : 1;
1560 u64 m3p0_dmapf_err : 1;
1561 u64 m2p0_pppf_err : 1;
1562 u64 m2p0_ppvf_err : 1;
1563 u64 m2p0_pktpf_err : 1;
1564 u64 m2p0_pktvf_err : 1;
1565 u64 m2p0_dmapf_err : 1;
1566 u64 m2p0_dmavf_err : 1;
1567 u64 m1p0_pppf_err : 1;
1568 u64 m1p0_pktpf_err : 1;
1569 u64 m1p0_dmapf_err : 1;
1570 u64 m0p1_pppf_err : 1;
1571 u64 m0p1_ppvf_err : 1;
1572 u64 m0p1_pktpf_err : 1;
1573 u64 m0p1_pktvf_err : 1;
1574 u64 m0p1_dmapf_err : 1;
1575 u64 m0p1_dmavf_err : 1;
1576 u64 m0p0_pppf_err : 1;
1577 u64 m0p0_ppvf_err : 1;
1578 u64 m0p0_pktpf_err : 1;
1579 u64 m0p0_pktvf_err : 1;
1580 u64 m0p0_dmapf_err : 1;
1581 u64 m0p0_dmavf_err : 1;
1582 u64 m2v0_flr : 1;
1583 u64 m2p0_flr : 1;
1584 u64 reserved_5_8 : 4;
1585 u64 m0v1_flr : 1;
1586 u64 m0p1_flr : 1;
1587 u64 m0v0_flr : 1;
1588 u64 m0p0_flr : 1;
1589 u64 rml_to : 1;
1590 } s;
1591 struct cvmx_sli_ciu_int_enb_s cn73xx;
1592 struct cvmx_sli_ciu_int_enb_s cn78xx;
1593 struct cvmx_sli_ciu_int_enb_s cnf75xx;
1594};
1595
1596typedef union cvmx_sli_ciu_int_enb cvmx_sli_ciu_int_enb_t;
1597
1598/**
1599 * cvmx_sli_ciu_int_sum
1600 *
1601 * The fields in this register are set when an interrupt condition occurs; write 1 to clear.
1602 * A bit set in this register will send and interrupt to CIU
1603 */
1604union cvmx_sli_ciu_int_sum {
1605 u64 u64;
1606 struct cvmx_sli_ciu_int_sum_s {
1607 u64 reserved_51_63 : 13;
1608 u64 m3_un_wi : 1;
1609 u64 m3_un_b0 : 1;
1610 u64 m3_up_wi : 1;
1611 u64 m3_up_b0 : 1;
1612 u64 m2_un_wi : 1;
1613 u64 m2_un_b0 : 1;
1614 u64 m2_up_wi : 1;
1615 u64 m2_up_b0 : 1;
1616 u64 m1_un_wi : 1;
1617 u64 m1_un_b0 : 1;
1618 u64 m1_up_wi : 1;
1619 u64 m1_up_b0 : 1;
1620 u64 m0_un_wi : 1;
1621 u64 m0_un_b0 : 1;
1622 u64 m0_up_wi : 1;
1623 u64 m0_up_b0 : 1;
1624 u64 m3p0_pppf_err : 1;
1625 u64 m3p0_pktpf_err : 1;
1626 u64 m3p0_dmapf_err : 1;
1627 u64 m2p0_pppf_err : 1;
1628 u64 m2p0_ppvf_err : 1;
1629 u64 m2p0_pktpf_err : 1;
1630 u64 m2p0_pktvf_err : 1;
1631 u64 m2p0_dmapf_err : 1;
1632 u64 m2p0_dmavf_err : 1;
1633 u64 m1p0_pppf_err : 1;
1634 u64 m1p0_pktpf_err : 1;
1635 u64 m1p0_dmapf_err : 1;
1636 u64 m0p1_pppf_err : 1;
1637 u64 m0p1_ppvf_err : 1;
1638 u64 m0p1_pktpf_err : 1;
1639 u64 m0p1_pktvf_err : 1;
1640 u64 m0p1_dmapf_err : 1;
1641 u64 m0p1_dmavf_err : 1;
1642 u64 m0p0_pppf_err : 1;
1643 u64 m0p0_ppvf_err : 1;
1644 u64 m0p0_pktpf_err : 1;
1645 u64 m0p0_pktvf_err : 1;
1646 u64 m0p0_dmapf_err : 1;
1647 u64 m0p0_dmavf_err : 1;
1648 u64 m2v0_flr : 1;
1649 u64 m2p0_flr : 1;
1650 u64 reserved_5_8 : 4;
1651 u64 m0v1_flr : 1;
1652 u64 m0p1_flr : 1;
1653 u64 m0v0_flr : 1;
1654 u64 m0p0_flr : 1;
1655 u64 rml_to : 1;
1656 } s;
1657 struct cvmx_sli_ciu_int_sum_s cn73xx;
1658 struct cvmx_sli_ciu_int_sum_s cn78xx;
1659 struct cvmx_sli_ciu_int_sum_s cnf75xx;
1660};
1661
1662typedef union cvmx_sli_ciu_int_sum cvmx_sli_ciu_int_sum_t;
1663
1664/**
1665 * cvmx_sli_ctl_port#
1666 *
1667 * These registers contains control information for access to ports. Indexed by SLI_PORT_E.
1668 * Note: SLI_CTL_PORT0 controls PF0.
1669 */
1670union cvmx_sli_ctl_portx {
1671 u64 u64;
1672 struct cvmx_sli_ctl_portx_s {
1673 u64 reserved_22_63 : 42;
1674 u64 intd : 1;
1675 u64 intc : 1;
1676 u64 intb : 1;
1677 u64 inta : 1;
1678 u64 dis_port : 1;
1679 u64 waitl_com : 1;
1680 u64 intd_map : 2;
1681 u64 intc_map : 2;
1682 u64 intb_map : 2;
1683 u64 inta_map : 2;
1684 u64 ctlp_ro : 1;
1685 u64 reserved_6_6 : 1;
1686 u64 ptlp_ro : 1;
1687 u64 reserved_1_4 : 4;
1688 u64 wait_com : 1;
1689 } s;
1690 struct cvmx_sli_ctl_portx_s cn61xx;
1691 struct cvmx_sli_ctl_portx_s cn63xx;
1692 struct cvmx_sli_ctl_portx_s cn63xxp1;
1693 struct cvmx_sli_ctl_portx_s cn66xx;
1694 struct cvmx_sli_ctl_portx_s cn68xx;
1695 struct cvmx_sli_ctl_portx_s cn68xxp1;
1696 struct cvmx_sli_ctl_portx_cn70xx {
1697 u64 reserved_22_63 : 42;
1698 u64 intd : 1;
1699 u64 intc : 1;
1700 u64 intb : 1;
1701 u64 inta : 1;
1702 u64 dis_port : 1;
1703 u64 waitl_com : 1;
1704 u64 intd_map : 2;
1705 u64 intc_map : 2;
1706 u64 intb_map : 2;
1707 u64 inta_map : 2;
1708 u64 ctlp_ro : 1;
1709 u64 reserved_6_6 : 1;
1710 u64 ptlp_ro : 1;
1711 u64 reserved_4_1 : 4;
1712 u64 wait_com : 1;
1713 } cn70xx;
1714 struct cvmx_sli_ctl_portx_cn70xx cn70xxp1;
1715 struct cvmx_sli_ctl_portx_cn73xx {
1716 u64 reserved_18_63 : 46;
1717 u64 dis_port : 1;
1718 u64 waitl_com : 1;
1719 u64 reserved_8_15 : 8;
1720 u64 ctlp_ro : 1;
1721 u64 reserved_6_6 : 1;
1722 u64 ptlp_ro : 1;
1723 u64 reserved_1_4 : 4;
1724 u64 wait_com : 1;
1725 } cn73xx;
1726 struct cvmx_sli_ctl_portx_cn73xx cn78xx;
1727 struct cvmx_sli_ctl_portx_cn73xx cn78xxp1;
1728 struct cvmx_sli_ctl_portx_s cnf71xx;
1729 struct cvmx_sli_ctl_portx_cn73xx cnf75xx;
1730};
1731
1732typedef union cvmx_sli_ctl_portx cvmx_sli_ctl_portx_t;
1733
1734/**
1735 * cvmx_sli_ctl_status
1736 *
1737 * This register contains control and status for SLI. Write operations to this register are not
1738 * ordered with write/read operations to the MAC memory space. To ensure that a write has
1739 * completed, software must read the register before making an access (i.e. MAC memory space)
1740 * that requires the value of this register to be updated.
1741 */
1742union cvmx_sli_ctl_status {
1743 u64 u64;
1744 struct cvmx_sli_ctl_status_s {
1745 u64 reserved_32_63 : 32;
1746 u64 m2s1_ncbi : 4;
1747 u64 m2s0_ncbi : 4;
1748 u64 oci_id : 4;
1749 u64 p1_ntags : 6;
1750 u64 p0_ntags : 6;
1751 u64 chip_rev : 8;
1752 } s;
1753 struct cvmx_sli_ctl_status_cn61xx {
1754 u64 reserved_14_63 : 50;
1755 u64 p0_ntags : 6;
1756 u64 chip_rev : 8;
1757 } cn61xx;
1758 struct cvmx_sli_ctl_status_cn63xx {
1759 u64 reserved_20_63 : 44;
1760 u64 p1_ntags : 6;
1761 u64 p0_ntags : 6;
1762 u64 chip_rev : 8;
1763 } cn63xx;
1764 struct cvmx_sli_ctl_status_cn63xx cn63xxp1;
1765 struct cvmx_sli_ctl_status_cn61xx cn66xx;
1766 struct cvmx_sli_ctl_status_cn63xx cn68xx;
1767 struct cvmx_sli_ctl_status_cn63xx cn68xxp1;
1768 struct cvmx_sli_ctl_status_cn63xx cn70xx;
1769 struct cvmx_sli_ctl_status_cn63xx cn70xxp1;
1770 struct cvmx_sli_ctl_status_cn73xx {
1771 u64 reserved_32_63 : 32;
1772 u64 m2s1_ncbi : 4;
1773 u64 m2s0_ncbi : 4;
1774 u64 reserved_20_23 : 4;
1775 u64 p1_ntags : 6;
1776 u64 p0_ntags : 6;
1777 u64 chip_rev : 8;
1778 } cn73xx;
1779 struct cvmx_sli_ctl_status_s cn78xx;
1780 struct cvmx_sli_ctl_status_s cn78xxp1;
1781 struct cvmx_sli_ctl_status_cn61xx cnf71xx;
1782 struct cvmx_sli_ctl_status_cn73xx cnf75xx;
1783};
1784
1785typedef union cvmx_sli_ctl_status cvmx_sli_ctl_status_t;
1786
1787/**
1788 * cvmx_sli_data_out_cnt
1789 *
1790 * This register contains the EXEC data out FIFO count and the data unload counter.
1791 *
1792 */
1793union cvmx_sli_data_out_cnt {
1794 u64 u64;
1795 struct cvmx_sli_data_out_cnt_s {
1796 u64 reserved_44_63 : 20;
1797 u64 p1_ucnt : 16;
1798 u64 p1_fcnt : 6;
1799 u64 p0_ucnt : 16;
1800 u64 p0_fcnt : 6;
1801 } s;
1802 struct cvmx_sli_data_out_cnt_s cn61xx;
1803 struct cvmx_sli_data_out_cnt_s cn63xx;
1804 struct cvmx_sli_data_out_cnt_s cn63xxp1;
1805 struct cvmx_sli_data_out_cnt_s cn66xx;
1806 struct cvmx_sli_data_out_cnt_s cn68xx;
1807 struct cvmx_sli_data_out_cnt_s cn68xxp1;
1808 struct cvmx_sli_data_out_cnt_s cn70xx;
1809 struct cvmx_sli_data_out_cnt_s cn70xxp1;
1810 struct cvmx_sli_data_out_cnt_s cn73xx;
1811 struct cvmx_sli_data_out_cnt_s cn78xx;
1812 struct cvmx_sli_data_out_cnt_s cn78xxp1;
1813 struct cvmx_sli_data_out_cnt_s cnf71xx;
1814 struct cvmx_sli_data_out_cnt_s cnf75xx;
1815};
1816
1817typedef union cvmx_sli_data_out_cnt cvmx_sli_data_out_cnt_t;
1818
1819/**
1820 * cvmx_sli_dbg_data
1821 *
1822 * SLI_DBG_DATA = SLI Debug Data Register
1823 *
1824 * Value returned on the debug-data lines from the RSLs
1825 */
1826union cvmx_sli_dbg_data {
1827 u64 u64;
1828 struct cvmx_sli_dbg_data_s {
1829 u64 reserved_18_63 : 46;
1830 u64 dsel_ext : 1;
1831 u64 data : 17;
1832 } s;
1833 struct cvmx_sli_dbg_data_s cn61xx;
1834 struct cvmx_sli_dbg_data_s cn63xx;
1835 struct cvmx_sli_dbg_data_s cn63xxp1;
1836 struct cvmx_sli_dbg_data_s cn66xx;
1837 struct cvmx_sli_dbg_data_s cn68xx;
1838 struct cvmx_sli_dbg_data_s cn68xxp1;
1839 struct cvmx_sli_dbg_data_s cnf71xx;
1840};
1841
1842typedef union cvmx_sli_dbg_data cvmx_sli_dbg_data_t;
1843
1844/**
1845 * cvmx_sli_dbg_select
1846 *
1847 * SLI_DBG_SELECT = Debug Select Register
1848 *
1849 * Contains the debug select value last written to the RSLs.
1850 */
1851union cvmx_sli_dbg_select {
1852 u64 u64;
1853 struct cvmx_sli_dbg_select_s {
1854 u64 reserved_33_63 : 31;
1855 u64 adbg_sel : 1;
1856 u64 dbg_sel : 32;
1857 } s;
1858 struct cvmx_sli_dbg_select_s cn61xx;
1859 struct cvmx_sli_dbg_select_s cn63xx;
1860 struct cvmx_sli_dbg_select_s cn63xxp1;
1861 struct cvmx_sli_dbg_select_s cn66xx;
1862 struct cvmx_sli_dbg_select_s cn68xx;
1863 struct cvmx_sli_dbg_select_s cn68xxp1;
1864 struct cvmx_sli_dbg_select_s cnf71xx;
1865};
1866
1867typedef union cvmx_sli_dbg_select cvmx_sli_dbg_select_t;
1868
1869/**
1870 * cvmx_sli_dma#_cnt
1871 *
1872 * These registers contain the DMA count values.
1873 *
1874 */
1875union cvmx_sli_dmax_cnt {
1876 u64 u64;
1877 struct cvmx_sli_dmax_cnt_s {
1878 u64 reserved_32_63 : 32;
1879 u64 cnt : 32;
1880 } s;
1881 struct cvmx_sli_dmax_cnt_s cn61xx;
1882 struct cvmx_sli_dmax_cnt_s cn63xx;
1883 struct cvmx_sli_dmax_cnt_s cn63xxp1;
1884 struct cvmx_sli_dmax_cnt_s cn66xx;
1885 struct cvmx_sli_dmax_cnt_s cn68xx;
1886 struct cvmx_sli_dmax_cnt_s cn68xxp1;
1887 struct cvmx_sli_dmax_cnt_s cn70xx;
1888 struct cvmx_sli_dmax_cnt_s cn70xxp1;
1889 struct cvmx_sli_dmax_cnt_s cn73xx;
1890 struct cvmx_sli_dmax_cnt_s cn78xx;
1891 struct cvmx_sli_dmax_cnt_s cn78xxp1;
1892 struct cvmx_sli_dmax_cnt_s cnf71xx;
1893 struct cvmx_sli_dmax_cnt_s cnf75xx;
1894};
1895
1896typedef union cvmx_sli_dmax_cnt cvmx_sli_dmax_cnt_t;
1897
1898/**
1899 * cvmx_sli_dma#_int_level
1900 *
1901 * These registers contain the thresholds for DMA count and timer interrupts.
1902 *
1903 */
1904union cvmx_sli_dmax_int_level {
1905 u64 u64;
1906 struct cvmx_sli_dmax_int_level_s {
1907 u64 time : 32;
1908 u64 cnt : 32;
1909 } s;
1910 struct cvmx_sli_dmax_int_level_s cn61xx;
1911 struct cvmx_sli_dmax_int_level_s cn63xx;
1912 struct cvmx_sli_dmax_int_level_s cn63xxp1;
1913 struct cvmx_sli_dmax_int_level_s cn66xx;
1914 struct cvmx_sli_dmax_int_level_s cn68xx;
1915 struct cvmx_sli_dmax_int_level_s cn68xxp1;
1916 struct cvmx_sli_dmax_int_level_s cn70xx;
1917 struct cvmx_sli_dmax_int_level_s cn70xxp1;
1918 struct cvmx_sli_dmax_int_level_s cn73xx;
1919 struct cvmx_sli_dmax_int_level_s cn78xx;
1920 struct cvmx_sli_dmax_int_level_s cn78xxp1;
1921 struct cvmx_sli_dmax_int_level_s cnf71xx;
1922 struct cvmx_sli_dmax_int_level_s cnf75xx;
1923};
1924
1925typedef union cvmx_sli_dmax_int_level cvmx_sli_dmax_int_level_t;
1926
1927/**
1928 * cvmx_sli_dma#_tim
1929 *
1930 * These registers contain the DMA timer values.
1931 *
1932 */
1933union cvmx_sli_dmax_tim {
1934 u64 u64;
1935 struct cvmx_sli_dmax_tim_s {
1936 u64 reserved_32_63 : 32;
1937 u64 tim : 32;
1938 } s;
1939 struct cvmx_sli_dmax_tim_s cn61xx;
1940 struct cvmx_sli_dmax_tim_s cn63xx;
1941 struct cvmx_sli_dmax_tim_s cn63xxp1;
1942 struct cvmx_sli_dmax_tim_s cn66xx;
1943 struct cvmx_sli_dmax_tim_s cn68xx;
1944 struct cvmx_sli_dmax_tim_s cn68xxp1;
1945 struct cvmx_sli_dmax_tim_s cn70xx;
1946 struct cvmx_sli_dmax_tim_s cn70xxp1;
1947 struct cvmx_sli_dmax_tim_s cn73xx;
1948 struct cvmx_sli_dmax_tim_s cn78xx;
1949 struct cvmx_sli_dmax_tim_s cn78xxp1;
1950 struct cvmx_sli_dmax_tim_s cnf71xx;
1951 struct cvmx_sli_dmax_tim_s cnf75xx;
1952};
1953
1954typedef union cvmx_sli_dmax_tim cvmx_sli_dmax_tim_t;
1955
1956/**
1957 * cvmx_sli_int_enb_ciu
1958 *
1959 * Used to enable the various interrupting conditions of SLI
1960 *
1961 */
1962union cvmx_sli_int_enb_ciu {
1963 u64 u64;
1964 struct cvmx_sli_int_enb_ciu_s {
1965 u64 reserved_62_63 : 2;
1966 u64 pipe_err : 1;
1967 u64 ill_pad : 1;
1968 u64 sprt3_err : 1;
1969 u64 sprt2_err : 1;
1970 u64 sprt1_err : 1;
1971 u64 sprt0_err : 1;
1972 u64 pins_err : 1;
1973 u64 pop_err : 1;
1974 u64 pdi_err : 1;
1975 u64 pgl_err : 1;
1976 u64 pin_bp : 1;
1977 u64 pout_err : 1;
1978 u64 psldbof : 1;
1979 u64 pidbof : 1;
1980 u64 reserved_38_47 : 10;
1981 u64 dtime : 2;
1982 u64 dcnt : 2;
1983 u64 dmafi : 2;
1984 u64 reserved_29_31 : 3;
1985 u64 mio_int2 : 1;
1986 u64 m3_un_wi : 1;
1987 u64 m3_un_b0 : 1;
1988 u64 m3_up_wi : 1;
1989 u64 m3_up_b0 : 1;
1990 u64 m2_un_wi : 1;
1991 u64 m2_un_b0 : 1;
1992 u64 m2_up_wi : 1;
1993 u64 m2_up_b0 : 1;
1994 u64 reserved_18_19 : 2;
1995 u64 mio_int1 : 1;
1996 u64 mio_int0 : 1;
1997 u64 m1_un_wi : 1;
1998 u64 m1_un_b0 : 1;
1999 u64 m1_up_wi : 1;
2000 u64 m1_up_b0 : 1;
2001 u64 m0_un_wi : 1;
2002 u64 m0_un_b0 : 1;
2003 u64 m0_up_wi : 1;
2004 u64 m0_up_b0 : 1;
2005 u64 reserved_6_7 : 2;
2006 u64 ptime : 1;
2007 u64 pcnt : 1;
2008 u64 iob2big : 1;
2009 u64 bar0_to : 1;
2010 u64 reserved_1_1 : 1;
2011 u64 rml_to : 1;
2012 } s;
2013 struct cvmx_sli_int_enb_ciu_cn61xx {
2014 u64 reserved_61_63 : 3;
2015 u64 ill_pad : 1;
2016 u64 sprt3_err : 1;
2017 u64 sprt2_err : 1;
2018 u64 sprt1_err : 1;
2019 u64 sprt0_err : 1;
2020 u64 pins_err : 1;
2021 u64 pop_err : 1;
2022 u64 pdi_err : 1;
2023 u64 pgl_err : 1;
2024 u64 pin_bp : 1;
2025 u64 pout_err : 1;
2026 u64 psldbof : 1;
2027 u64 pidbof : 1;
2028 u64 reserved_38_47 : 10;
2029 u64 dtime : 2;
2030 u64 dcnt : 2;
2031 u64 dmafi : 2;
2032 u64 reserved_28_31 : 4;
2033 u64 m3_un_wi : 1;
2034 u64 m3_un_b0 : 1;
2035 u64 m3_up_wi : 1;
2036 u64 m3_up_b0 : 1;
2037 u64 m2_un_wi : 1;
2038 u64 m2_un_b0 : 1;
2039 u64 m2_up_wi : 1;
2040 u64 m2_up_b0 : 1;
2041 u64 reserved_18_19 : 2;
2042 u64 mio_int1 : 1;
2043 u64 mio_int0 : 1;
2044 u64 m1_un_wi : 1;
2045 u64 m1_un_b0 : 1;
2046 u64 m1_up_wi : 1;
2047 u64 m1_up_b0 : 1;
2048 u64 m0_un_wi : 1;
2049 u64 m0_un_b0 : 1;
2050 u64 m0_up_wi : 1;
2051 u64 m0_up_b0 : 1;
2052 u64 reserved_6_7 : 2;
2053 u64 ptime : 1;
2054 u64 pcnt : 1;
2055 u64 iob2big : 1;
2056 u64 bar0_to : 1;
2057 u64 reserved_1_1 : 1;
2058 u64 rml_to : 1;
2059 } cn61xx;
2060 struct cvmx_sli_int_enb_ciu_cn63xx {
2061 u64 reserved_61_63 : 3;
2062 u64 ill_pad : 1;
2063 u64 reserved_58_59 : 2;
2064 u64 sprt1_err : 1;
2065 u64 sprt0_err : 1;
2066 u64 pins_err : 1;
2067 u64 pop_err : 1;
2068 u64 pdi_err : 1;
2069 u64 pgl_err : 1;
2070 u64 pin_bp : 1;
2071 u64 pout_err : 1;
2072 u64 psldbof : 1;
2073 u64 pidbof : 1;
2074 u64 reserved_38_47 : 10;
2075 u64 dtime : 2;
2076 u64 dcnt : 2;
2077 u64 dmafi : 2;
2078 u64 reserved_18_31 : 14;
2079 u64 mio_int1 : 1;
2080 u64 mio_int0 : 1;
2081 u64 m1_un_wi : 1;
2082 u64 m1_un_b0 : 1;
2083 u64 m1_up_wi : 1;
2084 u64 m1_up_b0 : 1;
2085 u64 m0_un_wi : 1;
2086 u64 m0_un_b0 : 1;
2087 u64 m0_up_wi : 1;
2088 u64 m0_up_b0 : 1;
2089 u64 reserved_6_7 : 2;
2090 u64 ptime : 1;
2091 u64 pcnt : 1;
2092 u64 iob2big : 1;
2093 u64 bar0_to : 1;
2094 u64 reserved_1_1 : 1;
2095 u64 rml_to : 1;
2096 } cn63xx;
2097 struct cvmx_sli_int_enb_ciu_cn63xx cn63xxp1;
2098 struct cvmx_sli_int_enb_ciu_cn61xx cn66xx;
2099 struct cvmx_sli_int_enb_ciu_cn68xx {
2100 u64 reserved_62_63 : 2;
2101 u64 pipe_err : 1;
2102 u64 ill_pad : 1;
2103 u64 reserved_58_59 : 2;
2104 u64 sprt1_err : 1;
2105 u64 sprt0_err : 1;
2106 u64 pins_err : 1;
2107 u64 pop_err : 1;
2108 u64 pdi_err : 1;
2109 u64 pgl_err : 1;
2110 u64 reserved_51_51 : 1;
2111 u64 pout_err : 1;
2112 u64 psldbof : 1;
2113 u64 pidbof : 1;
2114 u64 reserved_38_47 : 10;
2115 u64 dtime : 2;
2116 u64 dcnt : 2;
2117 u64 dmafi : 2;
2118 u64 reserved_18_31 : 14;
2119 u64 mio_int1 : 1;
2120 u64 mio_int0 : 1;
2121 u64 m1_un_wi : 1;
2122 u64 m1_un_b0 : 1;
2123 u64 m1_up_wi : 1;
2124 u64 m1_up_b0 : 1;
2125 u64 m0_un_wi : 1;
2126 u64 m0_un_b0 : 1;
2127 u64 m0_up_wi : 1;
2128 u64 m0_up_b0 : 1;
2129 u64 reserved_6_7 : 2;
2130 u64 ptime : 1;
2131 u64 pcnt : 1;
2132 u64 iob2big : 1;
2133 u64 bar0_to : 1;
2134 u64 reserved_1_1 : 1;
2135 u64 rml_to : 1;
2136 } cn68xx;
2137 struct cvmx_sli_int_enb_ciu_cn68xx cn68xxp1;
2138 struct cvmx_sli_int_enb_ciu_cn70xx {
2139 u64 reserved_63_61 : 3;
2140 u64 ill_pad : 1;
2141 u64 sprt3_err : 1;
2142 u64 sprt2_err : 1;
2143 u64 sprt1_err : 1;
2144 u64 sprt0_err : 1;
2145 u64 pins_err : 1;
2146 u64 pop_err : 1;
2147 u64 pdi_err : 1;
2148 u64 pgl_err : 1;
2149 u64 pin_bp : 1;
2150 u64 pout_err : 1;
2151 u64 psldbof : 1;
2152 u64 pidbof : 1;
2153 u64 reserved_47_38 : 10;
2154 u64 dtime : 2;
2155 u64 dcnt : 2;
2156 u64 dmafi : 2;
2157 u64 reserved_31_29 : 3;
2158 u64 mio_int2 : 1;
2159 u64 m3_un_wi : 1;
2160 u64 m3_un_b0 : 1;
2161 u64 m3_up_wi : 1;
2162 u64 m3_up_b0 : 1;
2163 u64 m2_un_wi : 1;
2164 u64 m2_un_b0 : 1;
2165 u64 m2_up_wi : 1;
2166 u64 m2_up_b0 : 1;
2167 u64 reserved_19_18 : 2;
2168 u64 mio_int1 : 1;
2169 u64 mio_int0 : 1;
2170 u64 m1_un_wi : 1;
2171 u64 m1_un_b0 : 1;
2172 u64 m1_up_wi : 1;
2173 u64 m1_up_b0 : 1;
2174 u64 m0_un_wi : 1;
2175 u64 m0_un_b0 : 1;
2176 u64 m0_up_wi : 1;
2177 u64 m0_up_b0 : 1;
2178 u64 reserved_7_6 : 2;
2179 u64 ptime : 1;
2180 u64 pcnt : 1;
2181 u64 iob2big : 1;
2182 u64 bar0_to : 1;
2183 u64 reserved_1_1 : 1;
2184 u64 rml_to : 1;
2185 } cn70xx;
2186 struct cvmx_sli_int_enb_ciu_cn70xx cn70xxp1;
2187 struct cvmx_sli_int_enb_ciu_cn61xx cnf71xx;
2188};
2189
2190typedef union cvmx_sli_int_enb_ciu cvmx_sli_int_enb_ciu_t;
2191
2192/**
2193 * cvmx_sli_int_enb_port#
2194 *
2195 * When a field in this register is set, and a corresponding interrupt condition asserts in
2196 * SLI_INT_SUM, an interrupt is generated. Interrupts can be sent to PCIe0 or PCIe1.
2197 */
2198union cvmx_sli_int_enb_portx {
2199 u64 u64;
2200 struct cvmx_sli_int_enb_portx_s {
2201 u64 reserved_62_63 : 2;
2202 u64 pipe_err : 1;
2203 u64 ill_pad : 1;
2204 u64 sprt3_err : 1;
2205 u64 sprt2_err : 1;
2206 u64 sprt1_err : 1;
2207 u64 sprt0_err : 1;
2208 u64 pins_err : 1;
2209 u64 pop_err : 1;
2210 u64 pdi_err : 1;
2211 u64 pgl_err : 1;
2212 u64 pin_bp : 1;
2213 u64 pout_err : 1;
2214 u64 psldbof : 1;
2215 u64 pidbof : 1;
2216 u64 reserved_38_47 : 10;
2217 u64 dtime : 2;
2218 u64 dcnt : 2;
2219 u64 dmafi : 2;
2220 u64 reserved_30_31 : 2;
2221 u64 mac2_int : 1;
2222 u64 reserved_28_28 : 1;
2223 u64 m3_un_wi : 1;
2224 u64 m3_un_b0 : 1;
2225 u64 m3_up_wi : 1;
2226 u64 m3_up_b0 : 1;
2227 u64 m2_un_wi : 1;
2228 u64 m2_un_b0 : 1;
2229 u64 m2_up_wi : 1;
2230 u64 m2_up_b0 : 1;
2231 u64 mac1_int : 1;
2232 u64 mac0_int : 1;
2233 u64 mio_int1 : 1;
2234 u64 mio_int0 : 1;
2235 u64 m1_un_wi : 1;
2236 u64 m1_un_b0 : 1;
2237 u64 m1_up_wi : 1;
2238 u64 m1_up_b0 : 1;
2239 u64 m0_un_wi : 1;
2240 u64 m0_un_b0 : 1;
2241 u64 m0_up_wi : 1;
2242 u64 m0_up_b0 : 1;
2243 u64 mio_int3 : 1;
2244 u64 reserved_6_6 : 1;
2245 u64 ptime : 1;
2246 u64 pcnt : 1;
2247 u64 iob2big : 1;
2248 u64 bar0_to : 1;
2249 u64 reserved_1_1 : 1;
2250 u64 rml_to : 1;
2251 } s;
2252 struct cvmx_sli_int_enb_portx_cn61xx {
2253 u64 reserved_61_63 : 3;
2254 u64 ill_pad : 1;
2255 u64 sprt3_err : 1;
2256 u64 sprt2_err : 1;
2257 u64 sprt1_err : 1;
2258 u64 sprt0_err : 1;
2259 u64 pins_err : 1;
2260 u64 pop_err : 1;
2261 u64 pdi_err : 1;
2262 u64 pgl_err : 1;
2263 u64 pin_bp : 1;
2264 u64 pout_err : 1;
2265 u64 psldbof : 1;
2266 u64 pidbof : 1;
2267 u64 reserved_38_47 : 10;
2268 u64 dtime : 2;
2269 u64 dcnt : 2;
2270 u64 dmafi : 2;
2271 u64 reserved_28_31 : 4;
2272 u64 m3_un_wi : 1;
2273 u64 m3_un_b0 : 1;
2274 u64 m3_up_wi : 1;
2275 u64 m3_up_b0 : 1;
2276 u64 m2_un_wi : 1;
2277 u64 m2_un_b0 : 1;
2278 u64 m2_up_wi : 1;
2279 u64 m2_up_b0 : 1;
2280 u64 mac1_int : 1;
2281 u64 mac0_int : 1;
2282 u64 mio_int1 : 1;
2283 u64 mio_int0 : 1;
2284 u64 m1_un_wi : 1;
2285 u64 m1_un_b0 : 1;
2286 u64 m1_up_wi : 1;
2287 u64 m1_up_b0 : 1;
2288 u64 m0_un_wi : 1;
2289 u64 m0_un_b0 : 1;
2290 u64 m0_up_wi : 1;
2291 u64 m0_up_b0 : 1;
2292 u64 reserved_6_7 : 2;
2293 u64 ptime : 1;
2294 u64 pcnt : 1;
2295 u64 iob2big : 1;
2296 u64 bar0_to : 1;
2297 u64 reserved_1_1 : 1;
2298 u64 rml_to : 1;
2299 } cn61xx;
2300 struct cvmx_sli_int_enb_portx_cn63xx {
2301 u64 reserved_61_63 : 3;
2302 u64 ill_pad : 1;
2303 u64 reserved_58_59 : 2;
2304 u64 sprt1_err : 1;
2305 u64 sprt0_err : 1;
2306 u64 pins_err : 1;
2307 u64 pop_err : 1;
2308 u64 pdi_err : 1;
2309 u64 pgl_err : 1;
2310 u64 pin_bp : 1;
2311 u64 pout_err : 1;
2312 u64 psldbof : 1;
2313 u64 pidbof : 1;
2314 u64 reserved_38_47 : 10;
2315 u64 dtime : 2;
2316 u64 dcnt : 2;
2317 u64 dmafi : 2;
2318 u64 reserved_20_31 : 12;
2319 u64 mac1_int : 1;
2320 u64 mac0_int : 1;
2321 u64 mio_int1 : 1;
2322 u64 mio_int0 : 1;
2323 u64 m1_un_wi : 1;
2324 u64 m1_un_b0 : 1;
2325 u64 m1_up_wi : 1;
2326 u64 m1_up_b0 : 1;
2327 u64 m0_un_wi : 1;
2328 u64 m0_un_b0 : 1;
2329 u64 m0_up_wi : 1;
2330 u64 m0_up_b0 : 1;
2331 u64 reserved_6_7 : 2;
2332 u64 ptime : 1;
2333 u64 pcnt : 1;
2334 u64 iob2big : 1;
2335 u64 bar0_to : 1;
2336 u64 reserved_1_1 : 1;
2337 u64 rml_to : 1;
2338 } cn63xx;
2339 struct cvmx_sli_int_enb_portx_cn63xx cn63xxp1;
2340 struct cvmx_sli_int_enb_portx_cn61xx cn66xx;
2341 struct cvmx_sli_int_enb_portx_cn68xx {
2342 u64 reserved_62_63 : 2;
2343 u64 pipe_err : 1;
2344 u64 ill_pad : 1;
2345 u64 reserved_58_59 : 2;
2346 u64 sprt1_err : 1;
2347 u64 sprt0_err : 1;
2348 u64 pins_err : 1;
2349 u64 pop_err : 1;
2350 u64 pdi_err : 1;
2351 u64 pgl_err : 1;
2352 u64 reserved_51_51 : 1;
2353 u64 pout_err : 1;
2354 u64 psldbof : 1;
2355 u64 pidbof : 1;
2356 u64 reserved_38_47 : 10;
2357 u64 dtime : 2;
2358 u64 dcnt : 2;
2359 u64 dmafi : 2;
2360 u64 reserved_20_31 : 12;
2361 u64 mac1_int : 1;
2362 u64 mac0_int : 1;
2363 u64 mio_int1 : 1;
2364 u64 mio_int0 : 1;
2365 u64 m1_un_wi : 1;
2366 u64 m1_un_b0 : 1;
2367 u64 m1_up_wi : 1;
2368 u64 m1_up_b0 : 1;
2369 u64 m0_un_wi : 1;
2370 u64 m0_un_b0 : 1;
2371 u64 m0_up_wi : 1;
2372 u64 m0_up_b0 : 1;
2373 u64 reserved_6_7 : 2;
2374 u64 ptime : 1;
2375 u64 pcnt : 1;
2376 u64 iob2big : 1;
2377 u64 bar0_to : 1;
2378 u64 reserved_1_1 : 1;
2379 u64 rml_to : 1;
2380 } cn68xx;
2381 struct cvmx_sli_int_enb_portx_cn68xx cn68xxp1;
2382 struct cvmx_sli_int_enb_portx_cn70xx {
2383 u64 reserved_63_61 : 3;
2384 u64 ill_pad : 1;
2385 u64 sprt3_err : 1;
2386 u64 sprt2_err : 1;
2387 u64 sprt1_err : 1;
2388 u64 sprt0_err : 1;
2389 u64 pins_err : 1;
2390 u64 pop_err : 1;
2391 u64 pdi_err : 1;
2392 u64 pgl_err : 1;
2393 u64 pin_bp : 1;
2394 u64 pout_err : 1;
2395 u64 psldbof : 1;
2396 u64 pidbof : 1;
2397 u64 reserved_47_38 : 10;
2398 u64 dtime : 2;
2399 u64 dcnt : 2;
2400 u64 dmafi : 2;
2401 u64 reserved_31_30 : 2;
2402 u64 mac2_int : 1;
2403 u64 mio_int2 : 1;
2404 u64 m3_un_wi : 1;
2405 u64 m3_un_b0 : 1;
2406 u64 m3_up_wi : 1;
2407 u64 m3_up_b0 : 1;
2408 u64 m2_un_wi : 1;
2409 u64 m2_un_b0 : 1;
2410 u64 m2_up_wi : 1;
2411 u64 m2_up_b0 : 1;
2412 u64 mac1_int : 1;
2413 u64 mac0_int : 1;
2414 u64 mio_int1 : 1;
2415 u64 mio_int0 : 1;
2416 u64 m1_un_wi : 1;
2417 u64 m1_un_b0 : 1;
2418 u64 m1_up_wi : 1;
2419 u64 m1_up_b0 : 1;
2420 u64 m0_un_wi : 1;
2421 u64 m0_un_b0 : 1;
2422 u64 m0_up_wi : 1;
2423 u64 m0_up_b0 : 1;
2424 u64 reserved_7_6 : 2;
2425 u64 ptime : 1;
2426 u64 pcnt : 1;
2427 u64 iob2big : 1;
2428 u64 bar0_to : 1;
2429 u64 reserved_1_1 : 1;
2430 u64 rml_to : 1;
2431 } cn70xx;
2432 struct cvmx_sli_int_enb_portx_cn70xx cn70xxp1;
2433 struct cvmx_sli_int_enb_portx_cn78xxp1 {
2434 u64 reserved_60_63 : 4;
2435 u64 sprt3_err : 1;
2436 u64 sprt2_err : 1;
2437 u64 sprt1_err : 1;
2438 u64 sprt0_err : 1;
2439 u64 pins_err : 1;
2440 u64 pop_err : 1;
2441 u64 pdi_err : 1;
2442 u64 pgl_err : 1;
2443 u64 reserved_50_51 : 2;
2444 u64 psldbof : 1;
2445 u64 pidbof : 1;
2446 u64 reserved_38_47 : 10;
2447 u64 dtime : 2;
2448 u64 dcnt : 2;
2449 u64 dmafi : 2;
2450 u64 reserved_29_31 : 3;
2451 u64 vf_err : 1;
2452 u64 m3_un_wi : 1;
2453 u64 m3_un_b0 : 1;
2454 u64 m3_up_wi : 1;
2455 u64 m3_up_b0 : 1;
2456 u64 m2_un_wi : 1;
2457 u64 m2_un_b0 : 1;
2458 u64 m2_up_wi : 1;
2459 u64 m2_up_b0 : 1;
2460 u64 reserved_18_19 : 2;
2461 u64 mio_int1 : 1;
2462 u64 mio_int0 : 1;
2463 u64 m1_un_wi : 1;
2464 u64 m1_un_b0 : 1;
2465 u64 m1_up_wi : 1;
2466 u64 m1_up_b0 : 1;
2467 u64 m0_un_wi : 1;
2468 u64 m0_un_b0 : 1;
2469 u64 m0_up_wi : 1;
2470 u64 m0_up_b0 : 1;
2471 u64 mio_int3 : 1;
2472 u64 mio_int2 : 1;
2473 u64 ptime : 1;
2474 u64 pcnt : 1;
2475 u64 reserved_1_3 : 3;
2476 u64 rml_to : 1;
2477 } cn78xxp1;
2478 struct cvmx_sli_int_enb_portx_cn61xx cnf71xx;
2479};
2480
2481typedef union cvmx_sli_int_enb_portx cvmx_sli_int_enb_portx_t;
2482
2483/**
2484 * cvmx_sli_int_sum
2485 *
2486 * The fields in this register are set when an interrupt condition occurs; write 1 to clear. All
2487 * fields of the register are valid when a PF reads the register. Not available to VFs, and
2488 * writes by the
2489 * VF do not modify the register.
2490 */
2491union cvmx_sli_int_sum {
2492 u64 u64;
2493 struct cvmx_sli_int_sum_s {
2494 u64 reserved_62_63 : 2;
2495 u64 pipe_err : 1;
2496 u64 ill_pad : 1;
2497 u64 sprt3_err : 1;
2498 u64 sprt2_err : 1;
2499 u64 sprt1_err : 1;
2500 u64 sprt0_err : 1;
2501 u64 pins_err : 1;
2502 u64 pop_err : 1;
2503 u64 pdi_err : 1;
2504 u64 pgl_err : 1;
2505 u64 pin_bp : 1;
2506 u64 pout_err : 1;
2507 u64 psldbof : 1;
2508 u64 pidbof : 1;
2509 u64 reserved_38_47 : 10;
2510 u64 dtime : 2;
2511 u64 dcnt : 2;
2512 u64 dmafi : 2;
2513 u64 reserved_30_31 : 2;
2514 u64 mac2_int : 1;
2515 u64 reserved_28_28 : 1;
2516 u64 m3_un_wi : 1;
2517 u64 m3_un_b0 : 1;
2518 u64 m3_up_wi : 1;
2519 u64 m3_up_b0 : 1;
2520 u64 m2_un_wi : 1;
2521 u64 m2_un_b0 : 1;
2522 u64 m2_up_wi : 1;
2523 u64 m2_up_b0 : 1;
2524 u64 mac1_int : 1;
2525 u64 mac0_int : 1;
2526 u64 mio_int1 : 1;
2527 u64 mio_int0 : 1;
2528 u64 m1_un_wi : 1;
2529 u64 m1_un_b0 : 1;
2530 u64 m1_up_wi : 1;
2531 u64 m1_up_b0 : 1;
2532 u64 m0_un_wi : 1;
2533 u64 m0_un_b0 : 1;
2534 u64 m0_up_wi : 1;
2535 u64 m0_up_b0 : 1;
2536 u64 mio_int3 : 1;
2537 u64 reserved_6_6 : 1;
2538 u64 ptime : 1;
2539 u64 pcnt : 1;
2540 u64 iob2big : 1;
2541 u64 bar0_to : 1;
2542 u64 reserved_1_1 : 1;
2543 u64 rml_to : 1;
2544 } s;
2545 struct cvmx_sli_int_sum_cn61xx {
2546 u64 reserved_61_63 : 3;
2547 u64 ill_pad : 1;
2548 u64 sprt3_err : 1;
2549 u64 sprt2_err : 1;
2550 u64 sprt1_err : 1;
2551 u64 sprt0_err : 1;
2552 u64 pins_err : 1;
2553 u64 pop_err : 1;
2554 u64 pdi_err : 1;
2555 u64 pgl_err : 1;
2556 u64 pin_bp : 1;
2557 u64 pout_err : 1;
2558 u64 psldbof : 1;
2559 u64 pidbof : 1;
2560 u64 reserved_38_47 : 10;
2561 u64 dtime : 2;
2562 u64 dcnt : 2;
2563 u64 dmafi : 2;
2564 u64 reserved_28_31 : 4;
2565 u64 m3_un_wi : 1;
2566 u64 m3_un_b0 : 1;
2567 u64 m3_up_wi : 1;
2568 u64 m3_up_b0 : 1;
2569 u64 m2_un_wi : 1;
2570 u64 m2_un_b0 : 1;
2571 u64 m2_up_wi : 1;
2572 u64 m2_up_b0 : 1;
2573 u64 mac1_int : 1;
2574 u64 mac0_int : 1;
2575 u64 mio_int1 : 1;
2576 u64 mio_int0 : 1;
2577 u64 m1_un_wi : 1;
2578 u64 m1_un_b0 : 1;
2579 u64 m1_up_wi : 1;
2580 u64 m1_up_b0 : 1;
2581 u64 m0_un_wi : 1;
2582 u64 m0_un_b0 : 1;
2583 u64 m0_up_wi : 1;
2584 u64 m0_up_b0 : 1;
2585 u64 reserved_6_7 : 2;
2586 u64 ptime : 1;
2587 u64 pcnt : 1;
2588 u64 iob2big : 1;
2589 u64 bar0_to : 1;
2590 u64 reserved_1_1 : 1;
2591 u64 rml_to : 1;
2592 } cn61xx;
2593 struct cvmx_sli_int_sum_cn63xx {
2594 u64 reserved_61_63 : 3;
2595 u64 ill_pad : 1;
2596 u64 reserved_58_59 : 2;
2597 u64 sprt1_err : 1;
2598 u64 sprt0_err : 1;
2599 u64 pins_err : 1;
2600 u64 pop_err : 1;
2601 u64 pdi_err : 1;
2602 u64 pgl_err : 1;
2603 u64 pin_bp : 1;
2604 u64 pout_err : 1;
2605 u64 psldbof : 1;
2606 u64 pidbof : 1;
2607 u64 reserved_38_47 : 10;
2608 u64 dtime : 2;
2609 u64 dcnt : 2;
2610 u64 dmafi : 2;
2611 u64 reserved_20_31 : 12;
2612 u64 mac1_int : 1;
2613 u64 mac0_int : 1;
2614 u64 mio_int1 : 1;
2615 u64 mio_int0 : 1;
2616 u64 m1_un_wi : 1;
2617 u64 m1_un_b0 : 1;
2618 u64 m1_up_wi : 1;
2619 u64 m1_up_b0 : 1;
2620 u64 m0_un_wi : 1;
2621 u64 m0_un_b0 : 1;
2622 u64 m0_up_wi : 1;
2623 u64 m0_up_b0 : 1;
2624 u64 reserved_6_7 : 2;
2625 u64 ptime : 1;
2626 u64 pcnt : 1;
2627 u64 iob2big : 1;
2628 u64 bar0_to : 1;
2629 u64 reserved_1_1 : 1;
2630 u64 rml_to : 1;
2631 } cn63xx;
2632 struct cvmx_sli_int_sum_cn63xx cn63xxp1;
2633 struct cvmx_sli_int_sum_cn61xx cn66xx;
2634 struct cvmx_sli_int_sum_cn68xx {
2635 u64 reserved_62_63 : 2;
2636 u64 pipe_err : 1;
2637 u64 ill_pad : 1;
2638 u64 reserved_58_59 : 2;
2639 u64 sprt1_err : 1;
2640 u64 sprt0_err : 1;
2641 u64 pins_err : 1;
2642 u64 pop_err : 1;
2643 u64 pdi_err : 1;
2644 u64 pgl_err : 1;
2645 u64 reserved_51_51 : 1;
2646 u64 pout_err : 1;
2647 u64 psldbof : 1;
2648 u64 pidbof : 1;
2649 u64 reserved_38_47 : 10;
2650 u64 dtime : 2;
2651 u64 dcnt : 2;
2652 u64 dmafi : 2;
2653 u64 reserved_20_31 : 12;
2654 u64 mac1_int : 1;
2655 u64 mac0_int : 1;
2656 u64 mio_int1 : 1;
2657 u64 mio_int0 : 1;
2658 u64 m1_un_wi : 1;
2659 u64 m1_un_b0 : 1;
2660 u64 m1_up_wi : 1;
2661 u64 m1_up_b0 : 1;
2662 u64 m0_un_wi : 1;
2663 u64 m0_un_b0 : 1;
2664 u64 m0_up_wi : 1;
2665 u64 m0_up_b0 : 1;
2666 u64 reserved_6_7 : 2;
2667 u64 ptime : 1;
2668 u64 pcnt : 1;
2669 u64 iob2big : 1;
2670 u64 bar0_to : 1;
2671 u64 reserved_1_1 : 1;
2672 u64 rml_to : 1;
2673 } cn68xx;
2674 struct cvmx_sli_int_sum_cn68xx cn68xxp1;
2675 struct cvmx_sli_int_sum_cn70xx {
2676 u64 reserved_61_63 : 3;
2677 u64 ill_pad : 1;
2678 u64 sprt3_err : 1;
2679 u64 sprt2_err : 1;
2680 u64 sprt1_err : 1;
2681 u64 sprt0_err : 1;
2682 u64 pins_err : 1;
2683 u64 pop_err : 1;
2684 u64 pdi_err : 1;
2685 u64 pgl_err : 1;
2686 u64 pin_bp : 1;
2687 u64 pout_err : 1;
2688 u64 psldbof : 1;
2689 u64 pidbof : 1;
2690 u64 reserved_38_47 : 10;
2691 u64 dtime : 2;
2692 u64 dcnt : 2;
2693 u64 dmafi : 2;
2694 u64 reserved_30_31 : 2;
2695 u64 mac2_int : 1;
2696 u64 mio_int2 : 1;
2697 u64 m3_un_wi : 1;
2698 u64 m3_un_b0 : 1;
2699 u64 m3_up_wi : 1;
2700 u64 m3_up_b0 : 1;
2701 u64 m2_un_wi : 1;
2702 u64 m2_un_b0 : 1;
2703 u64 m2_up_wi : 1;
2704 u64 m2_up_b0 : 1;
2705 u64 mac1_int : 1;
2706 u64 mac0_int : 1;
2707 u64 mio_int1 : 1;
2708 u64 mio_int0 : 1;
2709 u64 m1_un_wi : 1;
2710 u64 m1_un_b0 : 1;
2711 u64 m1_up_wi : 1;
2712 u64 m1_up_b0 : 1;
2713 u64 m0_un_wi : 1;
2714 u64 m0_un_b0 : 1;
2715 u64 m0_up_wi : 1;
2716 u64 m0_up_b0 : 1;
2717 u64 reserved_6_7 : 2;
2718 u64 ptime : 1;
2719 u64 pcnt : 1;
2720 u64 iob2big : 1;
2721 u64 bar0_to : 1;
2722 u64 reserved_1_1 : 1;
2723 u64 rml_to : 1;
2724 } cn70xx;
2725 struct cvmx_sli_int_sum_cn70xx cn70xxp1;
2726 struct cvmx_sli_int_sum_cn78xxp1 {
2727 u64 reserved_60_63 : 4;
2728 u64 sprt3_err : 1;
2729 u64 sprt2_err : 1;
2730 u64 sprt1_err : 1;
2731 u64 sprt0_err : 1;
2732 u64 pins_err : 1;
2733 u64 pop_err : 1;
2734 u64 pdi_err : 1;
2735 u64 pgl_err : 1;
2736 u64 reserved_50_51 : 2;
2737 u64 psldbof : 1;
2738 u64 pidbof : 1;
2739 u64 reserved_38_47 : 10;
2740 u64 dtime : 2;
2741 u64 dcnt : 2;
2742 u64 dmafi : 2;
2743 u64 reserved_29_31 : 3;
2744 u64 vf_err : 1;
2745 u64 m3_un_wi : 1;
2746 u64 m3_un_b0 : 1;
2747 u64 m3_up_wi : 1;
2748 u64 m3_up_b0 : 1;
2749 u64 m2_un_wi : 1;
2750 u64 m2_un_b0 : 1;
2751 u64 m2_up_wi : 1;
2752 u64 m2_up_b0 : 1;
2753 u64 reserved_18_19 : 2;
2754 u64 mio_int1 : 1;
2755 u64 mio_int0 : 1;
2756 u64 m1_un_wi : 1;
2757 u64 m1_un_b0 : 1;
2758 u64 m1_up_wi : 1;
2759 u64 m1_up_b0 : 1;
2760 u64 m0_un_wi : 1;
2761 u64 m0_un_b0 : 1;
2762 u64 m0_up_wi : 1;
2763 u64 m0_up_b0 : 1;
2764 u64 mio_int3 : 1;
2765 u64 mio_int2 : 1;
2766 u64 ptime : 1;
2767 u64 pcnt : 1;
2768 u64 reserved_1_3 : 3;
2769 u64 rml_to : 1;
2770 } cn78xxp1;
2771 struct cvmx_sli_int_sum_cn61xx cnf71xx;
2772};
2773
2774typedef union cvmx_sli_int_sum cvmx_sli_int_sum_t;
2775
2776/**
2777 * cvmx_sli_last_win_rdata0
2778 *
2779 * The data from the last initiated window read by MAC 0.
2780 *
2781 */
2782union cvmx_sli_last_win_rdata0 {
2783 u64 u64;
2784 struct cvmx_sli_last_win_rdata0_s {
2785 u64 data : 64;
2786 } s;
2787 struct cvmx_sli_last_win_rdata0_s cn61xx;
2788 struct cvmx_sli_last_win_rdata0_s cn63xx;
2789 struct cvmx_sli_last_win_rdata0_s cn63xxp1;
2790 struct cvmx_sli_last_win_rdata0_s cn66xx;
2791 struct cvmx_sli_last_win_rdata0_s cn68xx;
2792 struct cvmx_sli_last_win_rdata0_s cn68xxp1;
2793 struct cvmx_sli_last_win_rdata0_s cn70xx;
2794 struct cvmx_sli_last_win_rdata0_s cn70xxp1;
2795 struct cvmx_sli_last_win_rdata0_s cnf71xx;
2796};
2797
2798typedef union cvmx_sli_last_win_rdata0 cvmx_sli_last_win_rdata0_t;
2799
2800/**
2801 * cvmx_sli_last_win_rdata1
2802 *
2803 * The data from the last initiated window read by MAC 1.
2804 *
2805 */
2806union cvmx_sli_last_win_rdata1 {
2807 u64 u64;
2808 struct cvmx_sli_last_win_rdata1_s {
2809 u64 data : 64;
2810 } s;
2811 struct cvmx_sli_last_win_rdata1_s cn61xx;
2812 struct cvmx_sli_last_win_rdata1_s cn63xx;
2813 struct cvmx_sli_last_win_rdata1_s cn63xxp1;
2814 struct cvmx_sli_last_win_rdata1_s cn66xx;
2815 struct cvmx_sli_last_win_rdata1_s cn68xx;
2816 struct cvmx_sli_last_win_rdata1_s cn68xxp1;
2817 struct cvmx_sli_last_win_rdata1_s cn70xx;
2818 struct cvmx_sli_last_win_rdata1_s cn70xxp1;
2819 struct cvmx_sli_last_win_rdata1_s cnf71xx;
2820};
2821
2822typedef union cvmx_sli_last_win_rdata1 cvmx_sli_last_win_rdata1_t;
2823
2824/**
2825 * cvmx_sli_last_win_rdata2
2826 *
2827 * The data from the last initiated window read by MAC 2.
2828 *
2829 */
2830union cvmx_sli_last_win_rdata2 {
2831 u64 u64;
2832 struct cvmx_sli_last_win_rdata2_s {
2833 u64 data : 64;
2834 } s;
2835 struct cvmx_sli_last_win_rdata2_s cn61xx;
2836 struct cvmx_sli_last_win_rdata2_s cn66xx;
2837 struct cvmx_sli_last_win_rdata2_s cn70xx;
2838 struct cvmx_sli_last_win_rdata2_s cn70xxp1;
2839 struct cvmx_sli_last_win_rdata2_s cnf71xx;
2840};
2841
2842typedef union cvmx_sli_last_win_rdata2 cvmx_sli_last_win_rdata2_t;
2843
2844/**
2845 * cvmx_sli_last_win_rdata3
2846 *
2847 * The data from the last initiated window read by MAC 3.
2848 *
2849 */
2850union cvmx_sli_last_win_rdata3 {
2851 u64 u64;
2852 struct cvmx_sli_last_win_rdata3_s {
2853 u64 data : 64;
2854 } s;
2855 struct cvmx_sli_last_win_rdata3_s cn61xx;
2856 struct cvmx_sli_last_win_rdata3_s cn66xx;
2857 struct cvmx_sli_last_win_rdata3_s cn70xx;
2858 struct cvmx_sli_last_win_rdata3_s cn70xxp1;
2859 struct cvmx_sli_last_win_rdata3_s cnf71xx;
2860};
2861
2862typedef union cvmx_sli_last_win_rdata3 cvmx_sli_last_win_rdata3_t;
2863
2864/**
2865 * cvmx_sli_mac#_pf#_dma_vf_int
2866 *
2867 * When an error response is received for a VF DMA transaction read, the appropriate VF indexed
2868 * bit is set. The appropriate PF should read the appropriate register.
2869 * Indexed by (MAC index) SLI_PORT_E.
2870 * This CSR array is valid only for SLI_PORT_E::PEM0 PF0.
2871 */
2872union cvmx_sli_macx_pfx_dma_vf_int {
2873 u64 u64;
2874 struct cvmx_sli_macx_pfx_dma_vf_int_s {
2875 u64 vf_int : 64;
2876 } s;
2877 struct cvmx_sli_macx_pfx_dma_vf_int_s cn73xx;
2878 struct cvmx_sli_macx_pfx_dma_vf_int_s cn78xx;
2879 struct cvmx_sli_macx_pfx_dma_vf_int_s cnf75xx;
2880};
2881
2882typedef union cvmx_sli_macx_pfx_dma_vf_int cvmx_sli_macx_pfx_dma_vf_int_t;
2883
2884/**
2885 * cvmx_sli_mac#_pf#_dma_vf_int_enb
2886 *
2887 * Indexed by (MAC index) SLI_PORT_E.
2888 * This CSR array is valid only for SLI_PORT_E::PEM0 PF0.
2889 */
2890union cvmx_sli_macx_pfx_dma_vf_int_enb {
2891 u64 u64;
2892 struct cvmx_sli_macx_pfx_dma_vf_int_enb_s {
2893 u64 vf_int_enb : 64;
2894 } s;
2895 struct cvmx_sli_macx_pfx_dma_vf_int_enb_s cn73xx;
2896 struct cvmx_sli_macx_pfx_dma_vf_int_enb_s cn78xx;
2897 struct cvmx_sli_macx_pfx_dma_vf_int_enb_s cnf75xx;
2898};
2899
2900typedef union cvmx_sli_macx_pfx_dma_vf_int_enb cvmx_sli_macx_pfx_dma_vf_int_enb_t;
2901
2902/**
2903 * cvmx_sli_mac#_pf#_flr_vf_int
2904 *
2905 * Indexed by (MAC index) SLI_PORT_E.
2906 * This CSR array is valid only for SLI_PORT_E::PEM0 PF0.
2907 */
2908union cvmx_sli_macx_pfx_flr_vf_int {
2909 u64 u64;
2910 struct cvmx_sli_macx_pfx_flr_vf_int_s {
2911 u64 vf_int : 64;
2912 } s;
2913 struct cvmx_sli_macx_pfx_flr_vf_int_s cn73xx;
2914 struct cvmx_sli_macx_pfx_flr_vf_int_s cn78xx;
2915 struct cvmx_sli_macx_pfx_flr_vf_int_s cnf75xx;
2916};
2917
2918typedef union cvmx_sli_macx_pfx_flr_vf_int cvmx_sli_macx_pfx_flr_vf_int_t;
2919
2920/**
2921 * cvmx_sli_mac#_pf#_int_enb
2922 *
2923 * Interrupt enable register for a given PF SLI_MAC()_PF()_INT_SUM register.
2924 * Indexed by (MAC index) SLI_PORT_E.
2925 */
2926union cvmx_sli_macx_pfx_int_enb {
2927 u64 u64;
2928 struct cvmx_sli_macx_pfx_int_enb_s {
2929 u64 pppf_err : 1;
2930 u64 ppvf_err : 1;
2931 u64 pktpf_err : 1;
2932 u64 pktvf_err : 1;
2933 u64 dmapf_err : 1;
2934 u64 dmavf_err : 1;
2935 u64 vf_mbox : 1;
2936 u64 reserved_38_56 : 19;
2937 u64 dtime : 2;
2938 u64 dcnt : 2;
2939 u64 dmafi : 2;
2940 u64 reserved_12_31 : 20;
2941 u64 un_wi : 1;
2942 u64 un_b0 : 1;
2943 u64 up_wi : 1;
2944 u64 up_b0 : 1;
2945 u64 reserved_6_7 : 2;
2946 u64 ptime : 1;
2947 u64 pcnt : 1;
2948 u64 reserved_2_3 : 2;
2949 u64 mio_int : 1;
2950 u64 rml_to : 1;
2951 } s;
2952 struct cvmx_sli_macx_pfx_int_enb_s cn73xx;
2953 struct cvmx_sli_macx_pfx_int_enb_s cn78xx;
2954 struct cvmx_sli_macx_pfx_int_enb_s cnf75xx;
2955};
2956
2957typedef union cvmx_sli_macx_pfx_int_enb cvmx_sli_macx_pfx_int_enb_t;
2958
2959/**
2960 * cvmx_sli_mac#_pf#_int_sum
2961 *
2962 * Interrupt summary register for a given PF. Indexed (MAC index) by SLI_PORT_E.
2963 * The fields in this register are set when an interrupt condition occurs; write 1 to clear.
2964 */
2965union cvmx_sli_macx_pfx_int_sum {
2966 u64 u64;
2967 struct cvmx_sli_macx_pfx_int_sum_s {
2968 u64 pppf_err : 1;
2969 u64 ppvf_err : 1;
2970 u64 pktpf_err : 1;
2971 u64 pktvf_err : 1;
2972 u64 dmapf_err : 1;
2973 u64 dmavf_err : 1;
2974 u64 vf_mbox : 1;
2975 u64 reserved_38_56 : 19;
2976 u64 dtime : 2;
2977 u64 dcnt : 2;
2978 u64 dmafi : 2;
2979 u64 reserved_12_31 : 20;
2980 u64 un_wi : 1;
2981 u64 un_b0 : 1;
2982 u64 up_wi : 1;
2983 u64 up_b0 : 1;
2984 u64 reserved_6_7 : 2;
2985 u64 ptime : 1;
2986 u64 pcnt : 1;
2987 u64 reserved_2_3 : 2;
2988 u64 mio_int : 1;
2989 u64 rml_to : 1;
2990 } s;
2991 struct cvmx_sli_macx_pfx_int_sum_s cn73xx;
2992 struct cvmx_sli_macx_pfx_int_sum_s cn78xx;
2993 struct cvmx_sli_macx_pfx_int_sum_s cnf75xx;
2994};
2995
2996typedef union cvmx_sli_macx_pfx_int_sum cvmx_sli_macx_pfx_int_sum_t;
2997
2998/**
2999 * cvmx_sli_mac#_pf#_mbox_int
3000 *
3001 * When a VF to PF MBOX write occurs the appropriate bit is set.
3002 * Indexed by (MAC index) SLI_PORT_E.
3003 * This CSR array is valid only for SLI_PORT_E::PEM0 PF0.
3004 */
3005union cvmx_sli_macx_pfx_mbox_int {
3006 u64 u64;
3007 struct cvmx_sli_macx_pfx_mbox_int_s {
3008 u64 vf_int : 64;
3009 } s;
3010 struct cvmx_sli_macx_pfx_mbox_int_s cn73xx;
3011 struct cvmx_sli_macx_pfx_mbox_int_s cn78xx;
3012 struct cvmx_sli_macx_pfx_mbox_int_s cnf75xx;
3013};
3014
3015typedef union cvmx_sli_macx_pfx_mbox_int cvmx_sli_macx_pfx_mbox_int_t;
3016
3017/**
3018 * cvmx_sli_mac#_pf#_pkt_vf_int
3019 *
3020 * When an error response is received for a VF PP transaction read, a doorbell
3021 * overflow for a ring associated with a VF occurs or an illegal memory access from a VF occurs,
3022 * the appropriate VF indexed bit is set. The appropriate PF should read the appropriate
3023 * register.
3024 * Indexed by (MAC index) SLI_PORT_E.
3025 * This CSR array is valid only for SLI_PORT_E::PEM0 PF0.
3026 */
3027union cvmx_sli_macx_pfx_pkt_vf_int {
3028 u64 u64;
3029 struct cvmx_sli_macx_pfx_pkt_vf_int_s {
3030 u64 vf_int : 64;
3031 } s;
3032 struct cvmx_sli_macx_pfx_pkt_vf_int_s cn73xx;
3033 struct cvmx_sli_macx_pfx_pkt_vf_int_s cn78xx;
3034 struct cvmx_sli_macx_pfx_pkt_vf_int_s cnf75xx;
3035};
3036
3037typedef union cvmx_sli_macx_pfx_pkt_vf_int cvmx_sli_macx_pfx_pkt_vf_int_t;
3038
3039/**
3040 * cvmx_sli_mac#_pf#_pkt_vf_int_enb
3041 *
3042 * Indexed by (MAC index) SLI_PORT_E.
3043 * This CSR array is valid only for SLI_PORT_E::PEM0 PF0.
3044 */
3045union cvmx_sli_macx_pfx_pkt_vf_int_enb {
3046 u64 u64;
3047 struct cvmx_sli_macx_pfx_pkt_vf_int_enb_s {
3048 u64 vf_int_enb : 64;
3049 } s;
3050 struct cvmx_sli_macx_pfx_pkt_vf_int_enb_s cn73xx;
3051 struct cvmx_sli_macx_pfx_pkt_vf_int_enb_s cn78xx;
3052 struct cvmx_sli_macx_pfx_pkt_vf_int_enb_s cnf75xx;
3053};
3054
3055typedef union cvmx_sli_macx_pfx_pkt_vf_int_enb cvmx_sli_macx_pfx_pkt_vf_int_enb_t;
3056
3057/**
3058 * cvmx_sli_mac#_pf#_pp_vf_int
3059 *
3060 * When an error response is received for a VF PP transaction read, the appropriate VF indexed
3061 * bit is set. The appropriate PF should read the appropriate register.
3062 * Indexed by (MAC index) SLI_PORT_E.
3063 * This CSR array is valid only for SLI_PORT_E::PEM0 PF0.
3064 */
3065union cvmx_sli_macx_pfx_pp_vf_int {
3066 u64 u64;
3067 struct cvmx_sli_macx_pfx_pp_vf_int_s {
3068 u64 vf_int : 64;
3069 } s;
3070 struct cvmx_sli_macx_pfx_pp_vf_int_s cn73xx;
3071 struct cvmx_sli_macx_pfx_pp_vf_int_s cn78xx;
3072 struct cvmx_sli_macx_pfx_pp_vf_int_s cnf75xx;
3073};
3074
3075typedef union cvmx_sli_macx_pfx_pp_vf_int cvmx_sli_macx_pfx_pp_vf_int_t;
3076
3077/**
3078 * cvmx_sli_mac#_pf#_pp_vf_int_enb
3079 *
3080 * Indexed by (MAC index) SLI_PORT_E.
3081 * This CSR array is valid only for SLI_PORT_E::PEM0 PF0.
3082 */
3083union cvmx_sli_macx_pfx_pp_vf_int_enb {
3084 u64 u64;
3085 struct cvmx_sli_macx_pfx_pp_vf_int_enb_s {
3086 u64 vf_int_enb : 64;
3087 } s;
3088 struct cvmx_sli_macx_pfx_pp_vf_int_enb_s cn73xx;
3089 struct cvmx_sli_macx_pfx_pp_vf_int_enb_s cn78xx;
3090 struct cvmx_sli_macx_pfx_pp_vf_int_enb_s cnf75xx;
3091};
3092
3093typedef union cvmx_sli_macx_pfx_pp_vf_int_enb cvmx_sli_macx_pfx_pp_vf_int_enb_t;
3094
3095/**
3096 * cvmx_sli_mac_credit_cnt
3097 *
3098 * This register contains the number of credits for the MAC port FIFOs used by the SLI. This
3099 * value needs to be set before S2M traffic flow starts. A write operation to this register
3100 * causes the credit counts in the SLI for the MAC ports to be reset to the value in this
3101 * register if the corresponding disable bit in this register is set to 0.
3102 */
3103union cvmx_sli_mac_credit_cnt {
3104 u64 u64;
3105 struct cvmx_sli_mac_credit_cnt_s {
3106 u64 reserved_54_63 : 10;
3107 u64 p1_c_d : 1;
3108 u64 p1_n_d : 1;
3109 u64 p1_p_d : 1;
3110 u64 p0_c_d : 1;
3111 u64 p0_n_d : 1;
3112 u64 p0_p_d : 1;
3113 u64 p1_ccnt : 8;
3114 u64 p1_ncnt : 8;
3115 u64 p1_pcnt : 8;
3116 u64 p0_ccnt : 8;
3117 u64 p0_ncnt : 8;
3118 u64 p0_pcnt : 8;
3119 } s;
3120 struct cvmx_sli_mac_credit_cnt_s cn61xx;
3121 struct cvmx_sli_mac_credit_cnt_s cn63xx;
3122 struct cvmx_sli_mac_credit_cnt_cn63xxp1 {
3123 u64 reserved_48_63 : 16;
3124 u64 p1_ccnt : 8;
3125 u64 p1_ncnt : 8;
3126 u64 p1_pcnt : 8;
3127 u64 p0_ccnt : 8;
3128 u64 p0_ncnt : 8;
3129 u64 p0_pcnt : 8;
3130 } cn63xxp1;
3131 struct cvmx_sli_mac_credit_cnt_s cn66xx;
3132 struct cvmx_sli_mac_credit_cnt_s cn68xx;
3133 struct cvmx_sli_mac_credit_cnt_s cn68xxp1;
3134 struct cvmx_sli_mac_credit_cnt_s cn70xx;
3135 struct cvmx_sli_mac_credit_cnt_s cn70xxp1;
3136 struct cvmx_sli_mac_credit_cnt_s cn73xx;
3137 struct cvmx_sli_mac_credit_cnt_s cn78xx;
3138 struct cvmx_sli_mac_credit_cnt_s cn78xxp1;
3139 struct cvmx_sli_mac_credit_cnt_s cnf71xx;
3140 struct cvmx_sli_mac_credit_cnt_s cnf75xx;
3141};
3142
3143typedef union cvmx_sli_mac_credit_cnt cvmx_sli_mac_credit_cnt_t;
3144
3145/**
3146 * cvmx_sli_mac_credit_cnt2
3147 *
3148 * This register contains the number of credits for the MAC port FIFOs (for MACs 2 and 3) used by
3149 * the SLI. This value must be set before S2M traffic flow starts. A write to this register
3150 * causes the credit counts in the SLI for the MAC ports to be reset to the value in this
3151 * register.
3152 */
3153union cvmx_sli_mac_credit_cnt2 {
3154 u64 u64;
3155 struct cvmx_sli_mac_credit_cnt2_s {
3156 u64 reserved_54_63 : 10;
3157 u64 p3_c_d : 1;
3158 u64 p3_n_d : 1;
3159 u64 p3_p_d : 1;
3160 u64 p2_c_d : 1;
3161 u64 p2_n_d : 1;
3162 u64 p2_p_d : 1;
3163 u64 p3_ccnt : 8;
3164 u64 p3_ncnt : 8;
3165 u64 p3_pcnt : 8;
3166 u64 p2_ccnt : 8;
3167 u64 p2_ncnt : 8;
3168 u64 p2_pcnt : 8;
3169 } s;
3170 struct cvmx_sli_mac_credit_cnt2_s cn61xx;
3171 struct cvmx_sli_mac_credit_cnt2_s cn66xx;
3172 struct cvmx_sli_mac_credit_cnt2_s cn70xx;
3173 struct cvmx_sli_mac_credit_cnt2_s cn70xxp1;
3174 struct cvmx_sli_mac_credit_cnt2_s cn73xx;
3175 struct cvmx_sli_mac_credit_cnt2_s cn78xx;
3176 struct cvmx_sli_mac_credit_cnt2_s cn78xxp1;
3177 struct cvmx_sli_mac_credit_cnt2_s cnf71xx;
3178 struct cvmx_sli_mac_credit_cnt2_s cnf75xx;
3179};
3180
3181typedef union cvmx_sli_mac_credit_cnt2 cvmx_sli_mac_credit_cnt2_t;
3182
3183/**
3184 * cvmx_sli_mac_number
3185 *
3186 * When read from a MAC port, this register returns the MAC's port number, otherwise returns zero.
3187 *
3188 */
3189union cvmx_sli_mac_number {
3190 u64 u64;
3191 struct cvmx_sli_mac_number_s {
3192 u64 reserved_9_63 : 55;
3193 u64 a_mode : 1;
3194 u64 num : 8;
3195 } s;
3196 struct cvmx_sli_mac_number_s cn61xx;
3197 struct cvmx_sli_mac_number_cn63xx {
3198 u64 reserved_8_63 : 56;
3199 u64 num : 8;
3200 } cn63xx;
3201 struct cvmx_sli_mac_number_s cn66xx;
3202 struct cvmx_sli_mac_number_cn63xx cn68xx;
3203 struct cvmx_sli_mac_number_cn63xx cn68xxp1;
3204 struct cvmx_sli_mac_number_s cn70xx;
3205 struct cvmx_sli_mac_number_s cn70xxp1;
3206 struct cvmx_sli_mac_number_s cn73xx;
3207 struct cvmx_sli_mac_number_s cn78xx;
3208 struct cvmx_sli_mac_number_s cn78xxp1;
3209 struct cvmx_sli_mac_number_s cnf71xx;
3210 struct cvmx_sli_mac_number_s cnf75xx;
3211};
3212
3213typedef union cvmx_sli_mac_number cvmx_sli_mac_number_t;
3214
3215/**
3216 * cvmx_sli_mem_access_ctl
3217 *
3218 * This register contains control signals for access to the MAC address space.
3219 *
3220 */
3221union cvmx_sli_mem_access_ctl {
3222 u64 u64;
3223 struct cvmx_sli_mem_access_ctl_s {
3224 u64 reserved_14_63 : 50;
3225 u64 max_word : 4;
3226 u64 timer : 10;
3227 } s;
3228 struct cvmx_sli_mem_access_ctl_s cn61xx;
3229 struct cvmx_sli_mem_access_ctl_s cn63xx;
3230 struct cvmx_sli_mem_access_ctl_s cn63xxp1;
3231 struct cvmx_sli_mem_access_ctl_s cn66xx;
3232 struct cvmx_sli_mem_access_ctl_s cn68xx;
3233 struct cvmx_sli_mem_access_ctl_s cn68xxp1;
3234 struct cvmx_sli_mem_access_ctl_s cn70xx;
3235 struct cvmx_sli_mem_access_ctl_s cn70xxp1;
3236 struct cvmx_sli_mem_access_ctl_s cn73xx;
3237 struct cvmx_sli_mem_access_ctl_s cn78xx;
3238 struct cvmx_sli_mem_access_ctl_s cn78xxp1;
3239 struct cvmx_sli_mem_access_ctl_s cnf71xx;
3240 struct cvmx_sli_mem_access_ctl_s cnf75xx;
3241};
3242
3243typedef union cvmx_sli_mem_access_ctl cvmx_sli_mem_access_ctl_t;
3244
3245/**
3246 * cvmx_sli_mem_access_subid#
3247 *
3248 * These registers contains address index and control bits for access to memory from cores.
3249 *
3250 */
3251union cvmx_sli_mem_access_subidx {
3252 u64 u64;
3253 struct cvmx_sli_mem_access_subidx_s {
3254 u64 reserved_60_63 : 4;
3255 u64 pvf : 16;
3256 u64 reserved_43_43 : 1;
3257 u64 zero : 1;
3258 u64 port : 3;
3259 u64 nmerge : 1;
3260 u64 esr : 2;
3261 u64 esw : 2;
3262 u64 wtype : 2;
3263 u64 rtype : 2;
3264 u64 reserved_0_29 : 30;
3265 } s;
3266 struct cvmx_sli_mem_access_subidx_cn61xx {
3267 u64 reserved_43_63 : 21;
3268 u64 zero : 1;
3269 u64 port : 3;
3270 u64 nmerge : 1;
3271 u64 esr : 2;
3272 u64 esw : 2;
3273 u64 wtype : 2;
3274 u64 rtype : 2;
3275 u64 ba : 30;
3276 } cn61xx;
3277 struct cvmx_sli_mem_access_subidx_cn61xx cn63xx;
3278 struct cvmx_sli_mem_access_subidx_cn61xx cn63xxp1;
3279 struct cvmx_sli_mem_access_subidx_cn61xx cn66xx;
3280 struct cvmx_sli_mem_access_subidx_cn68xx {
3281 u64 reserved_43_63 : 21;
3282 u64 zero : 1;
3283 u64 port : 3;
3284 u64 nmerge : 1;
3285 u64 esr : 2;
3286 u64 esw : 2;
3287 u64 wtype : 2;
3288 u64 rtype : 2;
3289 u64 ba : 28;
3290 u64 reserved_0_1 : 2;
3291 } cn68xx;
3292 struct cvmx_sli_mem_access_subidx_cn68xx cn68xxp1;
3293 struct cvmx_sli_mem_access_subidx_cn61xx cn70xx;
3294 struct cvmx_sli_mem_access_subidx_cn61xx cn70xxp1;
3295 struct cvmx_sli_mem_access_subidx_cn73xx {
3296 u64 reserved_60_63 : 4;
3297 u64 pvf : 16;
3298 u64 reserved_43_43 : 1;
3299 u64 zero : 1;
3300 u64 port : 3;
3301 u64 nmerge : 1;
3302 u64 esr : 2;
3303 u64 esw : 2;
3304 u64 wtype : 2;
3305 u64 rtype : 2;
3306 u64 ba : 30;
3307 } cn73xx;
3308 struct cvmx_sli_mem_access_subidx_cn73xx cn78xx;
3309 struct cvmx_sli_mem_access_subidx_cn61xx cn78xxp1;
3310 struct cvmx_sli_mem_access_subidx_cn61xx cnf71xx;
3311 struct cvmx_sli_mem_access_subidx_cn73xx cnf75xx;
3312};
3313
3314typedef union cvmx_sli_mem_access_subidx cvmx_sli_mem_access_subidx_t;
3315
3316/**
3317 * cvmx_sli_mem_ctl
3318 *
3319 * This register controls the ECC of the SLI memories.
3320 *
3321 */
3322union cvmx_sli_mem_ctl {
3323 u64 u64;
3324 struct cvmx_sli_mem_ctl_s {
3325 u64 reserved_27_63 : 37;
3326 u64 tlpn1_fs : 2;
3327 u64 tlpn1_ecc : 1;
3328 u64 tlpp1_fs : 2;
3329 u64 tlpp1_ecc : 1;
3330 u64 tlpc1_fs : 2;
3331 u64 tlpc1_ecc : 1;
3332 u64 tlpn0_fs : 2;
3333 u64 tlpn0_ecc : 1;
3334 u64 tlpp0_fs : 2;
3335 u64 tlpp0_ecc : 1;
3336 u64 tlpc0_fs : 2;
3337 u64 tlpc0_ecc : 1;
3338 u64 nppr_fs : 2;
3339 u64 nppr_ecc : 1;
3340 u64 cpl1_fs : 2;
3341 u64 cpl1_ecc : 1;
3342 u64 cpl0_fs : 2;
3343 u64 cpl0_ecc : 1;
3344 } s;
3345 struct cvmx_sli_mem_ctl_s cn73xx;
3346 struct cvmx_sli_mem_ctl_s cn78xx;
3347 struct cvmx_sli_mem_ctl_s cn78xxp1;
3348 struct cvmx_sli_mem_ctl_s cnf75xx;
3349};
3350
3351typedef union cvmx_sli_mem_ctl cvmx_sli_mem_ctl_t;
3352
3353/**
3354 * cvmx_sli_mem_int_sum
3355 *
3356 * Set when an interrupt condition occurs; write one to clear.
3357 *
3358 */
3359union cvmx_sli_mem_int_sum {
3360 u64 u64;
3361 struct cvmx_sli_mem_int_sum_s {
3362 u64 reserved_18_63 : 46;
3363 u64 tlpn1_dbe : 1;
3364 u64 tlpn1_sbe : 1;
3365 u64 tlpp1_dbe : 1;
3366 u64 tlpp1_sbe : 1;
3367 u64 tlpc1_dbe : 1;
3368 u64 tlpc1_sbe : 1;
3369 u64 tlpn0_dbe : 1;
3370 u64 tlpn0_sbe : 1;
3371 u64 tlpp0_dbe : 1;
3372 u64 tlpp0_sbe : 1;
3373 u64 tlpc0_dbe : 1;
3374 u64 tlpc0_sbe : 1;
3375 u64 nppr_dbe : 1;
3376 u64 nppr_sbe : 1;
3377 u64 cpl1_dbe : 1;
3378 u64 cpl1_sbe : 1;
3379 u64 cpl0_dbe : 1;
3380 u64 cpl0_sbe : 1;
3381 } s;
3382 struct cvmx_sli_mem_int_sum_s cn73xx;
3383 struct cvmx_sli_mem_int_sum_s cn78xx;
3384 struct cvmx_sli_mem_int_sum_s cn78xxp1;
3385 struct cvmx_sli_mem_int_sum_s cnf75xx;
3386};
3387
3388typedef union cvmx_sli_mem_int_sum cvmx_sli_mem_int_sum_t;
3389
3390/**
3391 * cvmx_sli_msi_enb0
3392 *
3393 * Used to enable the interrupt generation for the bits in the SLI_MSI_RCV0.
3394 *
3395 */
3396union cvmx_sli_msi_enb0 {
3397 u64 u64;
3398 struct cvmx_sli_msi_enb0_s {
3399 u64 enb : 64;
3400 } s;
3401 struct cvmx_sli_msi_enb0_s cn61xx;
3402 struct cvmx_sli_msi_enb0_s cn63xx;
3403 struct cvmx_sli_msi_enb0_s cn63xxp1;
3404 struct cvmx_sli_msi_enb0_s cn66xx;
3405 struct cvmx_sli_msi_enb0_s cn68xx;
3406 struct cvmx_sli_msi_enb0_s cn68xxp1;
3407 struct cvmx_sli_msi_enb0_s cn70xx;
3408 struct cvmx_sli_msi_enb0_s cn70xxp1;
3409 struct cvmx_sli_msi_enb0_s cnf71xx;
3410};
3411
3412typedef union cvmx_sli_msi_enb0 cvmx_sli_msi_enb0_t;
3413
3414/**
3415 * cvmx_sli_msi_enb1
3416 *
3417 * Used to enable the interrupt generation for the bits in the SLI_MSI_RCV1.
3418 *
3419 */
3420union cvmx_sli_msi_enb1 {
3421 u64 u64;
3422 struct cvmx_sli_msi_enb1_s {
3423 u64 enb : 64;
3424 } s;
3425 struct cvmx_sli_msi_enb1_s cn61xx;
3426 struct cvmx_sli_msi_enb1_s cn63xx;
3427 struct cvmx_sli_msi_enb1_s cn63xxp1;
3428 struct cvmx_sli_msi_enb1_s cn66xx;
3429 struct cvmx_sli_msi_enb1_s cn68xx;
3430 struct cvmx_sli_msi_enb1_s cn68xxp1;
3431 struct cvmx_sli_msi_enb1_s cn70xx;
3432 struct cvmx_sli_msi_enb1_s cn70xxp1;
3433 struct cvmx_sli_msi_enb1_s cnf71xx;
3434};
3435
3436typedef union cvmx_sli_msi_enb1 cvmx_sli_msi_enb1_t;
3437
3438/**
3439 * cvmx_sli_msi_enb2
3440 *
3441 * Used to enable the interrupt generation for the bits in the SLI_MSI_RCV2.
3442 *
3443 */
3444union cvmx_sli_msi_enb2 {
3445 u64 u64;
3446 struct cvmx_sli_msi_enb2_s {
3447 u64 enb : 64;
3448 } s;
3449 struct cvmx_sli_msi_enb2_s cn61xx;
3450 struct cvmx_sli_msi_enb2_s cn63xx;
3451 struct cvmx_sli_msi_enb2_s cn63xxp1;
3452 struct cvmx_sli_msi_enb2_s cn66xx;
3453 struct cvmx_sli_msi_enb2_s cn68xx;
3454 struct cvmx_sli_msi_enb2_s cn68xxp1;
3455 struct cvmx_sli_msi_enb2_s cn70xx;
3456 struct cvmx_sli_msi_enb2_s cn70xxp1;
3457 struct cvmx_sli_msi_enb2_s cnf71xx;
3458};
3459
3460typedef union cvmx_sli_msi_enb2 cvmx_sli_msi_enb2_t;
3461
3462/**
3463 * cvmx_sli_msi_enb3
3464 *
3465 * Used to enable the interrupt generation for the bits in the SLI_MSI_RCV3.
3466 *
3467 */
3468union cvmx_sli_msi_enb3 {
3469 u64 u64;
3470 struct cvmx_sli_msi_enb3_s {
3471 u64 enb : 64;
3472 } s;
3473 struct cvmx_sli_msi_enb3_s cn61xx;
3474 struct cvmx_sli_msi_enb3_s cn63xx;
3475 struct cvmx_sli_msi_enb3_s cn63xxp1;
3476 struct cvmx_sli_msi_enb3_s cn66xx;
3477 struct cvmx_sli_msi_enb3_s cn68xx;
3478 struct cvmx_sli_msi_enb3_s cn68xxp1;
3479 struct cvmx_sli_msi_enb3_s cn70xx;
3480 struct cvmx_sli_msi_enb3_s cn70xxp1;
3481 struct cvmx_sli_msi_enb3_s cnf71xx;
3482};
3483
3484typedef union cvmx_sli_msi_enb3 cvmx_sli_msi_enb3_t;
3485
3486/**
3487 * cvmx_sli_msi_rcv0
3488 *
3489 * This register contains bits <63:0> of the 256 bits of MSI interrupts.
3490 *
3491 */
3492union cvmx_sli_msi_rcv0 {
3493 u64 u64;
3494 struct cvmx_sli_msi_rcv0_s {
3495 u64 intr : 64;
3496 } s;
3497 struct cvmx_sli_msi_rcv0_s cn61xx;
3498 struct cvmx_sli_msi_rcv0_s cn63xx;
3499 struct cvmx_sli_msi_rcv0_s cn63xxp1;
3500 struct cvmx_sli_msi_rcv0_s cn66xx;
3501 struct cvmx_sli_msi_rcv0_s cn68xx;
3502 struct cvmx_sli_msi_rcv0_s cn68xxp1;
3503 struct cvmx_sli_msi_rcv0_s cn70xx;
3504 struct cvmx_sli_msi_rcv0_s cn70xxp1;
3505 struct cvmx_sli_msi_rcv0_s cn73xx;
3506 struct cvmx_sli_msi_rcv0_s cn78xx;
3507 struct cvmx_sli_msi_rcv0_s cn78xxp1;
3508 struct cvmx_sli_msi_rcv0_s cnf71xx;
3509 struct cvmx_sli_msi_rcv0_s cnf75xx;
3510};
3511
3512typedef union cvmx_sli_msi_rcv0 cvmx_sli_msi_rcv0_t;
3513
3514/**
3515 * cvmx_sli_msi_rcv1
3516 *
3517 * This register contains bits <127:64> of the 256 bits of MSI interrupts.
3518 *
3519 */
3520union cvmx_sli_msi_rcv1 {
3521 u64 u64;
3522 struct cvmx_sli_msi_rcv1_s {
3523 u64 intr : 64;
3524 } s;
3525 struct cvmx_sli_msi_rcv1_s cn61xx;
3526 struct cvmx_sli_msi_rcv1_s cn63xx;
3527 struct cvmx_sli_msi_rcv1_s cn63xxp1;
3528 struct cvmx_sli_msi_rcv1_s cn66xx;
3529 struct cvmx_sli_msi_rcv1_s cn68xx;
3530 struct cvmx_sli_msi_rcv1_s cn68xxp1;
3531 struct cvmx_sli_msi_rcv1_s cn70xx;
3532 struct cvmx_sli_msi_rcv1_s cn70xxp1;
3533 struct cvmx_sli_msi_rcv1_s cn73xx;
3534 struct cvmx_sli_msi_rcv1_s cn78xx;
3535 struct cvmx_sli_msi_rcv1_s cn78xxp1;
3536 struct cvmx_sli_msi_rcv1_s cnf71xx;
3537 struct cvmx_sli_msi_rcv1_s cnf75xx;
3538};
3539
3540typedef union cvmx_sli_msi_rcv1 cvmx_sli_msi_rcv1_t;
3541
3542/**
3543 * cvmx_sli_msi_rcv2
3544 *
3545 * This register contains bits <191:128> of the 256 bits of MSI interrupts.
3546 *
3547 */
3548union cvmx_sli_msi_rcv2 {
3549 u64 u64;
3550 struct cvmx_sli_msi_rcv2_s {
3551 u64 intr : 64;
3552 } s;
3553 struct cvmx_sli_msi_rcv2_s cn61xx;
3554 struct cvmx_sli_msi_rcv2_s cn63xx;
3555 struct cvmx_sli_msi_rcv2_s cn63xxp1;
3556 struct cvmx_sli_msi_rcv2_s cn66xx;
3557 struct cvmx_sli_msi_rcv2_s cn68xx;
3558 struct cvmx_sli_msi_rcv2_s cn68xxp1;
3559 struct cvmx_sli_msi_rcv2_s cn70xx;
3560 struct cvmx_sli_msi_rcv2_s cn70xxp1;
3561 struct cvmx_sli_msi_rcv2_s cn73xx;
3562 struct cvmx_sli_msi_rcv2_s cn78xx;
3563 struct cvmx_sli_msi_rcv2_s cn78xxp1;
3564 struct cvmx_sli_msi_rcv2_s cnf71xx;
3565 struct cvmx_sli_msi_rcv2_s cnf75xx;
3566};
3567
3568typedef union cvmx_sli_msi_rcv2 cvmx_sli_msi_rcv2_t;
3569
3570/**
3571 * cvmx_sli_msi_rcv3
3572 *
3573 * This register contains bits <255:192> of the 256 bits of MSI interrupts.
3574 *
3575 */
3576union cvmx_sli_msi_rcv3 {
3577 u64 u64;
3578 struct cvmx_sli_msi_rcv3_s {
3579 u64 intr : 64;
3580 } s;
3581 struct cvmx_sli_msi_rcv3_s cn61xx;
3582 struct cvmx_sli_msi_rcv3_s cn63xx;
3583 struct cvmx_sli_msi_rcv3_s cn63xxp1;
3584 struct cvmx_sli_msi_rcv3_s cn66xx;
3585 struct cvmx_sli_msi_rcv3_s cn68xx;
3586 struct cvmx_sli_msi_rcv3_s cn68xxp1;
3587 struct cvmx_sli_msi_rcv3_s cn70xx;
3588 struct cvmx_sli_msi_rcv3_s cn70xxp1;
3589 struct cvmx_sli_msi_rcv3_s cn73xx;
3590 struct cvmx_sli_msi_rcv3_s cn78xx;
3591 struct cvmx_sli_msi_rcv3_s cn78xxp1;
3592 struct cvmx_sli_msi_rcv3_s cnf71xx;
3593 struct cvmx_sli_msi_rcv3_s cnf75xx;
3594};
3595
3596typedef union cvmx_sli_msi_rcv3 cvmx_sli_msi_rcv3_t;
3597
3598/**
3599 * cvmx_sli_msi_rd_map
3600 *
3601 * This register is used to read the mapping function of the SLI_PCIE_MSI_RCV to SLI_MSI_RCV
3602 * registers.
3603 */
3604union cvmx_sli_msi_rd_map {
3605 u64 u64;
3606 struct cvmx_sli_msi_rd_map_s {
3607 u64 reserved_16_63 : 48;
3608 u64 rd_int : 8;
3609 u64 msi_int : 8;
3610 } s;
3611 struct cvmx_sli_msi_rd_map_s cn61xx;
3612 struct cvmx_sli_msi_rd_map_s cn63xx;
3613 struct cvmx_sli_msi_rd_map_s cn63xxp1;
3614 struct cvmx_sli_msi_rd_map_s cn66xx;
3615 struct cvmx_sli_msi_rd_map_s cn68xx;
3616 struct cvmx_sli_msi_rd_map_s cn68xxp1;
3617 struct cvmx_sli_msi_rd_map_s cn70xx;
3618 struct cvmx_sli_msi_rd_map_s cn70xxp1;
3619 struct cvmx_sli_msi_rd_map_s cn73xx;
3620 struct cvmx_sli_msi_rd_map_s cn78xx;
3621 struct cvmx_sli_msi_rd_map_s cn78xxp1;
3622 struct cvmx_sli_msi_rd_map_s cnf71xx;
3623 struct cvmx_sli_msi_rd_map_s cnf75xx;
3624};
3625
3626typedef union cvmx_sli_msi_rd_map cvmx_sli_msi_rd_map_t;
3627
3628/**
3629 * cvmx_sli_msi_w1c_enb0
3630 *
3631 * Used to clear bits in SLI_MSI_ENB0.
3632 *
3633 */
3634union cvmx_sli_msi_w1c_enb0 {
3635 u64 u64;
3636 struct cvmx_sli_msi_w1c_enb0_s {
3637 u64 clr : 64;
3638 } s;
3639 struct cvmx_sli_msi_w1c_enb0_s cn61xx;
3640 struct cvmx_sli_msi_w1c_enb0_s cn63xx;
3641 struct cvmx_sli_msi_w1c_enb0_s cn63xxp1;
3642 struct cvmx_sli_msi_w1c_enb0_s cn66xx;
3643 struct cvmx_sli_msi_w1c_enb0_s cn68xx;
3644 struct cvmx_sli_msi_w1c_enb0_s cn68xxp1;
3645 struct cvmx_sli_msi_w1c_enb0_s cn70xx;
3646 struct cvmx_sli_msi_w1c_enb0_s cn70xxp1;
3647 struct cvmx_sli_msi_w1c_enb0_s cnf71xx;
3648};
3649
3650typedef union cvmx_sli_msi_w1c_enb0 cvmx_sli_msi_w1c_enb0_t;
3651
3652/**
3653 * cvmx_sli_msi_w1c_enb1
3654 *
3655 * Used to clear bits in SLI_MSI_ENB1.
3656 *
3657 */
3658union cvmx_sli_msi_w1c_enb1 {
3659 u64 u64;
3660 struct cvmx_sli_msi_w1c_enb1_s {
3661 u64 clr : 64;
3662 } s;
3663 struct cvmx_sli_msi_w1c_enb1_s cn61xx;
3664 struct cvmx_sli_msi_w1c_enb1_s cn63xx;
3665 struct cvmx_sli_msi_w1c_enb1_s cn63xxp1;
3666 struct cvmx_sli_msi_w1c_enb1_s cn66xx;
3667 struct cvmx_sli_msi_w1c_enb1_s cn68xx;
3668 struct cvmx_sli_msi_w1c_enb1_s cn68xxp1;
3669 struct cvmx_sli_msi_w1c_enb1_s cn70xx;
3670 struct cvmx_sli_msi_w1c_enb1_s cn70xxp1;
3671 struct cvmx_sli_msi_w1c_enb1_s cnf71xx;
3672};
3673
3674typedef union cvmx_sli_msi_w1c_enb1 cvmx_sli_msi_w1c_enb1_t;
3675
3676/**
3677 * cvmx_sli_msi_w1c_enb2
3678 *
3679 * Used to clear bits in SLI_MSI_ENB2.
3680 *
3681 */
3682union cvmx_sli_msi_w1c_enb2 {
3683 u64 u64;
3684 struct cvmx_sli_msi_w1c_enb2_s {
3685 u64 clr : 64;
3686 } s;
3687 struct cvmx_sli_msi_w1c_enb2_s cn61xx;
3688 struct cvmx_sli_msi_w1c_enb2_s cn63xx;
3689 struct cvmx_sli_msi_w1c_enb2_s cn63xxp1;
3690 struct cvmx_sli_msi_w1c_enb2_s cn66xx;
3691 struct cvmx_sli_msi_w1c_enb2_s cn68xx;
3692 struct cvmx_sli_msi_w1c_enb2_s cn68xxp1;
3693 struct cvmx_sli_msi_w1c_enb2_s cn70xx;
3694 struct cvmx_sli_msi_w1c_enb2_s cn70xxp1;
3695 struct cvmx_sli_msi_w1c_enb2_s cnf71xx;
3696};
3697
3698typedef union cvmx_sli_msi_w1c_enb2 cvmx_sli_msi_w1c_enb2_t;
3699
3700/**
3701 * cvmx_sli_msi_w1c_enb3
3702 *
3703 * Used to clear bits in SLI_MSI_ENB3.
3704 *
3705 */
3706union cvmx_sli_msi_w1c_enb3 {
3707 u64 u64;
3708 struct cvmx_sli_msi_w1c_enb3_s {
3709 u64 clr : 64;
3710 } s;
3711 struct cvmx_sli_msi_w1c_enb3_s cn61xx;
3712 struct cvmx_sli_msi_w1c_enb3_s cn63xx;
3713 struct cvmx_sli_msi_w1c_enb3_s cn63xxp1;
3714 struct cvmx_sli_msi_w1c_enb3_s cn66xx;
3715 struct cvmx_sli_msi_w1c_enb3_s cn68xx;
3716 struct cvmx_sli_msi_w1c_enb3_s cn68xxp1;
3717 struct cvmx_sli_msi_w1c_enb3_s cn70xx;
3718 struct cvmx_sli_msi_w1c_enb3_s cn70xxp1;
3719 struct cvmx_sli_msi_w1c_enb3_s cnf71xx;
3720};
3721
3722typedef union cvmx_sli_msi_w1c_enb3 cvmx_sli_msi_w1c_enb3_t;
3723
3724/**
3725 * cvmx_sli_msi_w1s_enb0
3726 *
3727 * Used to set bits in SLI_MSI_ENB0.
3728 *
3729 */
3730union cvmx_sli_msi_w1s_enb0 {
3731 u64 u64;
3732 struct cvmx_sli_msi_w1s_enb0_s {
3733 u64 set : 64;
3734 } s;
3735 struct cvmx_sli_msi_w1s_enb0_s cn61xx;
3736 struct cvmx_sli_msi_w1s_enb0_s cn63xx;
3737 struct cvmx_sli_msi_w1s_enb0_s cn63xxp1;
3738 struct cvmx_sli_msi_w1s_enb0_s cn66xx;
3739 struct cvmx_sli_msi_w1s_enb0_s cn68xx;
3740 struct cvmx_sli_msi_w1s_enb0_s cn68xxp1;
3741 struct cvmx_sli_msi_w1s_enb0_s cn70xx;
3742 struct cvmx_sli_msi_w1s_enb0_s cn70xxp1;
3743 struct cvmx_sli_msi_w1s_enb0_s cnf71xx;
3744};
3745
3746typedef union cvmx_sli_msi_w1s_enb0 cvmx_sli_msi_w1s_enb0_t;
3747
3748/**
3749 * cvmx_sli_msi_w1s_enb1
3750 *
3751 * SLI_MSI_W1S_ENB0 = SLI MSI Write 1 To Set Enable1
3752 * Used to set bits in SLI_MSI_ENB1.
3753 */
3754union cvmx_sli_msi_w1s_enb1 {
3755 u64 u64;
3756 struct cvmx_sli_msi_w1s_enb1_s {
3757 u64 set : 64;
3758 } s;
3759 struct cvmx_sli_msi_w1s_enb1_s cn61xx;
3760 struct cvmx_sli_msi_w1s_enb1_s cn63xx;
3761 struct cvmx_sli_msi_w1s_enb1_s cn63xxp1;
3762 struct cvmx_sli_msi_w1s_enb1_s cn66xx;
3763 struct cvmx_sli_msi_w1s_enb1_s cn68xx;
3764 struct cvmx_sli_msi_w1s_enb1_s cn68xxp1;
3765 struct cvmx_sli_msi_w1s_enb1_s cn70xx;
3766 struct cvmx_sli_msi_w1s_enb1_s cn70xxp1;
3767 struct cvmx_sli_msi_w1s_enb1_s cnf71xx;
3768};
3769
3770typedef union cvmx_sli_msi_w1s_enb1 cvmx_sli_msi_w1s_enb1_t;
3771
3772/**
3773 * cvmx_sli_msi_w1s_enb2
3774 *
3775 * Used to set bits in SLI_MSI_ENB2.
3776 *
3777 */
3778union cvmx_sli_msi_w1s_enb2 {
3779 u64 u64;
3780 struct cvmx_sli_msi_w1s_enb2_s {
3781 u64 set : 64;
3782 } s;
3783 struct cvmx_sli_msi_w1s_enb2_s cn61xx;
3784 struct cvmx_sli_msi_w1s_enb2_s cn63xx;
3785 struct cvmx_sli_msi_w1s_enb2_s cn63xxp1;
3786 struct cvmx_sli_msi_w1s_enb2_s cn66xx;
3787 struct cvmx_sli_msi_w1s_enb2_s cn68xx;
3788 struct cvmx_sli_msi_w1s_enb2_s cn68xxp1;
3789 struct cvmx_sli_msi_w1s_enb2_s cn70xx;
3790 struct cvmx_sli_msi_w1s_enb2_s cn70xxp1;
3791 struct cvmx_sli_msi_w1s_enb2_s cnf71xx;
3792};
3793
3794typedef union cvmx_sli_msi_w1s_enb2 cvmx_sli_msi_w1s_enb2_t;
3795
3796/**
3797 * cvmx_sli_msi_w1s_enb3
3798 *
3799 * Used to set bits in SLI_MSI_ENB3.
3800 *
3801 */
3802union cvmx_sli_msi_w1s_enb3 {
3803 u64 u64;
3804 struct cvmx_sli_msi_w1s_enb3_s {
3805 u64 set : 64;
3806 } s;
3807 struct cvmx_sli_msi_w1s_enb3_s cn61xx;
3808 struct cvmx_sli_msi_w1s_enb3_s cn63xx;
3809 struct cvmx_sli_msi_w1s_enb3_s cn63xxp1;
3810 struct cvmx_sli_msi_w1s_enb3_s cn66xx;
3811 struct cvmx_sli_msi_w1s_enb3_s cn68xx;
3812 struct cvmx_sli_msi_w1s_enb3_s cn68xxp1;
3813 struct cvmx_sli_msi_w1s_enb3_s cn70xx;
3814 struct cvmx_sli_msi_w1s_enb3_s cn70xxp1;
3815 struct cvmx_sli_msi_w1s_enb3_s cnf71xx;
3816};
3817
3818typedef union cvmx_sli_msi_w1s_enb3 cvmx_sli_msi_w1s_enb3_t;
3819
3820/**
3821 * cvmx_sli_msi_wr_map
3822 *
3823 * This register is used to write the mapping function of the SLI_PCIE_MSI_RCV to SLI_MSI_RCV
3824 * registers. At reset, the mapping function is one-to-one, that is MSI_INT 1 maps to CIU_INT 1,
3825 * 2 to 2, 3 to 3, etc.
3826 */
3827union cvmx_sli_msi_wr_map {
3828 u64 u64;
3829 struct cvmx_sli_msi_wr_map_s {
3830 u64 reserved_16_63 : 48;
3831 u64 ciu_int : 8;
3832 u64 msi_int : 8;
3833 } s;
3834 struct cvmx_sli_msi_wr_map_s cn61xx;
3835 struct cvmx_sli_msi_wr_map_s cn63xx;
3836 struct cvmx_sli_msi_wr_map_s cn63xxp1;
3837 struct cvmx_sli_msi_wr_map_s cn66xx;
3838 struct cvmx_sli_msi_wr_map_s cn68xx;
3839 struct cvmx_sli_msi_wr_map_s cn68xxp1;
3840 struct cvmx_sli_msi_wr_map_s cn70xx;
3841 struct cvmx_sli_msi_wr_map_s cn70xxp1;
3842 struct cvmx_sli_msi_wr_map_s cn73xx;
3843 struct cvmx_sli_msi_wr_map_s cn78xx;
3844 struct cvmx_sli_msi_wr_map_s cn78xxp1;
3845 struct cvmx_sli_msi_wr_map_s cnf71xx;
3846 struct cvmx_sli_msi_wr_map_s cnf75xx;
3847};
3848
3849typedef union cvmx_sli_msi_wr_map cvmx_sli_msi_wr_map_t;
3850
3851/**
3852 * cvmx_sli_msix#_table_addr
3853 *
3854 * The MSI-X table cannot be burst read or written.
3855 *
3856 * The combination of all MSI-X Tables contain (64 + 4) entries - one per
3857 * ring plus one per PF. (i.e. 64 plus one per valid SLI_MAC()_PF()_INT_SUM
3858 * present.)
3859 *
3860 * The MSI-X table for an individual PF has SLI_PKT_MAC()_PF()_RINFO[TRS]
3861 * entries for the rings associated to the PF (up to 64 max) plus one
3862 * more table entry for SLI_MAC()_PF()_INT_SUM. The
3863 * SLI_MAC()_PF()_INT_SUM-related MSI-X table entry is
3864 * always entry SLI_MSIX(SLI_PKT_MAC()_PF()_RINFO[TRS])_TABLE_ADDR and
3865 * always present and valid. All earlier SLI_MSIX()_TABLE_ADDR entries
3866 * correspond to rings. When SLI_PKT_MAC()_PF()_RINFO[NVFS]=0, SR-IOV
3867 * virtual functions cannot be used, and all SLI_PKT_MAC()_PF()_RINFO[TRS]+1
3868 * entries in the PF MSI-X table are present and valid for use by the PF.
3869 * When SLI_PKT_MAC()_PF()_RINFO[NVFS]!=0, SR-IOV virtual functions may
3870 * be used, and the first
3871 * SLI_PKT_MAC()_PF()_RINFO[NVFS]*SLI_PKT_MAC()_PF()_RINFO[RPVF]
3872 * entries of the PF MSI-X table are present but not valid, and
3873 * should never be accessed by the PF.
3874 *
3875 * The MSI-X table for an individual VF has SLI_PKT_MAC()_PF()_RINFO[RPVF]
3876 * entries (up to 8 max), all valid, one per ring that the VF owns.
3877 */
3878union cvmx_sli_msixx_table_addr {
3879 u64 u64;
3880 struct cvmx_sli_msixx_table_addr_s {
3881 u64 addr : 64;
3882 } s;
3883 struct cvmx_sli_msixx_table_addr_s cn73xx;
3884 struct cvmx_sli_msixx_table_addr_s cn78xx;
3885 struct cvmx_sli_msixx_table_addr_s cn78xxp1;
3886 struct cvmx_sli_msixx_table_addr_s cnf75xx;
3887};
3888
3889typedef union cvmx_sli_msixx_table_addr cvmx_sli_msixx_table_addr_t;
3890
3891/**
3892 * cvmx_sli_msix#_table_data
3893 *
3894 * The MSI-X table cannot be burst read or written. VF/PF access is the same as
3895 * described for the SLI_MSIX()_TABLE_ADDR.
3896 */
3897union cvmx_sli_msixx_table_data {
3898 u64 u64;
3899 struct cvmx_sli_msixx_table_data_s {
3900 u64 reserved_33_63 : 31;
3901 u64 vector_ctl : 1;
3902 u64 data : 32;
3903 } s;
3904 struct cvmx_sli_msixx_table_data_s cn73xx;
3905 struct cvmx_sli_msixx_table_data_s cn78xx;
3906 struct cvmx_sli_msixx_table_data_s cn78xxp1;
3907 struct cvmx_sli_msixx_table_data_s cnf75xx;
3908};
3909
3910typedef union cvmx_sli_msixx_table_data cvmx_sli_msixx_table_data_t;
3911
3912/**
3913 * cvmx_sli_msix_mac#_pf_table_addr
3914 *
3915 * These registers shadow the four physical MSIX PF ERR entries.
3916 * Each MAC sees its entry at its own TRS offset.
3917 */
3918union cvmx_sli_msix_macx_pf_table_addr {
3919 u64 u64;
3920 struct cvmx_sli_msix_macx_pf_table_addr_s {
3921 u64 addr : 64;
3922 } s;
3923 struct cvmx_sli_msix_macx_pf_table_addr_s cn78xxp1;
3924};
3925
3926typedef union cvmx_sli_msix_macx_pf_table_addr cvmx_sli_msix_macx_pf_table_addr_t;
3927
3928/**
3929 * cvmx_sli_msix_mac#_pf_table_data
3930 *
3931 * These registers shadow four physical MSIX PF ERR entries.
3932 * Each MAC sees its entry at its own TRS offset.
3933 */
3934union cvmx_sli_msix_macx_pf_table_data {
3935 u64 u64;
3936 struct cvmx_sli_msix_macx_pf_table_data_s {
3937 u64 reserved_33_63 : 31;
3938 u64 vector_ctl : 1;
3939 u64 data : 32;
3940 } s;
3941 struct cvmx_sli_msix_macx_pf_table_data_s cn78xxp1;
3942};
3943
3944typedef union cvmx_sli_msix_macx_pf_table_data cvmx_sli_msix_macx_pf_table_data_t;
3945
3946/**
3947 * cvmx_sli_msix_pba0
3948 *
3949 * The MSI-X pending bit array cannot be burst read.
3950 * In SR-IOV mode, a VF will find its pending completion interrupts in bit
3951 * positions [(RPVF-1):0]. If RPVF<64, bits [63:RPVF] are returned as zero.
3952 *
3953 * Each VF can read their own pending completion interrupts based on the ring/VF
3954 * configuration. Therefore, a VF sees the PBA as smaller than what is shown below
3955 * (unless it owns all 64 entries). Unassigned bits will return zeros.
3956 *
3957 * <pre>
3958 * RPVF Interrupts per VF Pending bits returned
3959 * ---- ----------------- ---------------------
3960 * 0 0 0
3961 * 1 1 MSG_PND0
3962 * 2 2 MSG_PND1 - MSG_PND0
3963 * 4 4 MSG_PND3 - MSG_PND0
3964 * 8 8 MSG_PND7 - MSG_PND0
3965 * </pre>
3966 *
3967 * If SLI_PKT_MAC()_PF()_RINFO[TRS]=63 (i.e. 64 total DPI Packet Rings configured), a PF will
3968 * find its pending completion interrupts in bit positions [63:0]. When
3969 * SLI_PKT_MAC()_PF()_RINFO[TRS]=63,
3970 * the PF will find its PCIe error interrupt in SLI_MSIX_PBA1, bit position 0.
3971 *
3972 * If SLI_PKT_MAC()_PF()_RINFO[TRS]<63 (i.e. 0, 1, 2, 4, or 8 rings configured), a PF will find
3973 * its ring pending completion interrupts in bit positions [TNR:0]. It will find its PCIe
3974 * error interrupt in bit position [(TNR+1)]. Bits [63:(TNR+2)] are returned as zero.
3975 * When SLI_PKT_MAC()_PF()_RINFO[TRS]<63, SLI_MSIX_PBA1 is not used and returns zeros.
3976 *
3977 * If SR-IOV Mode is off there is no virtual function support, but the PF can configure up to 65
3978 * entries (up to 64 DPI Packet Rings plus 1 PF ring) for itself.
3979 */
3980union cvmx_sli_msix_pba0 {
3981 u64 u64;
3982 struct cvmx_sli_msix_pba0_s {
3983 u64 msg_pnd : 64;
3984 } s;
3985 struct cvmx_sli_msix_pba0_s cn73xx;
3986 struct cvmx_sli_msix_pba0_s cn78xx;
3987 struct cvmx_sli_msix_pba0_s cn78xxp1;
3988 struct cvmx_sli_msix_pba0_s cnf75xx;
3989};
3990
3991typedef union cvmx_sli_msix_pba0 cvmx_sli_msix_pba0_t;
3992
3993/**
3994 * cvmx_sli_msix_pba1
3995 *
3996 * The MSI-X pending bit array cannot be burst read.
3997 *
3998 * PF_PND is assigned to PCIe related errors. The error bit can only be found in PBA1 when
3999 * SLI_PKT_MAC()_PF()_RINFO[TRS]=63 (i.e. 64 total DPI Packet Rings configured).
4000 *
4001 * This register is accessible by the PF. A read by a particular PF only
4002 * returns its own pending status. That is, any PF can read this register, but the hardware
4003 * ensures
4004 * that the PF only sees its own status.
4005 */
4006union cvmx_sli_msix_pba1 {
4007 u64 u64;
4008 struct cvmx_sli_msix_pba1_s {
4009 u64 reserved_1_63 : 63;
4010 u64 pf_pnd : 1;
4011 } s;
4012 struct cvmx_sli_msix_pba1_s cn73xx;
4013 struct cvmx_sli_msix_pba1_s cn78xx;
4014 struct cvmx_sli_msix_pba1_s cn78xxp1;
4015 struct cvmx_sli_msix_pba1_s cnf75xx;
4016};
4017
4018typedef union cvmx_sli_msix_pba1 cvmx_sli_msix_pba1_t;
4019
4020/**
4021 * cvmx_sli_nqm_rsp_err_snd_dbg
4022 *
4023 * This register is for diagnostic use only.
4024 *
4025 */
4026union cvmx_sli_nqm_rsp_err_snd_dbg {
4027 u64 u64;
4028 struct cvmx_sli_nqm_rsp_err_snd_dbg_s {
4029 u64 reserved_12_63 : 52;
4030 u64 vf_index : 12;
4031 } s;
4032 struct cvmx_sli_nqm_rsp_err_snd_dbg_s cn73xx;
4033 struct cvmx_sli_nqm_rsp_err_snd_dbg_s cn78xx;
4034 struct cvmx_sli_nqm_rsp_err_snd_dbg_s cnf75xx;
4035};
4036
4037typedef union cvmx_sli_nqm_rsp_err_snd_dbg cvmx_sli_nqm_rsp_err_snd_dbg_t;
4038
4039/**
4040 * cvmx_sli_pcie_msi_rcv
4041 *
4042 * This is the register where MSI write operations are directed from the MAC.
4043 *
4044 */
4045union cvmx_sli_pcie_msi_rcv {
4046 u64 u64;
4047 struct cvmx_sli_pcie_msi_rcv_s {
4048 u64 reserved_8_63 : 56;
4049 u64 intr : 8;
4050 } s;
4051 struct cvmx_sli_pcie_msi_rcv_s cn61xx;
4052 struct cvmx_sli_pcie_msi_rcv_s cn63xx;
4053 struct cvmx_sli_pcie_msi_rcv_s cn63xxp1;
4054 struct cvmx_sli_pcie_msi_rcv_s cn66xx;
4055 struct cvmx_sli_pcie_msi_rcv_s cn68xx;
4056 struct cvmx_sli_pcie_msi_rcv_s cn68xxp1;
4057 struct cvmx_sli_pcie_msi_rcv_s cn70xx;
4058 struct cvmx_sli_pcie_msi_rcv_s cn70xxp1;
4059 struct cvmx_sli_pcie_msi_rcv_s cn73xx;
4060 struct cvmx_sli_pcie_msi_rcv_s cn78xx;
4061 struct cvmx_sli_pcie_msi_rcv_s cn78xxp1;
4062 struct cvmx_sli_pcie_msi_rcv_s cnf71xx;
4063 struct cvmx_sli_pcie_msi_rcv_s cnf75xx;
4064};
4065
4066typedef union cvmx_sli_pcie_msi_rcv cvmx_sli_pcie_msi_rcv_t;
4067
4068/**
4069 * cvmx_sli_pcie_msi_rcv_b1
4070 *
4071 * This register is where MSI write operations are directed from the MAC. This register can be
4072 * used by the PCIe and SRIO MACs.
4073 */
4074union cvmx_sli_pcie_msi_rcv_b1 {
4075 u64 u64;
4076 struct cvmx_sli_pcie_msi_rcv_b1_s {
4077 u64 reserved_16_63 : 48;
4078 u64 intr : 8;
4079 u64 reserved_0_7 : 8;
4080 } s;
4081 struct cvmx_sli_pcie_msi_rcv_b1_s cn61xx;
4082 struct cvmx_sli_pcie_msi_rcv_b1_s cn63xx;
4083 struct cvmx_sli_pcie_msi_rcv_b1_s cn63xxp1;
4084 struct cvmx_sli_pcie_msi_rcv_b1_s cn66xx;
4085 struct cvmx_sli_pcie_msi_rcv_b1_s cn68xx;
4086 struct cvmx_sli_pcie_msi_rcv_b1_s cn68xxp1;
4087 struct cvmx_sli_pcie_msi_rcv_b1_s cn70xx;
4088 struct cvmx_sli_pcie_msi_rcv_b1_s cn70xxp1;
4089 struct cvmx_sli_pcie_msi_rcv_b1_s cn73xx;
4090 struct cvmx_sli_pcie_msi_rcv_b1_s cn78xx;
4091 struct cvmx_sli_pcie_msi_rcv_b1_s cn78xxp1;
4092 struct cvmx_sli_pcie_msi_rcv_b1_s cnf71xx;
4093 struct cvmx_sli_pcie_msi_rcv_b1_s cnf75xx;
4094};
4095
4096typedef union cvmx_sli_pcie_msi_rcv_b1 cvmx_sli_pcie_msi_rcv_b1_t;
4097
4098/**
4099 * cvmx_sli_pcie_msi_rcv_b2
4100 *
4101 * This register is where MSI write operations are directed from the MAC. This register can be
4102 * used by PCIe and SRIO MACs.
4103 */
4104union cvmx_sli_pcie_msi_rcv_b2 {
4105 u64 u64;
4106 struct cvmx_sli_pcie_msi_rcv_b2_s {
4107 u64 reserved_24_63 : 40;
4108 u64 intr : 8;
4109 u64 reserved_0_15 : 16;
4110 } s;
4111 struct cvmx_sli_pcie_msi_rcv_b2_s cn61xx;
4112 struct cvmx_sli_pcie_msi_rcv_b2_s cn63xx;
4113 struct cvmx_sli_pcie_msi_rcv_b2_s cn63xxp1;
4114 struct cvmx_sli_pcie_msi_rcv_b2_s cn66xx;
4115 struct cvmx_sli_pcie_msi_rcv_b2_s cn68xx;
4116 struct cvmx_sli_pcie_msi_rcv_b2_s cn68xxp1;
4117 struct cvmx_sli_pcie_msi_rcv_b2_s cn70xx;
4118 struct cvmx_sli_pcie_msi_rcv_b2_s cn70xxp1;
4119 struct cvmx_sli_pcie_msi_rcv_b2_s cn73xx;
4120 struct cvmx_sli_pcie_msi_rcv_b2_s cn78xx;
4121 struct cvmx_sli_pcie_msi_rcv_b2_s cn78xxp1;
4122 struct cvmx_sli_pcie_msi_rcv_b2_s cnf71xx;
4123 struct cvmx_sli_pcie_msi_rcv_b2_s cnf75xx;
4124};
4125
4126typedef union cvmx_sli_pcie_msi_rcv_b2 cvmx_sli_pcie_msi_rcv_b2_t;
4127
4128/**
4129 * cvmx_sli_pcie_msi_rcv_b3
4130 *
4131 * This register is where MSI write operations are directed from the MAC. This register can be
4132 * used by PCIe and SRIO MACs.
4133 */
4134union cvmx_sli_pcie_msi_rcv_b3 {
4135 u64 u64;
4136 struct cvmx_sli_pcie_msi_rcv_b3_s {
4137 u64 reserved_32_63 : 32;
4138 u64 intr : 8;
4139 u64 reserved_0_23 : 24;
4140 } s;
4141 struct cvmx_sli_pcie_msi_rcv_b3_s cn61xx;
4142 struct cvmx_sli_pcie_msi_rcv_b3_s cn63xx;
4143 struct cvmx_sli_pcie_msi_rcv_b3_s cn63xxp1;
4144 struct cvmx_sli_pcie_msi_rcv_b3_s cn66xx;
4145 struct cvmx_sli_pcie_msi_rcv_b3_s cn68xx;
4146 struct cvmx_sli_pcie_msi_rcv_b3_s cn68xxp1;
4147 struct cvmx_sli_pcie_msi_rcv_b3_s cn70xx;
4148 struct cvmx_sli_pcie_msi_rcv_b3_s cn70xxp1;
4149 struct cvmx_sli_pcie_msi_rcv_b3_s cn73xx;
4150 struct cvmx_sli_pcie_msi_rcv_b3_s cn78xx;
4151 struct cvmx_sli_pcie_msi_rcv_b3_s cn78xxp1;
4152 struct cvmx_sli_pcie_msi_rcv_b3_s cnf71xx;
4153 struct cvmx_sli_pcie_msi_rcv_b3_s cnf75xx;
4154};
4155
4156typedef union cvmx_sli_pcie_msi_rcv_b3 cvmx_sli_pcie_msi_rcv_b3_t;
4157
4158/**
4159 * cvmx_sli_pkt#_cnts
4160 *
4161 * This register contains the counters for output rings.
4162 *
4163 */
4164union cvmx_sli_pktx_cnts {
4165 u64 u64;
4166 struct cvmx_sli_pktx_cnts_s {
4167 u64 po_int : 1;
4168 u64 pi_int : 1;
4169 u64 mbox_int : 1;
4170 u64 resend : 1;
4171 u64 reserved_54_59 : 6;
4172 u64 timer : 22;
4173 u64 cnt : 32;
4174 } s;
4175 struct cvmx_sli_pktx_cnts_cn61xx {
4176 u64 reserved_54_63 : 10;
4177 u64 timer : 22;
4178 u64 cnt : 32;
4179 } cn61xx;
4180 struct cvmx_sli_pktx_cnts_cn61xx cn63xx;
4181 struct cvmx_sli_pktx_cnts_cn61xx cn63xxp1;
4182 struct cvmx_sli_pktx_cnts_cn61xx cn66xx;
4183 struct cvmx_sli_pktx_cnts_cn61xx cn68xx;
4184 struct cvmx_sli_pktx_cnts_cn61xx cn68xxp1;
4185 struct cvmx_sli_pktx_cnts_cn70xx {
4186 u64 reserved_63_54 : 10;
4187 u64 timer : 22;
4188 u64 cnt : 32;
4189 } cn70xx;
4190 struct cvmx_sli_pktx_cnts_cn70xx cn70xxp1;
4191 struct cvmx_sli_pktx_cnts_s cn73xx;
4192 struct cvmx_sli_pktx_cnts_s cn78xx;
4193 struct cvmx_sli_pktx_cnts_cn78xxp1 {
4194 u64 po_int : 1;
4195 u64 pi_int : 1;
4196 u64 reserved_61_54 : 8;
4197 u64 timer : 22;
4198 u64 cnt : 32;
4199 } cn78xxp1;
4200 struct cvmx_sli_pktx_cnts_cn61xx cnf71xx;
4201 struct cvmx_sli_pktx_cnts_s cnf75xx;
4202};
4203
4204typedef union cvmx_sli_pktx_cnts cvmx_sli_pktx_cnts_t;
4205
4206/**
4207 * cvmx_sli_pkt#_error_info
4208 *
4209 * The fields in this register are set when an error conditions occur and can be cleared.
4210 * These fields are for information purpose only and do NOT generate interrupts.
4211 */
4212union cvmx_sli_pktx_error_info {
4213 u64 u64;
4214 struct cvmx_sli_pktx_error_info_s {
4215 u64 reserved_8_63 : 56;
4216 u64 osize_err : 1;
4217 u64 nobdell_err : 1;
4218 u64 pins_err : 1;
4219 u64 pop_err : 1;
4220 u64 pdi_err : 1;
4221 u64 pgl_err : 1;
4222 u64 psldbof : 1;
4223 u64 pidbof : 1;
4224 } s;
4225 struct cvmx_sli_pktx_error_info_s cn73xx;
4226 struct cvmx_sli_pktx_error_info_s cn78xx;
4227 struct cvmx_sli_pktx_error_info_s cnf75xx;
4228};
4229
4230typedef union cvmx_sli_pktx_error_info cvmx_sli_pktx_error_info_t;
4231
4232/**
4233 * cvmx_sli_pkt#_in_bp
4234 *
4235 * "SLI_PKT[0..31]_IN_BP = SLI Packet ring# Input Backpressure
4236 * The counters and thresholds for input packets to apply backpressure to processing of the
4237 * packets."
4238 */
4239union cvmx_sli_pktx_in_bp {
4240 u64 u64;
4241 struct cvmx_sli_pktx_in_bp_s {
4242 u64 wmark : 32;
4243 u64 cnt : 32;
4244 } s;
4245 struct cvmx_sli_pktx_in_bp_s cn61xx;
4246 struct cvmx_sli_pktx_in_bp_s cn63xx;
4247 struct cvmx_sli_pktx_in_bp_s cn63xxp1;
4248 struct cvmx_sli_pktx_in_bp_s cn66xx;
4249 struct cvmx_sli_pktx_in_bp_s cn70xx;
4250 struct cvmx_sli_pktx_in_bp_s cn70xxp1;
4251 struct cvmx_sli_pktx_in_bp_s cnf71xx;
4252};
4253
4254typedef union cvmx_sli_pktx_in_bp cvmx_sli_pktx_in_bp_t;
4255
4256/**
4257 * cvmx_sli_pkt#_input_control
4258 *
4259 * This register is the control for read operations for gather list and instructions.
4260 *
4261 */
4262union cvmx_sli_pktx_input_control {
4263 u64 u64;
4264 struct cvmx_sli_pktx_input_control_s {
4265 u64 reserved_55_63 : 9;
4266 u64 rpvf : 7;
4267 u64 reserved_31_47 : 17;
4268 u64 mac_num : 2;
4269 u64 quiet : 1;
4270 u64 reserved_27_27 : 1;
4271 u64 rdsize : 2;
4272 u64 is_64b : 1;
4273 u64 rst : 1;
4274 u64 enb : 1;
4275 u64 pbp_dhi : 13;
4276 u64 d_nsr : 1;
4277 u64 d_esr : 2;
4278 u64 d_ror : 1;
4279 u64 use_csr : 1;
4280 u64 nsr : 1;
4281 u64 esr : 2;
4282 u64 ror : 1;
4283 } s;
4284 struct cvmx_sli_pktx_input_control_cn73xx {
4285 u64 reserved_55_63 : 9;
4286 u64 rpvf : 7;
4287 u64 pvf_num : 16;
4288 u64 reserved_31_31 : 1;
4289 u64 mac_num : 2;
4290 u64 quiet : 1;
4291 u64 reserved_27_27 : 1;
4292 u64 rdsize : 2;
4293 u64 is_64b : 1;
4294 u64 rst : 1;
4295 u64 enb : 1;
4296 u64 pbp_dhi : 13;
4297 u64 d_nsr : 1;
4298 u64 d_esr : 2;
4299 u64 d_ror : 1;
4300 u64 use_csr : 1;
4301 u64 nsr : 1;
4302 u64 esr : 2;
4303 u64 ror : 1;
4304 } cn73xx;
4305 struct cvmx_sli_pktx_input_control_cn73xx cn78xx;
4306 struct cvmx_sli_pktx_input_control_cn78xxp1 {
4307 u64 reserved_39_63 : 25;
4308 u64 vf_num : 7;
4309 u64 reserved_31_31 : 1;
4310 u64 mac_num : 2;
4311 u64 reserved_27_28 : 2;
4312 u64 rdsize : 2;
4313 u64 is_64b : 1;
4314 u64 rst : 1;
4315 u64 enb : 1;
4316 u64 pbp_dhi : 13;
4317 u64 d_nsr : 1;
4318 u64 d_esr : 2;
4319 u64 d_ror : 1;
4320 u64 use_csr : 1;
4321 u64 nsr : 1;
4322 u64 esr : 2;
4323 u64 ror : 1;
4324 } cn78xxp1;
4325 struct cvmx_sli_pktx_input_control_cn73xx cnf75xx;
4326};
4327
4328typedef union cvmx_sli_pktx_input_control cvmx_sli_pktx_input_control_t;
4329
4330/**
4331 * cvmx_sli_pkt#_instr_baddr
4332 *
4333 * This register contains the start-of-instruction for input packets. The address must be
4334 * addressed-aligned to the size of the instruction.
4335 */
4336union cvmx_sli_pktx_instr_baddr {
4337 u64 u64;
4338 struct cvmx_sli_pktx_instr_baddr_s {
4339 u64 addr : 61;
4340 u64 reserved_0_2 : 3;
4341 } s;
4342 struct cvmx_sli_pktx_instr_baddr_s cn61xx;
4343 struct cvmx_sli_pktx_instr_baddr_s cn63xx;
4344 struct cvmx_sli_pktx_instr_baddr_s cn63xxp1;
4345 struct cvmx_sli_pktx_instr_baddr_s cn66xx;
4346 struct cvmx_sli_pktx_instr_baddr_s cn68xx;
4347 struct cvmx_sli_pktx_instr_baddr_s cn68xxp1;
4348 struct cvmx_sli_pktx_instr_baddr_s cn70xx;
4349 struct cvmx_sli_pktx_instr_baddr_s cn70xxp1;
4350 struct cvmx_sli_pktx_instr_baddr_s cn73xx;
4351 struct cvmx_sli_pktx_instr_baddr_s cn78xx;
4352 struct cvmx_sli_pktx_instr_baddr_s cn78xxp1;
4353 struct cvmx_sli_pktx_instr_baddr_s cnf71xx;
4354 struct cvmx_sli_pktx_instr_baddr_s cnf75xx;
4355};
4356
4357typedef union cvmx_sli_pktx_instr_baddr cvmx_sli_pktx_instr_baddr_t;
4358
4359/**
4360 * cvmx_sli_pkt#_instr_baoff_dbell
4361 *
4362 * This register contains the doorbell and base address offset for the next read.
4363 *
4364 */
4365union cvmx_sli_pktx_instr_baoff_dbell {
4366 u64 u64;
4367 struct cvmx_sli_pktx_instr_baoff_dbell_s {
4368 u64 aoff : 32;
4369 u64 dbell : 32;
4370 } s;
4371 struct cvmx_sli_pktx_instr_baoff_dbell_s cn61xx;
4372 struct cvmx_sli_pktx_instr_baoff_dbell_s cn63xx;
4373 struct cvmx_sli_pktx_instr_baoff_dbell_s cn63xxp1;
4374 struct cvmx_sli_pktx_instr_baoff_dbell_s cn66xx;
4375 struct cvmx_sli_pktx_instr_baoff_dbell_s cn68xx;
4376 struct cvmx_sli_pktx_instr_baoff_dbell_s cn68xxp1;
4377 struct cvmx_sli_pktx_instr_baoff_dbell_s cn70xx;
4378 struct cvmx_sli_pktx_instr_baoff_dbell_s cn70xxp1;
4379 struct cvmx_sli_pktx_instr_baoff_dbell_s cn73xx;
4380 struct cvmx_sli_pktx_instr_baoff_dbell_s cn78xx;
4381 struct cvmx_sli_pktx_instr_baoff_dbell_s cn78xxp1;
4382 struct cvmx_sli_pktx_instr_baoff_dbell_s cnf71xx;
4383 struct cvmx_sli_pktx_instr_baoff_dbell_s cnf75xx;
4384};
4385
4386typedef union cvmx_sli_pktx_instr_baoff_dbell cvmx_sli_pktx_instr_baoff_dbell_t;
4387
4388/**
4389 * cvmx_sli_pkt#_instr_fifo_rsize
4390 *
4391 * This register contains the FIFO field and ring size for instructions.
4392 *
4393 */
4394union cvmx_sli_pktx_instr_fifo_rsize {
4395 u64 u64;
4396 struct cvmx_sli_pktx_instr_fifo_rsize_s {
4397 u64 max : 9;
4398 u64 rrp : 9;
4399 u64 wrp : 9;
4400 u64 fcnt : 5;
4401 u64 rsize : 32;
4402 } s;
4403 struct cvmx_sli_pktx_instr_fifo_rsize_s cn61xx;
4404 struct cvmx_sli_pktx_instr_fifo_rsize_s cn63xx;
4405 struct cvmx_sli_pktx_instr_fifo_rsize_s cn63xxp1;
4406 struct cvmx_sli_pktx_instr_fifo_rsize_s cn66xx;
4407 struct cvmx_sli_pktx_instr_fifo_rsize_s cn68xx;
4408 struct cvmx_sli_pktx_instr_fifo_rsize_s cn68xxp1;
4409 struct cvmx_sli_pktx_instr_fifo_rsize_s cn70xx;
4410 struct cvmx_sli_pktx_instr_fifo_rsize_s cn70xxp1;
4411 struct cvmx_sli_pktx_instr_fifo_rsize_s cn73xx;
4412 struct cvmx_sli_pktx_instr_fifo_rsize_s cn78xx;
4413 struct cvmx_sli_pktx_instr_fifo_rsize_s cn78xxp1;
4414 struct cvmx_sli_pktx_instr_fifo_rsize_s cnf71xx;
4415 struct cvmx_sli_pktx_instr_fifo_rsize_s cnf75xx;
4416};
4417
4418typedef union cvmx_sli_pktx_instr_fifo_rsize cvmx_sli_pktx_instr_fifo_rsize_t;
4419
4420/**
4421 * cvmx_sli_pkt#_instr_header
4422 *
4423 * "SLI_PKT[0..31]_INSTR_HEADER = SLI Packet ring# Instruction Header.
4424 * VAlues used to build input packet header."
4425 */
4426union cvmx_sli_pktx_instr_header {
4427 u64 u64;
4428 struct cvmx_sli_pktx_instr_header_s {
4429 u64 reserved_44_63 : 20;
4430 u64 pbp : 1;
4431 u64 reserved_38_42 : 5;
4432 u64 rparmode : 2;
4433 u64 reserved_35_35 : 1;
4434 u64 rskp_len : 7;
4435 u64 rngrpext : 2;
4436 u64 rnqos : 1;
4437 u64 rngrp : 1;
4438 u64 rntt : 1;
4439 u64 rntag : 1;
4440 u64 use_ihdr : 1;
4441 u64 reserved_16_20 : 5;
4442 u64 par_mode : 2;
4443 u64 reserved_13_13 : 1;
4444 u64 skp_len : 7;
4445 u64 ngrpext : 2;
4446 u64 nqos : 1;
4447 u64 ngrp : 1;
4448 u64 ntt : 1;
4449 u64 ntag : 1;
4450 } s;
4451 struct cvmx_sli_pktx_instr_header_cn61xx {
4452 u64 reserved_44_63 : 20;
4453 u64 pbp : 1;
4454 u64 reserved_38_42 : 5;
4455 u64 rparmode : 2;
4456 u64 reserved_35_35 : 1;
4457 u64 rskp_len : 7;
4458 u64 reserved_26_27 : 2;
4459 u64 rnqos : 1;
4460 u64 rngrp : 1;
4461 u64 rntt : 1;
4462 u64 rntag : 1;
4463 u64 use_ihdr : 1;
4464 u64 reserved_16_20 : 5;
4465 u64 par_mode : 2;
4466 u64 reserved_13_13 : 1;
4467 u64 skp_len : 7;
4468 u64 reserved_4_5 : 2;
4469 u64 nqos : 1;
4470 u64 ngrp : 1;
4471 u64 ntt : 1;
4472 u64 ntag : 1;
4473 } cn61xx;
4474 struct cvmx_sli_pktx_instr_header_cn61xx cn63xx;
4475 struct cvmx_sli_pktx_instr_header_cn61xx cn63xxp1;
4476 struct cvmx_sli_pktx_instr_header_cn61xx cn66xx;
4477 struct cvmx_sli_pktx_instr_header_s cn68xx;
4478 struct cvmx_sli_pktx_instr_header_cn61xx cn68xxp1;
4479 struct cvmx_sli_pktx_instr_header_cn70xx {
4480 u64 reserved_44_63 : 20;
4481 u64 pbp : 1;
4482 u64 reserved_38_42 : 5;
4483 u64 rparmode : 2;
4484 u64 reserved_35_35 : 1;
4485 u64 rskp_len : 7;
4486 u64 reserved_27_26 : 2;
4487 u64 rnqos : 1;
4488 u64 rngrp : 1;
4489 u64 rntt : 1;
4490 u64 rntag : 1;
4491 u64 use_ihdr : 1;
4492 u64 reserved_20_16 : 5;
4493 u64 par_mode : 2;
4494 u64 reserved_13_13 : 1;
4495 u64 skp_len : 7;
4496 u64 reserved_5_4 : 2;
4497 u64 nqos : 1;
4498 u64 ngrp : 1;
4499 u64 ntt : 1;
4500 u64 ntag : 1;
4501 } cn70xx;
4502 struct cvmx_sli_pktx_instr_header_cn70xx cn70xxp1;
4503 struct cvmx_sli_pktx_instr_header_cn61xx cnf71xx;
4504};
4505
4506typedef union cvmx_sli_pktx_instr_header cvmx_sli_pktx_instr_header_t;
4507
4508/**
4509 * cvmx_sli_pkt#_int_levels
4510 *
4511 * This register contains output-packet interrupt levels.
4512 *
4513 */
4514union cvmx_sli_pktx_int_levels {
4515 u64 u64;
4516 struct cvmx_sli_pktx_int_levels_s {
4517 u64 reserved_54_63 : 10;
4518 u64 time : 22;
4519 u64 cnt : 32;
4520 } s;
4521 struct cvmx_sli_pktx_int_levels_s cn73xx;
4522 struct cvmx_sli_pktx_int_levels_s cn78xx;
4523 struct cvmx_sli_pktx_int_levels_s cn78xxp1;
4524 struct cvmx_sli_pktx_int_levels_s cnf75xx;
4525};
4526
4527typedef union cvmx_sli_pktx_int_levels cvmx_sli_pktx_int_levels_t;
4528
4529/**
4530 * cvmx_sli_pkt#_mbox_int
4531 *
4532 * This register contains information to service mbox interrupts to the VF
4533 * when the PF writes SLI_PKT()_PF_VF_MBOX_SIG(0).
4534 */
4535union cvmx_sli_pktx_mbox_int {
4536 u64 u64;
4537 struct cvmx_sli_pktx_mbox_int_s {
4538 u64 po_int : 1;
4539 u64 pi_int : 1;
4540 u64 mbox_int : 1;
4541 u64 resend : 1;
4542 u64 reserved_1_59 : 59;
4543 u64 mbox_en : 1;
4544 } s;
4545 struct cvmx_sli_pktx_mbox_int_s cn73xx;
4546 struct cvmx_sli_pktx_mbox_int_s cn78xx;
4547 struct cvmx_sli_pktx_mbox_int_s cnf75xx;
4548};
4549
4550typedef union cvmx_sli_pktx_mbox_int cvmx_sli_pktx_mbox_int_t;
4551
4552/**
4553 * cvmx_sli_pkt#_out_size
4554 *
4555 * This register contains the BSIZE and ISIZE for output packet rings.
4556 *
4557 */
4558union cvmx_sli_pktx_out_size {
4559 u64 u64;
4560 struct cvmx_sli_pktx_out_size_s {
4561 u64 reserved_23_63 : 41;
4562 u64 isize : 7;
4563 u64 bsize : 16;
4564 } s;
4565 struct cvmx_sli_pktx_out_size_s cn61xx;
4566 struct cvmx_sli_pktx_out_size_s cn63xx;
4567 struct cvmx_sli_pktx_out_size_s cn63xxp1;
4568 struct cvmx_sli_pktx_out_size_s cn66xx;
4569 struct cvmx_sli_pktx_out_size_s cn68xx;
4570 struct cvmx_sli_pktx_out_size_s cn68xxp1;
4571 struct cvmx_sli_pktx_out_size_s cn70xx;
4572 struct cvmx_sli_pktx_out_size_s cn70xxp1;
4573 struct cvmx_sli_pktx_out_size_cn73xx {
4574 u64 reserved_22_63 : 42;
4575 u64 isize : 6;
4576 u64 bsize : 16;
4577 } cn73xx;
4578 struct cvmx_sli_pktx_out_size_cn73xx cn78xx;
4579 struct cvmx_sli_pktx_out_size_s cn78xxp1;
4580 struct cvmx_sli_pktx_out_size_s cnf71xx;
4581 struct cvmx_sli_pktx_out_size_cn73xx cnf75xx;
4582};
4583
4584typedef union cvmx_sli_pktx_out_size cvmx_sli_pktx_out_size_t;
4585
4586/**
4587 * cvmx_sli_pkt#_output_control
4588 *
4589 * This register is the control for read operations for gather list and instructions.
4590 *
4591 */
4592union cvmx_sli_pktx_output_control {
4593 u64 u64;
4594 struct cvmx_sli_pktx_output_control_s {
4595 u64 reserved_14_63 : 50;
4596 u64 tenb : 1;
4597 u64 cenb : 1;
4598 u64 iptr : 1;
4599 u64 es : 2;
4600 u64 nsr : 1;
4601 u64 ror : 1;
4602 u64 dptr : 1;
4603 u64 bmode : 1;
4604 u64 es_p : 2;
4605 u64 nsr_p : 1;
4606 u64 ror_p : 1;
4607 u64 enb : 1;
4608 } s;
4609 struct cvmx_sli_pktx_output_control_s cn73xx;
4610 struct cvmx_sli_pktx_output_control_s cn78xx;
4611 struct cvmx_sli_pktx_output_control_s cn78xxp1;
4612 struct cvmx_sli_pktx_output_control_s cnf75xx;
4613};
4614
4615typedef union cvmx_sli_pktx_output_control cvmx_sli_pktx_output_control_t;
4616
4617/**
4618 * cvmx_sli_pkt#_pf_vf_mbox_sig#
4619 *
4620 * These registers are used for communication of data from the PF to the VF and vice versa.
4621 *
4622 * There are two registers per ring, SIG(0) and SIG(1). The PF and VF, both, have read and
4623 * write access to these registers.
4624 *
4625 * For PF-to-VF ring interrupts, SLI_PKT(0..63)_MBOX_INT[MBOX_EN] must be set.
4626 * When [MBOX_EN] is set, writes from the PF to byte 0 of the SIG(0) register will cause
4627 * an interrupt by setting [MBOX_INT] in the corresponding ring address of
4628 * SLI_PKT()_MBOX_INT[MBOX_INT],
4629 * SLI_PKT_IN_DONE()_CNTS[MBOX_INT], and SLI_PKT()_CNTS[MBOX_INT].
4630 *
4631 * For VF-to-PF ring interrupt, SLI_MAC()_PF()_INT_ENB[VF_MBOX] must be set.
4632 * When [VF_MBOX] is set, write from the VF to byte 0 of the SIG(1) register will cause an
4633 * interrupt by setting ring address VF_INT field in corresponding SLI_MAC()_PF()_MBOX_INT
4634 * register,
4635 * which may cause an interrupt to occur through PF.
4636 *
4637 * Each PF and VF can only access the rings that it owns as programmed by
4638 * SLI_PKT_MAC()_PF()_RINFO.
4639 * The signaling is ring-based. If a VF owns more than one ring, it can ignore the other
4640 * rings' registers if not needed.
4641 */
4642union cvmx_sli_pktx_pf_vf_mbox_sigx {
4643 u64 u64;
4644 struct cvmx_sli_pktx_pf_vf_mbox_sigx_s {
4645 u64 data : 64;
4646 } s;
4647 struct cvmx_sli_pktx_pf_vf_mbox_sigx_s cn73xx;
4648 struct cvmx_sli_pktx_pf_vf_mbox_sigx_s cn78xx;
4649 struct cvmx_sli_pktx_pf_vf_mbox_sigx_s cnf75xx;
4650};
4651
4652typedef union cvmx_sli_pktx_pf_vf_mbox_sigx cvmx_sli_pktx_pf_vf_mbox_sigx_t;
4653
4654/**
4655 * cvmx_sli_pkt#_slist_baddr
4656 *
4657 * This register contains the start of scatter list for output-packet pointers. This address must
4658 * be 16-byte aligned.
4659 */
4660union cvmx_sli_pktx_slist_baddr {
4661 u64 u64;
4662 struct cvmx_sli_pktx_slist_baddr_s {
4663 u64 addr : 60;
4664 u64 reserved_0_3 : 4;
4665 } s;
4666 struct cvmx_sli_pktx_slist_baddr_s cn61xx;
4667 struct cvmx_sli_pktx_slist_baddr_s cn63xx;
4668 struct cvmx_sli_pktx_slist_baddr_s cn63xxp1;
4669 struct cvmx_sli_pktx_slist_baddr_s cn66xx;
4670 struct cvmx_sli_pktx_slist_baddr_s cn68xx;
4671 struct cvmx_sli_pktx_slist_baddr_s cn68xxp1;
4672 struct cvmx_sli_pktx_slist_baddr_s cn70xx;
4673 struct cvmx_sli_pktx_slist_baddr_s cn70xxp1;
4674 struct cvmx_sli_pktx_slist_baddr_s cn73xx;
4675 struct cvmx_sli_pktx_slist_baddr_s cn78xx;
4676 struct cvmx_sli_pktx_slist_baddr_s cn78xxp1;
4677 struct cvmx_sli_pktx_slist_baddr_s cnf71xx;
4678 struct cvmx_sli_pktx_slist_baddr_s cnf75xx;
4679};
4680
4681typedef union cvmx_sli_pktx_slist_baddr cvmx_sli_pktx_slist_baddr_t;
4682
4683/**
4684 * cvmx_sli_pkt#_slist_baoff_dbell
4685 *
4686 * This register contains the doorbell and base-address offset for next read operation.
4687 *
4688 */
4689union cvmx_sli_pktx_slist_baoff_dbell {
4690 u64 u64;
4691 struct cvmx_sli_pktx_slist_baoff_dbell_s {
4692 u64 aoff : 32;
4693 u64 dbell : 32;
4694 } s;
4695 struct cvmx_sli_pktx_slist_baoff_dbell_s cn61xx;
4696 struct cvmx_sli_pktx_slist_baoff_dbell_s cn63xx;
4697 struct cvmx_sli_pktx_slist_baoff_dbell_s cn63xxp1;
4698 struct cvmx_sli_pktx_slist_baoff_dbell_s cn66xx;
4699 struct cvmx_sli_pktx_slist_baoff_dbell_s cn68xx;
4700 struct cvmx_sli_pktx_slist_baoff_dbell_s cn68xxp1;
4701 struct cvmx_sli_pktx_slist_baoff_dbell_s cn70xx;
4702 struct cvmx_sli_pktx_slist_baoff_dbell_s cn70xxp1;
4703 struct cvmx_sli_pktx_slist_baoff_dbell_s cn73xx;
4704 struct cvmx_sli_pktx_slist_baoff_dbell_s cn78xx;
4705 struct cvmx_sli_pktx_slist_baoff_dbell_s cn78xxp1;
4706 struct cvmx_sli_pktx_slist_baoff_dbell_s cnf71xx;
4707 struct cvmx_sli_pktx_slist_baoff_dbell_s cnf75xx;
4708};
4709
4710typedef union cvmx_sli_pktx_slist_baoff_dbell cvmx_sli_pktx_slist_baoff_dbell_t;
4711
4712/**
4713 * cvmx_sli_pkt#_slist_fifo_rsize
4714 *
4715 * This register contains the number of scatter pointer pairs in the scatter list.
4716 *
4717 */
4718union cvmx_sli_pktx_slist_fifo_rsize {
4719 u64 u64;
4720 struct cvmx_sli_pktx_slist_fifo_rsize_s {
4721 u64 reserved_32_63 : 32;
4722 u64 rsize : 32;
4723 } s;
4724 struct cvmx_sli_pktx_slist_fifo_rsize_s cn61xx;
4725 struct cvmx_sli_pktx_slist_fifo_rsize_s cn63xx;
4726 struct cvmx_sli_pktx_slist_fifo_rsize_s cn63xxp1;
4727 struct cvmx_sli_pktx_slist_fifo_rsize_s cn66xx;
4728 struct cvmx_sli_pktx_slist_fifo_rsize_s cn68xx;
4729 struct cvmx_sli_pktx_slist_fifo_rsize_s cn68xxp1;
4730 struct cvmx_sli_pktx_slist_fifo_rsize_cn70xx {
4731 u64 reserved_63_32 : 32;
4732 u64 rsize : 32;
4733 } cn70xx;
4734 struct cvmx_sli_pktx_slist_fifo_rsize_cn70xx cn70xxp1;
4735 struct cvmx_sli_pktx_slist_fifo_rsize_cn70xx cn73xx;
4736 struct cvmx_sli_pktx_slist_fifo_rsize_cn70xx cn78xx;
4737 struct cvmx_sli_pktx_slist_fifo_rsize_cn70xx cn78xxp1;
4738 struct cvmx_sli_pktx_slist_fifo_rsize_s cnf71xx;
4739 struct cvmx_sli_pktx_slist_fifo_rsize_cn70xx cnf75xx;
4740};
4741
4742typedef union cvmx_sli_pktx_slist_fifo_rsize cvmx_sli_pktx_slist_fifo_rsize_t;
4743
4744/**
4745 * cvmx_sli_pkt#_vf_int_sum
4746 *
4747 * This register contains summary interrupts bits for a VF. A VF read of this register
4748 * for any of its 8 rings will return the same 8-bit summary for packet input, packet
4749 * output and mailbox interrupts. If a PF reads this register it will return 0x0.
4750 */
4751union cvmx_sli_pktx_vf_int_sum {
4752 u64 u64;
4753 struct cvmx_sli_pktx_vf_int_sum_s {
4754 u64 reserved_40_63 : 24;
4755 u64 mbox : 8;
4756 u64 reserved_24_31 : 8;
4757 u64 pkt_out : 8;
4758 u64 reserved_8_15 : 8;
4759 u64 pkt_in : 8;
4760 } s;
4761 struct cvmx_sli_pktx_vf_int_sum_s cn73xx;
4762 struct cvmx_sli_pktx_vf_int_sum_s cn78xx;
4763 struct cvmx_sli_pktx_vf_int_sum_s cnf75xx;
4764};
4765
4766typedef union cvmx_sli_pktx_vf_int_sum cvmx_sli_pktx_vf_int_sum_t;
4767
4768/**
4769 * cvmx_sli_pkt#_vf_sig
4770 *
4771 * This register is used to signal between PF/VF. These 64 registers are index by VF number.
4772 *
4773 */
4774union cvmx_sli_pktx_vf_sig {
4775 u64 u64;
4776 struct cvmx_sli_pktx_vf_sig_s {
4777 u64 data : 64;
4778 } s;
4779 struct cvmx_sli_pktx_vf_sig_s cn78xxp1;
4780};
4781
4782typedef union cvmx_sli_pktx_vf_sig cvmx_sli_pktx_vf_sig_t;
4783
4784/**
4785 * cvmx_sli_pkt_bist_status
4786 *
4787 * This is the built-in self-test (BIST) status register. Each bit is the BIST result of an
4788 * individual memory (per bit, 0 = pass and 1 = fail).
4789 */
4790union cvmx_sli_pkt_bist_status {
4791 u64 u64;
4792 struct cvmx_sli_pkt_bist_status_s {
4793 u64 reserved_22_63 : 42;
4794 u64 bist : 22;
4795 } s;
4796 struct cvmx_sli_pkt_bist_status_s cn73xx;
4797 struct cvmx_sli_pkt_bist_status_s cn78xx;
4798 struct cvmx_sli_pkt_bist_status_s cnf75xx;
4799};
4800
4801typedef union cvmx_sli_pkt_bist_status cvmx_sli_pkt_bist_status_t;
4802
4803/**
4804 * cvmx_sli_pkt_cnt_int
4805 *
4806 * This register specifies which output packet rings are interrupting because of packet counters.
4807 * A bit set in this interrupt register will set a corresponding bit in SLI_PKT_INT and can
4808 * also cause SLI_MAC()_PF()_INT_SUM[PCNT] to be set if SLI_PKT()_OUTPUT_CONTROL[CENB] is set.
4809 * When read by a function, this register informs which rings owned by the function (0 to N,
4810 * N as large as 63) have this interrupt pending.
4811 */
4812union cvmx_sli_pkt_cnt_int {
4813 u64 u64;
4814 struct cvmx_sli_pkt_cnt_int_s {
4815 u64 reserved_0_63 : 64;
4816 } s;
4817 struct cvmx_sli_pkt_cnt_int_cn61xx {
4818 u64 reserved_32_63 : 32;
4819 u64 port : 32;
4820 } cn61xx;
4821 struct cvmx_sli_pkt_cnt_int_cn61xx cn63xx;
4822 struct cvmx_sli_pkt_cnt_int_cn61xx cn63xxp1;
4823 struct cvmx_sli_pkt_cnt_int_cn61xx cn66xx;
4824 struct cvmx_sli_pkt_cnt_int_cn61xx cn68xx;
4825 struct cvmx_sli_pkt_cnt_int_cn61xx cn68xxp1;
4826 struct cvmx_sli_pkt_cnt_int_cn61xx cn70xx;
4827 struct cvmx_sli_pkt_cnt_int_cn61xx cn70xxp1;
4828 struct cvmx_sli_pkt_cnt_int_cn73xx {
4829 u64 ring : 64;
4830 } cn73xx;
4831 struct cvmx_sli_pkt_cnt_int_cn73xx cn78xx;
4832 struct cvmx_sli_pkt_cnt_int_cn73xx cn78xxp1;
4833 struct cvmx_sli_pkt_cnt_int_cn61xx cnf71xx;
4834 struct cvmx_sli_pkt_cnt_int_cn73xx cnf75xx;
4835};
4836
4837typedef union cvmx_sli_pkt_cnt_int cvmx_sli_pkt_cnt_int_t;
4838
4839/**
4840 * cvmx_sli_pkt_cnt_int_enb
4841 *
4842 * Enable for the packets rings that are interrupting because of Packet Counters.
4843 *
4844 */
4845union cvmx_sli_pkt_cnt_int_enb {
4846 u64 u64;
4847 struct cvmx_sli_pkt_cnt_int_enb_s {
4848 u64 reserved_32_63 : 32;
4849 u64 port : 32;
4850 } s;
4851 struct cvmx_sli_pkt_cnt_int_enb_s cn61xx;
4852 struct cvmx_sli_pkt_cnt_int_enb_s cn63xx;
4853 struct cvmx_sli_pkt_cnt_int_enb_s cn63xxp1;
4854 struct cvmx_sli_pkt_cnt_int_enb_s cn66xx;
4855 struct cvmx_sli_pkt_cnt_int_enb_s cn68xx;
4856 struct cvmx_sli_pkt_cnt_int_enb_s cn68xxp1;
4857 struct cvmx_sli_pkt_cnt_int_enb_s cn70xx;
4858 struct cvmx_sli_pkt_cnt_int_enb_s cn70xxp1;
4859 struct cvmx_sli_pkt_cnt_int_enb_s cnf71xx;
4860};
4861
4862typedef union cvmx_sli_pkt_cnt_int_enb cvmx_sli_pkt_cnt_int_enb_t;
4863
4864/**
4865 * cvmx_sli_pkt_ctl
4866 *
4867 * Control for packets.
4868 *
4869 */
4870union cvmx_sli_pkt_ctl {
4871 u64 u64;
4872 struct cvmx_sli_pkt_ctl_s {
4873 u64 reserved_5_63 : 59;
4874 u64 ring_en : 1;
4875 u64 pkt_bp : 4;
4876 } s;
4877 struct cvmx_sli_pkt_ctl_s cn61xx;
4878 struct cvmx_sli_pkt_ctl_s cn63xx;
4879 struct cvmx_sli_pkt_ctl_s cn63xxp1;
4880 struct cvmx_sli_pkt_ctl_s cn66xx;
4881 struct cvmx_sli_pkt_ctl_s cn68xx;
4882 struct cvmx_sli_pkt_ctl_s cn68xxp1;
4883 struct cvmx_sli_pkt_ctl_s cn70xx;
4884 struct cvmx_sli_pkt_ctl_s cn70xxp1;
4885 struct cvmx_sli_pkt_ctl_s cnf71xx;
4886};
4887
4888typedef union cvmx_sli_pkt_ctl cvmx_sli_pkt_ctl_t;
4889
4890/**
4891 * cvmx_sli_pkt_data_out_es
4892 *
4893 * The Endian Swap for writing Data Out.
4894 *
4895 */
4896union cvmx_sli_pkt_data_out_es {
4897 u64 u64;
4898 struct cvmx_sli_pkt_data_out_es_s {
4899 u64 es : 64;
4900 } s;
4901 struct cvmx_sli_pkt_data_out_es_s cn61xx;
4902 struct cvmx_sli_pkt_data_out_es_s cn63xx;
4903 struct cvmx_sli_pkt_data_out_es_s cn63xxp1;
4904 struct cvmx_sli_pkt_data_out_es_s cn66xx;
4905 struct cvmx_sli_pkt_data_out_es_s cn68xx;
4906 struct cvmx_sli_pkt_data_out_es_s cn68xxp1;
4907 struct cvmx_sli_pkt_data_out_es_s cn70xx;
4908 struct cvmx_sli_pkt_data_out_es_s cn70xxp1;
4909 struct cvmx_sli_pkt_data_out_es_s cnf71xx;
4910};
4911
4912typedef union cvmx_sli_pkt_data_out_es cvmx_sli_pkt_data_out_es_t;
4913
4914/**
4915 * cvmx_sli_pkt_data_out_ns
4916 *
4917 * The NS field for the TLP when writing packet data.
4918 *
4919 */
4920union cvmx_sli_pkt_data_out_ns {
4921 u64 u64;
4922 struct cvmx_sli_pkt_data_out_ns_s {
4923 u64 reserved_32_63 : 32;
4924 u64 nsr : 32;
4925 } s;
4926 struct cvmx_sli_pkt_data_out_ns_s cn61xx;
4927 struct cvmx_sli_pkt_data_out_ns_s cn63xx;
4928 struct cvmx_sli_pkt_data_out_ns_s cn63xxp1;
4929 struct cvmx_sli_pkt_data_out_ns_s cn66xx;
4930 struct cvmx_sli_pkt_data_out_ns_s cn68xx;
4931 struct cvmx_sli_pkt_data_out_ns_s cn68xxp1;
4932 struct cvmx_sli_pkt_data_out_ns_s cn70xx;
4933 struct cvmx_sli_pkt_data_out_ns_s cn70xxp1;
4934 struct cvmx_sli_pkt_data_out_ns_s cnf71xx;
4935};
4936
4937typedef union cvmx_sli_pkt_data_out_ns cvmx_sli_pkt_data_out_ns_t;
4938
4939/**
4940 * cvmx_sli_pkt_data_out_ror
4941 *
4942 * The ROR field for the TLP when writing Packet Data.
4943 *
4944 */
4945union cvmx_sli_pkt_data_out_ror {
4946 u64 u64;
4947 struct cvmx_sli_pkt_data_out_ror_s {
4948 u64 reserved_32_63 : 32;
4949 u64 ror : 32;
4950 } s;
4951 struct cvmx_sli_pkt_data_out_ror_s cn61xx;
4952 struct cvmx_sli_pkt_data_out_ror_s cn63xx;
4953 struct cvmx_sli_pkt_data_out_ror_s cn63xxp1;
4954 struct cvmx_sli_pkt_data_out_ror_s cn66xx;
4955 struct cvmx_sli_pkt_data_out_ror_s cn68xx;
4956 struct cvmx_sli_pkt_data_out_ror_s cn68xxp1;
4957 struct cvmx_sli_pkt_data_out_ror_s cn70xx;
4958 struct cvmx_sli_pkt_data_out_ror_s cn70xxp1;
4959 struct cvmx_sli_pkt_data_out_ror_s cnf71xx;
4960};
4961
4962typedef union cvmx_sli_pkt_data_out_ror cvmx_sli_pkt_data_out_ror_t;
4963
4964/**
4965 * cvmx_sli_pkt_dpaddr
4966 *
4967 * Used to detemine address and attributes for packet data writes.
4968 *
4969 */
4970union cvmx_sli_pkt_dpaddr {
4971 u64 u64;
4972 struct cvmx_sli_pkt_dpaddr_s {
4973 u64 reserved_32_63 : 32;
4974 u64 dptr : 32;
4975 } s;
4976 struct cvmx_sli_pkt_dpaddr_s cn61xx;
4977 struct cvmx_sli_pkt_dpaddr_s cn63xx;
4978 struct cvmx_sli_pkt_dpaddr_s cn63xxp1;
4979 struct cvmx_sli_pkt_dpaddr_s cn66xx;
4980 struct cvmx_sli_pkt_dpaddr_s cn68xx;
4981 struct cvmx_sli_pkt_dpaddr_s cn68xxp1;
4982 struct cvmx_sli_pkt_dpaddr_s cn70xx;
4983 struct cvmx_sli_pkt_dpaddr_s cn70xxp1;
4984 struct cvmx_sli_pkt_dpaddr_s cnf71xx;
4985};
4986
4987typedef union cvmx_sli_pkt_dpaddr cvmx_sli_pkt_dpaddr_t;
4988
4989/**
4990 * cvmx_sli_pkt_gbl_control
4991 *
4992 * This register contains control bits that affect all packet rings.
4993 *
4994 */
4995union cvmx_sli_pkt_gbl_control {
4996 u64 u64;
4997 struct cvmx_sli_pkt_gbl_control_s {
4998 u64 reserved_32_63 : 32;
4999 u64 qtime : 16;
5000 u64 reserved_14_15 : 2;
5001 u64 bpkind : 6;
5002 u64 reserved_4_7 : 4;
5003 u64 pkpfval : 1;
5004 u64 bpflr_d : 1;
5005 u64 noptr_d : 1;
5006 u64 picnt_d : 1;
5007 } s;
5008 struct cvmx_sli_pkt_gbl_control_s cn73xx;
5009 struct cvmx_sli_pkt_gbl_control_s cn78xx;
5010 struct cvmx_sli_pkt_gbl_control_s cnf75xx;
5011};
5012
5013typedef union cvmx_sli_pkt_gbl_control cvmx_sli_pkt_gbl_control_t;
5014
5015/**
5016 * cvmx_sli_pkt_in_bp
5017 *
5018 * Which input rings have backpressure applied.
5019 *
5020 */
5021union cvmx_sli_pkt_in_bp {
5022 u64 u64;
5023 struct cvmx_sli_pkt_in_bp_s {
5024 u64 reserved_32_63 : 32;
5025 u64 bp : 32;
5026 } s;
5027 struct cvmx_sli_pkt_in_bp_s cn61xx;
5028 struct cvmx_sli_pkt_in_bp_s cn63xx;
5029 struct cvmx_sli_pkt_in_bp_s cn63xxp1;
5030 struct cvmx_sli_pkt_in_bp_s cn66xx;
5031 struct cvmx_sli_pkt_in_bp_s cn70xx;
5032 struct cvmx_sli_pkt_in_bp_s cn70xxp1;
5033 struct cvmx_sli_pkt_in_bp_s cnf71xx;
5034};
5035
5036typedef union cvmx_sli_pkt_in_bp cvmx_sli_pkt_in_bp_t;
5037
5038/**
5039 * cvmx_sli_pkt_in_done#_cnts
5040 *
5041 * This register contains counters for instructions completed on input rings.
5042 *
5043 */
5044union cvmx_sli_pkt_in_donex_cnts {
5045 u64 u64;
5046 struct cvmx_sli_pkt_in_donex_cnts_s {
5047 u64 po_int : 1;
5048 u64 pi_int : 1;
5049 u64 mbox_int : 1;
5050 u64 resend : 1;
5051 u64 reserved_49_59 : 11;
5052 u64 cint_enb : 1;
5053 u64 wmark : 16;
5054 u64 cnt : 32;
5055 } s;
5056 struct cvmx_sli_pkt_in_donex_cnts_cn61xx {
5057 u64 reserved_32_63 : 32;
5058 u64 cnt : 32;
5059 } cn61xx;
5060 struct cvmx_sli_pkt_in_donex_cnts_cn61xx cn63xx;
5061 struct cvmx_sli_pkt_in_donex_cnts_cn61xx cn63xxp1;
5062 struct cvmx_sli_pkt_in_donex_cnts_cn61xx cn66xx;
5063 struct cvmx_sli_pkt_in_donex_cnts_cn61xx cn68xx;
5064 struct cvmx_sli_pkt_in_donex_cnts_cn61xx cn68xxp1;
5065 struct cvmx_sli_pkt_in_donex_cnts_cn70xx {
5066 u64 reserved_63_32 : 32;
5067 u64 cnt : 32;
5068 } cn70xx;
5069 struct cvmx_sli_pkt_in_donex_cnts_cn70xx cn70xxp1;
5070 struct cvmx_sli_pkt_in_donex_cnts_s cn73xx;
5071 struct cvmx_sli_pkt_in_donex_cnts_s cn78xx;
5072 struct cvmx_sli_pkt_in_donex_cnts_cn78xxp1 {
5073 u64 po_int : 1;
5074 u64 pi_int : 1;
5075 u64 reserved_61_49 : 13;
5076 u64 cint_enb : 1;
5077 u64 wmark : 16;
5078 u64 cnt : 32;
5079 } cn78xxp1;
5080 struct cvmx_sli_pkt_in_donex_cnts_cn61xx cnf71xx;
5081 struct cvmx_sli_pkt_in_donex_cnts_s cnf75xx;
5082};
5083
5084typedef union cvmx_sli_pkt_in_donex_cnts cvmx_sli_pkt_in_donex_cnts_t;
5085
5086/**
5087 * cvmx_sli_pkt_in_instr_counts
5088 *
5089 * This register contains keeps track of the number of instructions read into the FIFO and
5090 * packets sent to PKI. This register is PF-only.
5091 */
5092union cvmx_sli_pkt_in_instr_counts {
5093 u64 u64;
5094 struct cvmx_sli_pkt_in_instr_counts_s {
5095 u64 wr_cnt : 32;
5096 u64 rd_cnt : 32;
5097 } s;
5098 struct cvmx_sli_pkt_in_instr_counts_s cn61xx;
5099 struct cvmx_sli_pkt_in_instr_counts_s cn63xx;
5100 struct cvmx_sli_pkt_in_instr_counts_s cn63xxp1;
5101 struct cvmx_sli_pkt_in_instr_counts_s cn66xx;
5102 struct cvmx_sli_pkt_in_instr_counts_s cn68xx;
5103 struct cvmx_sli_pkt_in_instr_counts_s cn68xxp1;
5104 struct cvmx_sli_pkt_in_instr_counts_s cn70xx;
5105 struct cvmx_sli_pkt_in_instr_counts_s cn70xxp1;
5106 struct cvmx_sli_pkt_in_instr_counts_s cn73xx;
5107 struct cvmx_sli_pkt_in_instr_counts_s cn78xx;
5108 struct cvmx_sli_pkt_in_instr_counts_s cn78xxp1;
5109 struct cvmx_sli_pkt_in_instr_counts_s cnf71xx;
5110 struct cvmx_sli_pkt_in_instr_counts_s cnf75xx;
5111};
5112
5113typedef union cvmx_sli_pkt_in_instr_counts cvmx_sli_pkt_in_instr_counts_t;
5114
5115/**
5116 * cvmx_sli_pkt_in_int
5117 *
5118 * This register specifies which input packets rings are interrupting because of done counts.
5119 * A bit set in this interrupt register will set a corresponding bit in SLI_PKT_INT which
5120 * can cause a MSI-X interrupt. When read by a function, this register informs which rings
5121 * owned by the function (0 to N, N as large as 63) have this interrupt pending.
5122 * SLI_PKT_IN_INT conditions can cause MSI-X interrupts, but do not cause any
5123 * SLI_MAC()_PF()_INT_SUM
5124 * bit to set, and cannot cause INTA/B/C/D nor MSI interrupts.
5125 */
5126union cvmx_sli_pkt_in_int {
5127 u64 u64;
5128 struct cvmx_sli_pkt_in_int_s {
5129 u64 ring : 64;
5130 } s;
5131 struct cvmx_sli_pkt_in_int_s cn73xx;
5132 struct cvmx_sli_pkt_in_int_s cn78xx;
5133 struct cvmx_sli_pkt_in_int_s cn78xxp1;
5134 struct cvmx_sli_pkt_in_int_s cnf75xx;
5135};
5136
5137typedef union cvmx_sli_pkt_in_int cvmx_sli_pkt_in_int_t;
5138
5139/**
5140 * cvmx_sli_pkt_in_jabber
5141 *
5142 * Register to set limit on SLI packet input packet sizes.
5143 *
5144 */
5145union cvmx_sli_pkt_in_jabber {
5146 u64 u64;
5147 struct cvmx_sli_pkt_in_jabber_s {
5148 u64 reserved_32_63 : 32;
5149 u64 size : 32;
5150 } s;
5151 struct cvmx_sli_pkt_in_jabber_s cn73xx;
5152 struct cvmx_sli_pkt_in_jabber_s cn78xx;
5153 struct cvmx_sli_pkt_in_jabber_s cnf75xx;
5154};
5155
5156typedef union cvmx_sli_pkt_in_jabber cvmx_sli_pkt_in_jabber_t;
5157
5158/**
5159 * cvmx_sli_pkt_in_pcie_port
5160 *
5161 * Assigns Packet Input rings to MAC ports.
5162 *
5163 */
5164union cvmx_sli_pkt_in_pcie_port {
5165 u64 u64;
5166 struct cvmx_sli_pkt_in_pcie_port_s {
5167 u64 pp : 64;
5168 } s;
5169 struct cvmx_sli_pkt_in_pcie_port_s cn61xx;
5170 struct cvmx_sli_pkt_in_pcie_port_s cn63xx;
5171 struct cvmx_sli_pkt_in_pcie_port_s cn63xxp1;
5172 struct cvmx_sli_pkt_in_pcie_port_s cn66xx;
5173 struct cvmx_sli_pkt_in_pcie_port_s cn68xx;
5174 struct cvmx_sli_pkt_in_pcie_port_s cn68xxp1;
5175 struct cvmx_sli_pkt_in_pcie_port_s cn70xx;
5176 struct cvmx_sli_pkt_in_pcie_port_s cn70xxp1;
5177 struct cvmx_sli_pkt_in_pcie_port_s cnf71xx;
5178};
5179
5180typedef union cvmx_sli_pkt_in_pcie_port cvmx_sli_pkt_in_pcie_port_t;
5181
5182/**
5183 * cvmx_sli_pkt_input_control
5184 *
5185 * Control for reads for gather list and instructions.
5186 *
5187 */
5188union cvmx_sli_pkt_input_control {
5189 u64 u64;
5190 struct cvmx_sli_pkt_input_control_s {
5191 u64 prd_erst : 1;
5192 u64 prd_rds : 7;
5193 u64 gii_erst : 1;
5194 u64 gii_rds : 7;
5195 u64 reserved_41_47 : 7;
5196 u64 prc_idle : 1;
5197 u64 reserved_24_39 : 16;
5198 u64 pin_rst : 1;
5199 u64 pkt_rr : 1;
5200 u64 pbp_dhi : 13;
5201 u64 d_nsr : 1;
5202 u64 d_esr : 2;
5203 u64 d_ror : 1;
5204 u64 use_csr : 1;
5205 u64 nsr : 1;
5206 u64 esr : 2;
5207 u64 ror : 1;
5208 } s;
5209 struct cvmx_sli_pkt_input_control_s cn61xx;
5210 struct cvmx_sli_pkt_input_control_cn63xx {
5211 u64 reserved_23_63 : 41;
5212 u64 pkt_rr : 1;
5213 u64 pbp_dhi : 13;
5214 u64 d_nsr : 1;
5215 u64 d_esr : 2;
5216 u64 d_ror : 1;
5217 u64 use_csr : 1;
5218 u64 nsr : 1;
5219 u64 esr : 2;
5220 u64 ror : 1;
5221 } cn63xx;
5222 struct cvmx_sli_pkt_input_control_cn63xx cn63xxp1;
5223 struct cvmx_sli_pkt_input_control_s cn66xx;
5224 struct cvmx_sli_pkt_input_control_s cn68xx;
5225 struct cvmx_sli_pkt_input_control_s cn68xxp1;
5226 struct cvmx_sli_pkt_input_control_s cn70xx;
5227 struct cvmx_sli_pkt_input_control_s cn70xxp1;
5228 struct cvmx_sli_pkt_input_control_s cnf71xx;
5229};
5230
5231typedef union cvmx_sli_pkt_input_control cvmx_sli_pkt_input_control_t;
5232
5233/**
5234 * cvmx_sli_pkt_instr_enb
5235 *
5236 * Multi-ring instruction input enable register. This register is PF-only.
5237 *
5238 */
5239union cvmx_sli_pkt_instr_enb {
5240 u64 u64;
5241 struct cvmx_sli_pkt_instr_enb_s {
5242 u64 enb : 64;
5243 } s;
5244 struct cvmx_sli_pkt_instr_enb_cn61xx {
5245 u64 reserved_32_63 : 32;
5246 u64 enb : 32;
5247 } cn61xx;
5248 struct cvmx_sli_pkt_instr_enb_cn61xx cn63xx;
5249 struct cvmx_sli_pkt_instr_enb_cn61xx cn63xxp1;
5250 struct cvmx_sli_pkt_instr_enb_cn61xx cn66xx;
5251 struct cvmx_sli_pkt_instr_enb_cn61xx cn68xx;
5252 struct cvmx_sli_pkt_instr_enb_cn61xx cn68xxp1;
5253 struct cvmx_sli_pkt_instr_enb_cn61xx cn70xx;
5254 struct cvmx_sli_pkt_instr_enb_cn61xx cn70xxp1;
5255 struct cvmx_sli_pkt_instr_enb_s cn78xxp1;
5256 struct cvmx_sli_pkt_instr_enb_cn61xx cnf71xx;
5257};
5258
5259typedef union cvmx_sli_pkt_instr_enb cvmx_sli_pkt_instr_enb_t;
5260
5261/**
5262 * cvmx_sli_pkt_instr_rd_size
5263 *
5264 * The number of instruction allowed to be read at one time.
5265 *
5266 */
5267union cvmx_sli_pkt_instr_rd_size {
5268 u64 u64;
5269 struct cvmx_sli_pkt_instr_rd_size_s {
5270 u64 rdsize : 64;
5271 } s;
5272 struct cvmx_sli_pkt_instr_rd_size_s cn61xx;
5273 struct cvmx_sli_pkt_instr_rd_size_s cn63xx;
5274 struct cvmx_sli_pkt_instr_rd_size_s cn63xxp1;
5275 struct cvmx_sli_pkt_instr_rd_size_s cn66xx;
5276 struct cvmx_sli_pkt_instr_rd_size_s cn68xx;
5277 struct cvmx_sli_pkt_instr_rd_size_s cn68xxp1;
5278 struct cvmx_sli_pkt_instr_rd_size_s cn70xx;
5279 struct cvmx_sli_pkt_instr_rd_size_s cn70xxp1;
5280 struct cvmx_sli_pkt_instr_rd_size_s cnf71xx;
5281};
5282
5283typedef union cvmx_sli_pkt_instr_rd_size cvmx_sli_pkt_instr_rd_size_t;
5284
5285/**
5286 * cvmx_sli_pkt_instr_size
5287 *
5288 * Determines if instructions are 64 or 32 byte in size for a Packet-ring.
5289 *
5290 */
5291union cvmx_sli_pkt_instr_size {
5292 u64 u64;
5293 struct cvmx_sli_pkt_instr_size_s {
5294 u64 reserved_32_63 : 32;
5295 u64 is_64b : 32;
5296 } s;
5297 struct cvmx_sli_pkt_instr_size_s cn61xx;
5298 struct cvmx_sli_pkt_instr_size_s cn63xx;
5299 struct cvmx_sli_pkt_instr_size_s cn63xxp1;
5300 struct cvmx_sli_pkt_instr_size_s cn66xx;
5301 struct cvmx_sli_pkt_instr_size_s cn68xx;
5302 struct cvmx_sli_pkt_instr_size_s cn68xxp1;
5303 struct cvmx_sli_pkt_instr_size_s cn70xx;
5304 struct cvmx_sli_pkt_instr_size_s cn70xxp1;
5305 struct cvmx_sli_pkt_instr_size_s cnf71xx;
5306};
5307
5308typedef union cvmx_sli_pkt_instr_size cvmx_sli_pkt_instr_size_t;
5309
5310/**
5311 * cvmx_sli_pkt_int
5312 *
5313 * This register combines the SLI_PKT_CNT_INT, SLI_PKT_TIME_INT or SLI_PKT_IN_INT interrupt
5314 * registers. When read by a function, this register informs which rings owned by the function
5315 * (0 to N, N as large as 63) have an interrupt pending.
5316 */
5317union cvmx_sli_pkt_int {
5318 u64 u64;
5319 struct cvmx_sli_pkt_int_s {
5320 u64 ring : 64;
5321 } s;
5322 struct cvmx_sli_pkt_int_s cn73xx;
5323 struct cvmx_sli_pkt_int_s cn78xx;
5324 struct cvmx_sli_pkt_int_s cn78xxp1;
5325 struct cvmx_sli_pkt_int_s cnf75xx;
5326};
5327
5328typedef union cvmx_sli_pkt_int cvmx_sli_pkt_int_t;
5329
5330/**
5331 * cvmx_sli_pkt_int_levels
5332 *
5333 * SLI_PKT_INT_LEVELS = SLI's Packet Interrupt Levels
5334 * Output packet interrupt levels.
5335 */
5336union cvmx_sli_pkt_int_levels {
5337 u64 u64;
5338 struct cvmx_sli_pkt_int_levels_s {
5339 u64 reserved_54_63 : 10;
5340 u64 time : 22;
5341 u64 cnt : 32;
5342 } s;
5343 struct cvmx_sli_pkt_int_levels_s cn61xx;
5344 struct cvmx_sli_pkt_int_levels_s cn63xx;
5345 struct cvmx_sli_pkt_int_levels_s cn63xxp1;
5346 struct cvmx_sli_pkt_int_levels_s cn66xx;
5347 struct cvmx_sli_pkt_int_levels_s cn68xx;
5348 struct cvmx_sli_pkt_int_levels_s cn68xxp1;
5349 struct cvmx_sli_pkt_int_levels_s cn70xx;
5350 struct cvmx_sli_pkt_int_levels_s cn70xxp1;
5351 struct cvmx_sli_pkt_int_levels_s cnf71xx;
5352};
5353
5354typedef union cvmx_sli_pkt_int_levels cvmx_sli_pkt_int_levels_t;
5355
5356/**
5357 * cvmx_sli_pkt_iptr
5358 *
5359 * Controls using the Info-Pointer to store length and data.
5360 *
5361 */
5362union cvmx_sli_pkt_iptr {
5363 u64 u64;
5364 struct cvmx_sli_pkt_iptr_s {
5365 u64 reserved_32_63 : 32;
5366 u64 iptr : 32;
5367 } s;
5368 struct cvmx_sli_pkt_iptr_s cn61xx;
5369 struct cvmx_sli_pkt_iptr_s cn63xx;
5370 struct cvmx_sli_pkt_iptr_s cn63xxp1;
5371 struct cvmx_sli_pkt_iptr_s cn66xx;
5372 struct cvmx_sli_pkt_iptr_s cn68xx;
5373 struct cvmx_sli_pkt_iptr_s cn68xxp1;
5374 struct cvmx_sli_pkt_iptr_s cn70xx;
5375 struct cvmx_sli_pkt_iptr_s cn70xxp1;
5376 struct cvmx_sli_pkt_iptr_s cnf71xx;
5377};
5378
5379typedef union cvmx_sli_pkt_iptr cvmx_sli_pkt_iptr_t;
5380
5381/**
5382 * cvmx_sli_pkt_mac#_pf#_rinfo
5383 *
5384 * This register sets the total number and starting number of rings for a given MAC and PF
5385 * combination. Indexed by (MAC index) SLI_PORT_E. In SR-IOV mode, SLI_PKT_MAC()_PF()_RINFO[RPVF]
5386 * and SLI_PKT_MAC()_PF()_RINFO[NVFS] must be non zero and determine which rings the PFs and
5387 * VFs own.
5388 *
5389 * An individual VF will own SLI_PKT_MAC()_PF()_RINFO[RPVF] number of rings.
5390 *
5391 * A PF will own the rings starting from ((SLI_PKT_MAC()_PF()_RINFO[SRN] +
5392 * (SLI_PKT_MAC()_PF()_RINFO[RPVF] * SLI_PKT_MAC()_PF()_RINFO[NVFS]))
5393 * to (SLI_PKT_MAC()_PF()_RINFO[SRN] + (SLI_PKT_MAC()_PF()_RINFO[TRS] -
5394 * 1)). SLI_PKT()_INPUT_CONTROL[PVF_NUM] must be written to values that
5395 * correlate with the fields in this register.
5396 *
5397 * e.g. Given:
5398 * _ SLI_PKT_MAC0_PF0_RINFO[SRN] = 32,
5399 * _ SLI_PKT_MAC0_PF0_RINFO[TRS] = 32,
5400 * _ SLI_PKT_MAC0_PF0_RINFO[RPVF] = 4,
5401 * _ SLI_PKT_MAC0_PF0_RINFO[NVFS] = 7:
5402 * _ rings owned by VF1: 32,33,34,35
5403 * _ rings owned by VF2: 36,37,38,39
5404 * _ rings owned by VF3: 40,41,42,43
5405 * _ rings owned by VF4: 44,45,46,47
5406 * _ rings owned by VF5: 48,49,50,51
5407 * _ rings owned by VF6: 52,53,54,55
5408 * _ rings owned by VF7: 56,57,58,59
5409 * _ rings owned by PF: 60,61,62,63
5410 */
5411union cvmx_sli_pkt_macx_pfx_rinfo {
5412 u64 u64;
5413 struct cvmx_sli_pkt_macx_pfx_rinfo_s {
5414 u64 reserved_55_63 : 9;
5415 u64 nvfs : 7;
5416 u64 reserved_40_47 : 8;
5417 u64 rpvf : 8;
5418 u64 reserved_24_31 : 8;
5419 u64 trs : 8;
5420 u64 reserved_7_15 : 9;
5421 u64 srn : 7;
5422 } s;
5423 struct cvmx_sli_pkt_macx_pfx_rinfo_s cn73xx;
5424 struct cvmx_sli_pkt_macx_pfx_rinfo_s cn78xx;
5425 struct cvmx_sli_pkt_macx_pfx_rinfo_s cnf75xx;
5426};
5427
5428typedef union cvmx_sli_pkt_macx_pfx_rinfo cvmx_sli_pkt_macx_pfx_rinfo_t;
5429
5430/**
5431 * cvmx_sli_pkt_mac#_rinfo
5432 *
5433 * This register sets the total number and starting number of rings used by the MAC.
5434 * This register is PF-only.
5435 */
5436union cvmx_sli_pkt_macx_rinfo {
5437 u64 u64;
5438 struct cvmx_sli_pkt_macx_rinfo_s {
5439 u64 reserved_40_63 : 24;
5440 u64 rpvf : 8;
5441 u64 reserved_24_31 : 8;
5442 u64 trs : 8;
5443 u64 reserved_7_15 : 9;
5444 u64 srn : 7;
5445 } s;
5446 struct cvmx_sli_pkt_macx_rinfo_s cn78xxp1;
5447};
5448
5449typedef union cvmx_sli_pkt_macx_rinfo cvmx_sli_pkt_macx_rinfo_t;
5450
5451/**
5452 * cvmx_sli_pkt_mac0_sig0
5453 *
5454 * This register is used to signal between PF/VF. This register can be R/W by the PF from MAC0
5455 * and any VF.
5456 */
5457union cvmx_sli_pkt_mac0_sig0 {
5458 u64 u64;
5459 struct cvmx_sli_pkt_mac0_sig0_s {
5460 u64 data : 64;
5461 } s;
5462 struct cvmx_sli_pkt_mac0_sig0_s cn78xxp1;
5463};
5464
5465typedef union cvmx_sli_pkt_mac0_sig0 cvmx_sli_pkt_mac0_sig0_t;
5466
5467/**
5468 * cvmx_sli_pkt_mac0_sig1
5469 *
5470 * This register is used to signal between PF/VF. This register can be R/W by the PF from MAC0
5471 * and any VF.
5472 */
5473union cvmx_sli_pkt_mac0_sig1 {
5474 u64 u64;
5475 struct cvmx_sli_pkt_mac0_sig1_s {
5476 u64 data : 64;
5477 } s;
5478 struct cvmx_sli_pkt_mac0_sig1_s cn78xxp1;
5479};
5480
5481typedef union cvmx_sli_pkt_mac0_sig1 cvmx_sli_pkt_mac0_sig1_t;
5482
5483/**
5484 * cvmx_sli_pkt_mac1_sig0
5485 *
5486 * This register is used to signal between PF/VF. This register can be R/W by the PF from MAC1
5487 * and any VF.
5488 */
5489union cvmx_sli_pkt_mac1_sig0 {
5490 u64 u64;
5491 struct cvmx_sli_pkt_mac1_sig0_s {
5492 u64 data : 64;
5493 } s;
5494 struct cvmx_sli_pkt_mac1_sig0_s cn78xxp1;
5495};
5496
5497typedef union cvmx_sli_pkt_mac1_sig0 cvmx_sli_pkt_mac1_sig0_t;
5498
5499/**
5500 * cvmx_sli_pkt_mac1_sig1
5501 *
5502 * This register is used to signal between PF/VF. This register can be R/W by the PF from MAC1
5503 * and any VF.
5504 */
5505union cvmx_sli_pkt_mac1_sig1 {
5506 u64 u64;
5507 struct cvmx_sli_pkt_mac1_sig1_s {
5508 u64 data : 64;
5509 } s;
5510 struct cvmx_sli_pkt_mac1_sig1_s cn78xxp1;
5511};
5512
5513typedef union cvmx_sli_pkt_mac1_sig1 cvmx_sli_pkt_mac1_sig1_t;
5514
5515/**
5516 * cvmx_sli_pkt_mem_ctl
5517 *
5518 * This register controls the ECC of the SLI packet memories.
5519 *
5520 */
5521union cvmx_sli_pkt_mem_ctl {
5522 u64 u64;
5523 struct cvmx_sli_pkt_mem_ctl_s {
5524 u64 reserved_48_63 : 16;
5525 u64 msix_mbox_fs : 2;
5526 u64 msix_mbox_ecc : 1;
5527 u64 reserved_36_44 : 9;
5528 u64 pos_fs : 2;
5529 u64 pos_ecc : 1;
5530 u64 pinm_fs : 2;
5531 u64 pinm_ecc : 1;
5532 u64 pind_fs : 2;
5533 u64 pind_ecc : 1;
5534 u64 point_fs : 2;
5535 u64 point_ecc : 1;
5536 u64 slist_fs : 2;
5537 u64 slist_ecc : 1;
5538 u64 pop1_fs : 2;
5539 u64 pop1_ecc : 1;
5540 u64 pop0_fs : 2;
5541 u64 pop0_ecc : 1;
5542 u64 pfp_fs : 2;
5543 u64 pfp_ecc : 1;
5544 u64 pbn_fs : 2;
5545 u64 pbn_ecc : 1;
5546 u64 pdf_fs : 2;
5547 u64 pdf_ecc : 1;
5548 u64 psf_fs : 2;
5549 u64 psf_ecc : 1;
5550 u64 poi_fs : 2;
5551 u64 poi_ecc : 1;
5552 } s;
5553 struct cvmx_sli_pkt_mem_ctl_cn73xx {
5554 u64 reserved_48_63 : 16;
5555 u64 msix_mbox_fs : 2;
5556 u64 msix_mbox_ecc : 1;
5557 u64 msix_data_fs : 2;
5558 u64 msix_data_ecc : 1;
5559 u64 msix_addr_fs : 2;
5560 u64 msix_addr_ecc : 1;
5561 u64 pof_fs : 2;
5562 u64 pof_ecc : 1;
5563 u64 pos_fs : 2;
5564 u64 pos_ecc : 1;
5565 u64 pinm_fs : 2;
5566 u64 pinm_ecc : 1;
5567 u64 pind_fs : 2;
5568 u64 pind_ecc : 1;
5569 u64 point_fs : 2;
5570 u64 point_ecc : 1;
5571 u64 slist_fs : 2;
5572 u64 slist_ecc : 1;
5573 u64 pop1_fs : 2;
5574 u64 pop1_ecc : 1;
5575 u64 pop0_fs : 2;
5576 u64 pop0_ecc : 1;
5577 u64 pfp_fs : 2;
5578 u64 pfp_ecc : 1;
5579 u64 pbn_fs : 2;
5580 u64 pbn_ecc : 1;
5581 u64 pdf_fs : 2;
5582 u64 pdf_ecc : 1;
5583 u64 psf_fs : 2;
5584 u64 psf_ecc : 1;
5585 u64 poi_fs : 2;
5586 u64 poi_ecc : 1;
5587 } cn73xx;
5588 struct cvmx_sli_pkt_mem_ctl_cn73xx cn78xx;
5589 struct cvmx_sli_pkt_mem_ctl_cn78xxp1 {
5590 u64 reserved_44_63 : 20;
5591 u64 msid_fs : 2;
5592 u64 msia_fs : 2;
5593 u64 msi_ecc : 1;
5594 u64 posi_fs : 2;
5595 u64 posi_ecc : 1;
5596 u64 pos_fs : 2;
5597 u64 pos_ecc : 1;
5598 u64 pinm_fs : 2;
5599 u64 pinm_ecc : 1;
5600 u64 pind_fs : 2;
5601 u64 pind_ecc : 1;
5602 u64 point_fs : 2;
5603 u64 point_ecc : 1;
5604 u64 slist_fs : 2;
5605 u64 slist_ecc : 1;
5606 u64 pop1_fs : 2;
5607 u64 pop1_ecc : 1;
5608 u64 pop0_fs : 2;
5609 u64 pop0_ecc : 1;
5610 u64 pfp_fs : 2;
5611 u64 pfp_ecc : 1;
5612 u64 pbn_fs : 2;
5613 u64 pbn_ecc : 1;
5614 u64 pdf_fs : 2;
5615 u64 pdf_ecc : 1;
5616 u64 psf_fs : 2;
5617 u64 psf_ecc : 1;
5618 u64 poi_fs : 2;
5619 u64 poi_ecc : 1;
5620 } cn78xxp1;
5621 struct cvmx_sli_pkt_mem_ctl_cn73xx cnf75xx;
5622};
5623
5624typedef union cvmx_sli_pkt_mem_ctl cvmx_sli_pkt_mem_ctl_t;
5625
5626/**
5627 * cvmx_sli_pkt_out_bmode
5628 *
5629 * Control the updating of the SLI_PKT#_CNT register.
5630 *
5631 */
5632union cvmx_sli_pkt_out_bmode {
5633 u64 u64;
5634 struct cvmx_sli_pkt_out_bmode_s {
5635 u64 reserved_32_63 : 32;
5636 u64 bmode : 32;
5637 } s;
5638 struct cvmx_sli_pkt_out_bmode_s cn61xx;
5639 struct cvmx_sli_pkt_out_bmode_s cn63xx;
5640 struct cvmx_sli_pkt_out_bmode_s cn63xxp1;
5641 struct cvmx_sli_pkt_out_bmode_s cn66xx;
5642 struct cvmx_sli_pkt_out_bmode_s cn68xx;
5643 struct cvmx_sli_pkt_out_bmode_s cn68xxp1;
5644 struct cvmx_sli_pkt_out_bmode_s cn70xx;
5645 struct cvmx_sli_pkt_out_bmode_s cn70xxp1;
5646 struct cvmx_sli_pkt_out_bmode_s cnf71xx;
5647};
5648
5649typedef union cvmx_sli_pkt_out_bmode cvmx_sli_pkt_out_bmode_t;
5650
5651/**
5652 * cvmx_sli_pkt_out_bp_en
5653 *
5654 * This register enables sending backpressure to PKO.
5655 *
5656 */
5657union cvmx_sli_pkt_out_bp_en {
5658 u64 u64;
5659 struct cvmx_sli_pkt_out_bp_en_s {
5660 u64 bp_en : 64;
5661 } s;
5662 struct cvmx_sli_pkt_out_bp_en_cn68xx {
5663 u64 reserved_32_63 : 32;
5664 u64 bp_en : 32;
5665 } cn68xx;
5666 struct cvmx_sli_pkt_out_bp_en_cn68xx cn68xxp1;
5667 struct cvmx_sli_pkt_out_bp_en_s cn78xxp1;
5668};
5669
5670typedef union cvmx_sli_pkt_out_bp_en cvmx_sli_pkt_out_bp_en_t;
5671
5672/**
5673 * cvmx_sli_pkt_out_bp_en2_w1c
5674 *
5675 * This register disables sending backpressure to PKO.
5676 *
5677 */
5678union cvmx_sli_pkt_out_bp_en2_w1c {
5679 u64 u64;
5680 struct cvmx_sli_pkt_out_bp_en2_w1c_s {
5681 u64 w1c : 64;
5682 } s;
5683 struct cvmx_sli_pkt_out_bp_en2_w1c_s cn73xx;
5684};
5685
5686typedef union cvmx_sli_pkt_out_bp_en2_w1c cvmx_sli_pkt_out_bp_en2_w1c_t;
5687
5688/**
5689 * cvmx_sli_pkt_out_bp_en2_w1s
5690 *
5691 * This register enables sending backpressure to PKO.
5692 *
5693 */
5694union cvmx_sli_pkt_out_bp_en2_w1s {
5695 u64 u64;
5696 struct cvmx_sli_pkt_out_bp_en2_w1s_s {
5697 u64 w1s : 64;
5698 } s;
5699 struct cvmx_sli_pkt_out_bp_en2_w1s_s cn73xx;
5700};
5701
5702typedef union cvmx_sli_pkt_out_bp_en2_w1s cvmx_sli_pkt_out_bp_en2_w1s_t;
5703
5704/**
5705 * cvmx_sli_pkt_out_bp_en_w1c
5706 *
5707 * This register disables sending backpressure to PKO.
5708 *
5709 */
5710union cvmx_sli_pkt_out_bp_en_w1c {
5711 u64 u64;
5712 struct cvmx_sli_pkt_out_bp_en_w1c_s {
5713 u64 w1c : 64;
5714 } s;
5715 struct cvmx_sli_pkt_out_bp_en_w1c_s cn73xx;
5716 struct cvmx_sli_pkt_out_bp_en_w1c_s cn78xx;
5717 struct cvmx_sli_pkt_out_bp_en_w1c_s cnf75xx;
5718};
5719
5720typedef union cvmx_sli_pkt_out_bp_en_w1c cvmx_sli_pkt_out_bp_en_w1c_t;
5721
5722/**
5723 * cvmx_sli_pkt_out_bp_en_w1s
5724 *
5725 * This register enables sending backpressure to PKO.
5726 *
5727 */
5728union cvmx_sli_pkt_out_bp_en_w1s {
5729 u64 u64;
5730 struct cvmx_sli_pkt_out_bp_en_w1s_s {
5731 u64 w1s : 64;
5732 } s;
5733 struct cvmx_sli_pkt_out_bp_en_w1s_s cn73xx;
5734 struct cvmx_sli_pkt_out_bp_en_w1s_s cn78xx;
5735 struct cvmx_sli_pkt_out_bp_en_w1s_s cnf75xx;
5736};
5737
5738typedef union cvmx_sli_pkt_out_bp_en_w1s cvmx_sli_pkt_out_bp_en_w1s_t;
5739
5740/**
5741 * cvmx_sli_pkt_out_enb
5742 *
5743 * Multi-ring packet output enable register. This register is PF-only.
5744 *
5745 */
5746union cvmx_sli_pkt_out_enb {
5747 u64 u64;
5748 struct cvmx_sli_pkt_out_enb_s {
5749 u64 enb : 64;
5750 } s;
5751 struct cvmx_sli_pkt_out_enb_cn61xx {
5752 u64 reserved_32_63 : 32;
5753 u64 enb : 32;
5754 } cn61xx;
5755 struct cvmx_sli_pkt_out_enb_cn61xx cn63xx;
5756 struct cvmx_sli_pkt_out_enb_cn61xx cn63xxp1;
5757 struct cvmx_sli_pkt_out_enb_cn61xx cn66xx;
5758 struct cvmx_sli_pkt_out_enb_cn61xx cn68xx;
5759 struct cvmx_sli_pkt_out_enb_cn61xx cn68xxp1;
5760 struct cvmx_sli_pkt_out_enb_cn61xx cn70xx;
5761 struct cvmx_sli_pkt_out_enb_cn61xx cn70xxp1;
5762 struct cvmx_sli_pkt_out_enb_s cn78xxp1;
5763 struct cvmx_sli_pkt_out_enb_cn61xx cnf71xx;
5764};
5765
5766typedef union cvmx_sli_pkt_out_enb cvmx_sli_pkt_out_enb_t;
5767
5768/**
5769 * cvmx_sli_pkt_output_wmark
5770 *
5771 * This register sets the value that determines when backpressure is applied to the PKO. When
5772 * SLI_PKT()_SLIST_BAOFF_DBELL[DBELL] is less than [WMARK], backpressure is sent to PKO for
5773 * the associated channel. This register is PF-only.
5774 */
5775union cvmx_sli_pkt_output_wmark {
5776 u64 u64;
5777 struct cvmx_sli_pkt_output_wmark_s {
5778 u64 reserved_32_63 : 32;
5779 u64 wmark : 32;
5780 } s;
5781 struct cvmx_sli_pkt_output_wmark_s cn61xx;
5782 struct cvmx_sli_pkt_output_wmark_s cn63xx;
5783 struct cvmx_sli_pkt_output_wmark_s cn63xxp1;
5784 struct cvmx_sli_pkt_output_wmark_s cn66xx;
5785 struct cvmx_sli_pkt_output_wmark_s cn68xx;
5786 struct cvmx_sli_pkt_output_wmark_s cn68xxp1;
5787 struct cvmx_sli_pkt_output_wmark_s cn70xx;
5788 struct cvmx_sli_pkt_output_wmark_s cn70xxp1;
5789 struct cvmx_sli_pkt_output_wmark_s cn73xx;
5790 struct cvmx_sli_pkt_output_wmark_s cn78xx;
5791 struct cvmx_sli_pkt_output_wmark_s cn78xxp1;
5792 struct cvmx_sli_pkt_output_wmark_s cnf71xx;
5793 struct cvmx_sli_pkt_output_wmark_s cnf75xx;
5794};
5795
5796typedef union cvmx_sli_pkt_output_wmark cvmx_sli_pkt_output_wmark_t;
5797
5798/**
5799 * cvmx_sli_pkt_pcie_port
5800 *
5801 * Assigns Packet Ports to MAC ports.
5802 *
5803 */
5804union cvmx_sli_pkt_pcie_port {
5805 u64 u64;
5806 struct cvmx_sli_pkt_pcie_port_s {
5807 u64 pp : 64;
5808 } s;
5809 struct cvmx_sli_pkt_pcie_port_s cn61xx;
5810 struct cvmx_sli_pkt_pcie_port_s cn63xx;
5811 struct cvmx_sli_pkt_pcie_port_s cn63xxp1;
5812 struct cvmx_sli_pkt_pcie_port_s cn66xx;
5813 struct cvmx_sli_pkt_pcie_port_s cn68xx;
5814 struct cvmx_sli_pkt_pcie_port_s cn68xxp1;
5815 struct cvmx_sli_pkt_pcie_port_s cn70xx;
5816 struct cvmx_sli_pkt_pcie_port_s cn70xxp1;
5817 struct cvmx_sli_pkt_pcie_port_s cnf71xx;
5818};
5819
5820typedef union cvmx_sli_pkt_pcie_port cvmx_sli_pkt_pcie_port_t;
5821
5822/**
5823 * cvmx_sli_pkt_pkind_valid
5824 *
5825 * Enables bits per PKIND that are allowed to be sent to PKI specified in the
5826 * DPI_PKT_INST_HDR_S[PKIND] DPI packet instruction field.
5827 */
5828union cvmx_sli_pkt_pkind_valid {
5829 u64 u64;
5830 struct cvmx_sli_pkt_pkind_valid_s {
5831 u64 enb : 64;
5832 } s;
5833 struct cvmx_sli_pkt_pkind_valid_s cn73xx;
5834 struct cvmx_sli_pkt_pkind_valid_s cn78xx;
5835 struct cvmx_sli_pkt_pkind_valid_s cnf75xx;
5836};
5837
5838typedef union cvmx_sli_pkt_pkind_valid cvmx_sli_pkt_pkind_valid_t;
5839
5840/**
5841 * cvmx_sli_pkt_port_in_rst
5842 *
5843 * SLI_PKT_PORT_IN_RST = SLI Packet Port In Reset
5844 * Vector bits related to ring-port for ones that are reset.
5845 */
5846union cvmx_sli_pkt_port_in_rst {
5847 u64 u64;
5848 struct cvmx_sli_pkt_port_in_rst_s {
5849 u64 in_rst : 32;
5850 u64 out_rst : 32;
5851 } s;
5852 struct cvmx_sli_pkt_port_in_rst_s cn61xx;
5853 struct cvmx_sli_pkt_port_in_rst_s cn63xx;
5854 struct cvmx_sli_pkt_port_in_rst_s cn63xxp1;
5855 struct cvmx_sli_pkt_port_in_rst_s cn66xx;
5856 struct cvmx_sli_pkt_port_in_rst_s cn68xx;
5857 struct cvmx_sli_pkt_port_in_rst_s cn68xxp1;
5858 struct cvmx_sli_pkt_port_in_rst_s cn70xx;
5859 struct cvmx_sli_pkt_port_in_rst_s cn70xxp1;
5860 struct cvmx_sli_pkt_port_in_rst_s cnf71xx;
5861};
5862
5863typedef union cvmx_sli_pkt_port_in_rst cvmx_sli_pkt_port_in_rst_t;
5864
5865/**
5866 * cvmx_sli_pkt_ring_rst
5867 *
5868 * When read by a PF, this register informs which rings owned by the function (0 to N, N as large
5869 * as 63) are in reset. See also SLI_PKT()_INPUT_CONTROL[RST].
5870 */
5871union cvmx_sli_pkt_ring_rst {
5872 u64 u64;
5873 struct cvmx_sli_pkt_ring_rst_s {
5874 u64 rst : 64;
5875 } s;
5876 struct cvmx_sli_pkt_ring_rst_s cn73xx;
5877 struct cvmx_sli_pkt_ring_rst_s cn78xx;
5878 struct cvmx_sli_pkt_ring_rst_s cn78xxp1;
5879 struct cvmx_sli_pkt_ring_rst_s cnf75xx;
5880};
5881
5882typedef union cvmx_sli_pkt_ring_rst cvmx_sli_pkt_ring_rst_t;
5883
5884/**
5885 * cvmx_sli_pkt_slist_es
5886 *
5887 * The Endian Swap for Scatter List Read.
5888 *
5889 */
5890union cvmx_sli_pkt_slist_es {
5891 u64 u64;
5892 struct cvmx_sli_pkt_slist_es_s {
5893 u64 es : 64;
5894 } s;
5895 struct cvmx_sli_pkt_slist_es_s cn61xx;
5896 struct cvmx_sli_pkt_slist_es_s cn63xx;
5897 struct cvmx_sli_pkt_slist_es_s cn63xxp1;
5898 struct cvmx_sli_pkt_slist_es_s cn66xx;
5899 struct cvmx_sli_pkt_slist_es_s cn68xx;
5900 struct cvmx_sli_pkt_slist_es_s cn68xxp1;
5901 struct cvmx_sli_pkt_slist_es_s cn70xx;
5902 struct cvmx_sli_pkt_slist_es_s cn70xxp1;
5903 struct cvmx_sli_pkt_slist_es_s cnf71xx;
5904};
5905
5906typedef union cvmx_sli_pkt_slist_es cvmx_sli_pkt_slist_es_t;
5907
5908/**
5909 * cvmx_sli_pkt_slist_ns
5910 *
5911 * The NS field for the TLP when fetching Scatter List.
5912 *
5913 */
5914union cvmx_sli_pkt_slist_ns {
5915 u64 u64;
5916 struct cvmx_sli_pkt_slist_ns_s {
5917 u64 reserved_32_63 : 32;
5918 u64 nsr : 32;
5919 } s;
5920 struct cvmx_sli_pkt_slist_ns_s cn61xx;
5921 struct cvmx_sli_pkt_slist_ns_s cn63xx;
5922 struct cvmx_sli_pkt_slist_ns_s cn63xxp1;
5923 struct cvmx_sli_pkt_slist_ns_s cn66xx;
5924 struct cvmx_sli_pkt_slist_ns_s cn68xx;
5925 struct cvmx_sli_pkt_slist_ns_s cn68xxp1;
5926 struct cvmx_sli_pkt_slist_ns_s cn70xx;
5927 struct cvmx_sli_pkt_slist_ns_s cn70xxp1;
5928 struct cvmx_sli_pkt_slist_ns_s cnf71xx;
5929};
5930
5931typedef union cvmx_sli_pkt_slist_ns cvmx_sli_pkt_slist_ns_t;
5932
5933/**
5934 * cvmx_sli_pkt_slist_ror
5935 *
5936 * The ROR field for the TLP when fetching Scatter List.
5937 *
5938 */
5939union cvmx_sli_pkt_slist_ror {
5940 u64 u64;
5941 struct cvmx_sli_pkt_slist_ror_s {
5942 u64 reserved_32_63 : 32;
5943 u64 ror : 32;
5944 } s;
5945 struct cvmx_sli_pkt_slist_ror_s cn61xx;
5946 struct cvmx_sli_pkt_slist_ror_s cn63xx;
5947 struct cvmx_sli_pkt_slist_ror_s cn63xxp1;
5948 struct cvmx_sli_pkt_slist_ror_s cn66xx;
5949 struct cvmx_sli_pkt_slist_ror_s cn68xx;
5950 struct cvmx_sli_pkt_slist_ror_s cn68xxp1;
5951 struct cvmx_sli_pkt_slist_ror_s cn70xx;
5952 struct cvmx_sli_pkt_slist_ror_s cn70xxp1;
5953 struct cvmx_sli_pkt_slist_ror_s cnf71xx;
5954};
5955
5956typedef union cvmx_sli_pkt_slist_ror cvmx_sli_pkt_slist_ror_t;
5957
5958/**
5959 * cvmx_sli_pkt_time_int
5960 *
5961 * This register specifies which output packets rings are interrupting because of packet timers.
5962 * A bit set in this interrupt register will set a corresponding bit in SLI_PKT_INT and can
5963 * also cause SLI_MAC()_PF()_INT_SUM[PTIME] to be set if
5964 * SLI_PKT()_OUTPUT_CONTROL[TENB]
5965 * is set. When read by a function, this register informs which rings owned by the function (0 to
5966 * N,
5967 * N as large as 63) have this interrupt pending.
5968 */
5969union cvmx_sli_pkt_time_int {
5970 u64 u64;
5971 struct cvmx_sli_pkt_time_int_s {
5972 u64 reserved_0_63 : 64;
5973 } s;
5974 struct cvmx_sli_pkt_time_int_cn61xx {
5975 u64 reserved_32_63 : 32;
5976 u64 port : 32;
5977 } cn61xx;
5978 struct cvmx_sli_pkt_time_int_cn61xx cn63xx;
5979 struct cvmx_sli_pkt_time_int_cn61xx cn63xxp1;
5980 struct cvmx_sli_pkt_time_int_cn61xx cn66xx;
5981 struct cvmx_sli_pkt_time_int_cn61xx cn68xx;
5982 struct cvmx_sli_pkt_time_int_cn61xx cn68xxp1;
5983 struct cvmx_sli_pkt_time_int_cn61xx cn70xx;
5984 struct cvmx_sli_pkt_time_int_cn61xx cn70xxp1;
5985 struct cvmx_sli_pkt_time_int_cn73xx {
5986 u64 ring : 64;
5987 } cn73xx;
5988 struct cvmx_sli_pkt_time_int_cn73xx cn78xx;
5989 struct cvmx_sli_pkt_time_int_cn73xx cn78xxp1;
5990 struct cvmx_sli_pkt_time_int_cn61xx cnf71xx;
5991 struct cvmx_sli_pkt_time_int_cn73xx cnf75xx;
5992};
5993
5994typedef union cvmx_sli_pkt_time_int cvmx_sli_pkt_time_int_t;
5995
5996/**
5997 * cvmx_sli_pkt_time_int_enb
5998 *
5999 * The packets rings that are interrupting because of Packet Timers.
6000 *
6001 */
6002union cvmx_sli_pkt_time_int_enb {
6003 u64 u64;
6004 struct cvmx_sli_pkt_time_int_enb_s {
6005 u64 reserved_32_63 : 32;
6006 u64 port : 32;
6007 } s;
6008 struct cvmx_sli_pkt_time_int_enb_s cn61xx;
6009 struct cvmx_sli_pkt_time_int_enb_s cn63xx;
6010 struct cvmx_sli_pkt_time_int_enb_s cn63xxp1;
6011 struct cvmx_sli_pkt_time_int_enb_s cn66xx;
6012 struct cvmx_sli_pkt_time_int_enb_s cn68xx;
6013 struct cvmx_sli_pkt_time_int_enb_s cn68xxp1;
6014 struct cvmx_sli_pkt_time_int_enb_s cn70xx;
6015 struct cvmx_sli_pkt_time_int_enb_s cn70xxp1;
6016 struct cvmx_sli_pkt_time_int_enb_s cnf71xx;
6017};
6018
6019typedef union cvmx_sli_pkt_time_int_enb cvmx_sli_pkt_time_int_enb_t;
6020
6021/**
6022 * cvmx_sli_port#_pkind
6023 *
6024 * SLI_PORT[0..31]_PKIND = SLI Port Pkind
6025 *
6026 * The SLI/DPI supports 32 input rings for fetching input packets. This register maps the input-rings (0-31) to a PKIND.
6027 */
6028union cvmx_sli_portx_pkind {
6029 u64 u64;
6030 struct cvmx_sli_portx_pkind_s {
6031 u64 reserved_25_63 : 39;
6032 u64 rpk_enb : 1;
6033 u64 reserved_22_23 : 2;
6034 u64 pkindr : 6;
6035 u64 reserved_14_15 : 2;
6036 u64 bpkind : 6;
6037 u64 reserved_6_7 : 2;
6038 u64 pkind : 6;
6039 } s;
6040 struct cvmx_sli_portx_pkind_s cn68xx;
6041 struct cvmx_sli_portx_pkind_cn68xxp1 {
6042 u64 reserved_14_63 : 50;
6043 u64 bpkind : 6;
6044 u64 reserved_6_7 : 2;
6045 u64 pkind : 6;
6046 } cn68xxp1;
6047};
6048
6049typedef union cvmx_sli_portx_pkind cvmx_sli_portx_pkind_t;
6050
6051/**
6052 * cvmx_sli_pp_pkt_csr_control
6053 *
6054 * This register provides access to SLI packet register space from the cores.
6055 * These SLI packet registers include the following:
6056 * SLI_MSIXX_TABLE_ADDR,
6057 * SLI_MSIXX_TABLE_DATA,
6058 * SLI_MSIX_PBA0,
6059 * SLI_MSIX_PBA1,
6060 * SLI_PKTX_INPUT_CONTROL,
6061 * SLI_PKTX_INSTR_BADDR,
6062 * SLI_PKTX_INSTR_BAOFF_DBELL,
6063 * SLI_PKTX_INSTR_FIFO_RSIZE,
6064 * SLI_PKT_IN_DONEX_CNTS,
6065 * SLI_PKTX_OUTPUT_CONTROL,
6066 * SLI_PKTX_OUT_SIZE,
6067 * SLI_PKTX_SLIST_BADDR,
6068 * SLI_PKTX_SLIST_BAOFF_DBELL,
6069 * SLI_PKTX_SLIST_FIFO_RSIZE,
6070 * SLI_PKTX_INT_LEVELS,
6071 * SLI_PKTX_CNTS,
6072 * SLI_PKTX_ERROR_INFO,
6073 * SLI_PKTX_VF_INT_SUM,
6074 * SLI_PKTX_PF_VF_MBOX_SIG,
6075 * SLI_PKTX_MBOX_INT.
6076 */
6077union cvmx_sli_pp_pkt_csr_control {
6078 u64 u64;
6079 struct cvmx_sli_pp_pkt_csr_control_s {
6080 u64 reserved_18_63 : 46;
6081 u64 mac : 2;
6082 u64 pvf : 16;
6083 } s;
6084 struct cvmx_sli_pp_pkt_csr_control_s cn73xx;
6085 struct cvmx_sli_pp_pkt_csr_control_s cn78xx;
6086 struct cvmx_sli_pp_pkt_csr_control_s cnf75xx;
6087};
6088
6089typedef union cvmx_sli_pp_pkt_csr_control cvmx_sli_pp_pkt_csr_control_t;
6090
6091/**
6092 * cvmx_sli_s2c_end_merge
6093 *
6094 * Writing this register will cause a merge to end.
6095 *
6096 */
6097union cvmx_sli_s2c_end_merge {
6098 u64 u64;
6099 struct cvmx_sli_s2c_end_merge_s {
6100 u64 reserved_0_63 : 64;
6101 } s;
6102 struct cvmx_sli_s2c_end_merge_s cn73xx;
6103 struct cvmx_sli_s2c_end_merge_s cn78xx;
6104 struct cvmx_sli_s2c_end_merge_s cn78xxp1;
6105 struct cvmx_sli_s2c_end_merge_s cnf75xx;
6106};
6107
6108typedef union cvmx_sli_s2c_end_merge cvmx_sli_s2c_end_merge_t;
6109
6110/**
6111 * cvmx_sli_s2m_port#_ctl
6112 *
6113 * These registers contain control for access from SLI to a MAC port. Indexed by SLI_PORT_E.
6114 * Write operations to these registers are not ordered with write/read operations to the MAC
6115 * memory space. To ensure that a write operation has completed, read the register before
6116 * making an access (i.e. MAC memory space) that requires the value of this register to be
6117 * updated.
6118 */
6119union cvmx_sli_s2m_portx_ctl {
6120 u64 u64;
6121 struct cvmx_sli_s2m_portx_ctl_s {
6122 u64 reserved_7_63 : 57;
6123 u64 dvferr : 1;
6124 u64 lcl_node : 1;
6125 u64 wind_d : 1;
6126 u64 bar0_d : 1;
6127 u64 reserved_0_2 : 3;
6128 } s;
6129 struct cvmx_sli_s2m_portx_ctl_cn61xx {
6130 u64 reserved_5_63 : 59;
6131 u64 wind_d : 1;
6132 u64 bar0_d : 1;
6133 u64 mrrs : 3;
6134 } cn61xx;
6135 struct cvmx_sli_s2m_portx_ctl_cn61xx cn63xx;
6136 struct cvmx_sli_s2m_portx_ctl_cn61xx cn63xxp1;
6137 struct cvmx_sli_s2m_portx_ctl_cn61xx cn66xx;
6138 struct cvmx_sli_s2m_portx_ctl_cn61xx cn68xx;
6139 struct cvmx_sli_s2m_portx_ctl_cn61xx cn68xxp1;
6140 struct cvmx_sli_s2m_portx_ctl_cn61xx cn70xx;
6141 struct cvmx_sli_s2m_portx_ctl_cn61xx cn70xxp1;
6142 struct cvmx_sli_s2m_portx_ctl_cn73xx {
6143 u64 reserved_7_63 : 57;
6144 u64 dvferr : 1;
6145 u64 lcl_node : 1;
6146 u64 wind_d : 1;
6147 u64 bar0_d : 1;
6148 u64 ld_cmd : 2;
6149 u64 reserved_0_0 : 1;
6150 } cn73xx;
6151 struct cvmx_sli_s2m_portx_ctl_cn73xx cn78xx;
6152 struct cvmx_sli_s2m_portx_ctl_cn78xxp1 {
6153 u64 reserved_6_63 : 58;
6154 u64 lcl_node : 1;
6155 u64 wind_d : 1;
6156 u64 bar0_d : 1;
6157 u64 ld_cmd : 2;
6158 u64 reserved_0_0 : 1;
6159 } cn78xxp1;
6160 struct cvmx_sli_s2m_portx_ctl_cn61xx cnf71xx;
6161 struct cvmx_sli_s2m_portx_ctl_cn73xx cnf75xx;
6162};
6163
6164typedef union cvmx_sli_s2m_portx_ctl cvmx_sli_s2m_portx_ctl_t;
6165
6166/**
6167 * cvmx_sli_scratch_1
6168 *
6169 * This registers is a general purpose 64-bit scratch register for software use.
6170 *
6171 */
6172union cvmx_sli_scratch_1 {
6173 u64 u64;
6174 struct cvmx_sli_scratch_1_s {
6175 u64 data : 64;
6176 } s;
6177 struct cvmx_sli_scratch_1_s cn61xx;
6178 struct cvmx_sli_scratch_1_s cn63xx;
6179 struct cvmx_sli_scratch_1_s cn63xxp1;
6180 struct cvmx_sli_scratch_1_s cn66xx;
6181 struct cvmx_sli_scratch_1_s cn68xx;
6182 struct cvmx_sli_scratch_1_s cn68xxp1;
6183 struct cvmx_sli_scratch_1_s cn70xx;
6184 struct cvmx_sli_scratch_1_s cn70xxp1;
6185 struct cvmx_sli_scratch_1_s cn73xx;
6186 struct cvmx_sli_scratch_1_s cn78xx;
6187 struct cvmx_sli_scratch_1_s cn78xxp1;
6188 struct cvmx_sli_scratch_1_s cnf71xx;
6189 struct cvmx_sli_scratch_1_s cnf75xx;
6190};
6191
6192typedef union cvmx_sli_scratch_1 cvmx_sli_scratch_1_t;
6193
6194/**
6195 * cvmx_sli_scratch_2
6196 *
6197 * This registers is a general purpose 64-bit scratch register for software use.
6198 *
6199 */
6200union cvmx_sli_scratch_2 {
6201 u64 u64;
6202 struct cvmx_sli_scratch_2_s {
6203 u64 data : 64;
6204 } s;
6205 struct cvmx_sli_scratch_2_s cn61xx;
6206 struct cvmx_sli_scratch_2_s cn63xx;
6207 struct cvmx_sli_scratch_2_s cn63xxp1;
6208 struct cvmx_sli_scratch_2_s cn66xx;
6209 struct cvmx_sli_scratch_2_s cn68xx;
6210 struct cvmx_sli_scratch_2_s cn68xxp1;
6211 struct cvmx_sli_scratch_2_s cn70xx;
6212 struct cvmx_sli_scratch_2_s cn70xxp1;
6213 struct cvmx_sli_scratch_2_s cn73xx;
6214 struct cvmx_sli_scratch_2_s cn78xx;
6215 struct cvmx_sli_scratch_2_s cn78xxp1;
6216 struct cvmx_sli_scratch_2_s cnf71xx;
6217 struct cvmx_sli_scratch_2_s cnf75xx;
6218};
6219
6220typedef union cvmx_sli_scratch_2 cvmx_sli_scratch_2_t;
6221
6222/**
6223 * cvmx_sli_state1
6224 *
6225 * This register contains state machines in SLI and is for debug.
6226 *
6227 */
6228union cvmx_sli_state1 {
6229 u64 u64;
6230 struct cvmx_sli_state1_s {
6231 u64 cpl1 : 12;
6232 u64 cpl0 : 12;
6233 u64 arb : 1;
6234 u64 csr : 39;
6235 } s;
6236 struct cvmx_sli_state1_s cn61xx;
6237 struct cvmx_sli_state1_s cn63xx;
6238 struct cvmx_sli_state1_s cn63xxp1;
6239 struct cvmx_sli_state1_s cn66xx;
6240 struct cvmx_sli_state1_s cn68xx;
6241 struct cvmx_sli_state1_s cn68xxp1;
6242 struct cvmx_sli_state1_s cn70xx;
6243 struct cvmx_sli_state1_s cn70xxp1;
6244 struct cvmx_sli_state1_s cn73xx;
6245 struct cvmx_sli_state1_s cn78xx;
6246 struct cvmx_sli_state1_s cn78xxp1;
6247 struct cvmx_sli_state1_s cnf71xx;
6248 struct cvmx_sli_state1_s cnf75xx;
6249};
6250
6251typedef union cvmx_sli_state1 cvmx_sli_state1_t;
6252
6253/**
6254 * cvmx_sli_state2
6255 *
6256 * This register contains state machines in SLI and is for debug.
6257 *
6258 */
6259union cvmx_sli_state2 {
6260 u64 u64;
6261 struct cvmx_sli_state2_s {
6262 u64 reserved_0_63 : 64;
6263 } s;
6264 struct cvmx_sli_state2_cn61xx {
6265 u64 reserved_56_63 : 8;
6266 u64 nnp1 : 8;
6267 u64 reserved_47_47 : 1;
6268 u64 rac : 1;
6269 u64 csm1 : 15;
6270 u64 csm0 : 15;
6271 u64 nnp0 : 8;
6272 u64 nnd : 8;
6273 } cn61xx;
6274 struct cvmx_sli_state2_cn61xx cn63xx;
6275 struct cvmx_sli_state2_cn61xx cn63xxp1;
6276 struct cvmx_sli_state2_cn61xx cn66xx;
6277 struct cvmx_sli_state2_cn61xx cn68xx;
6278 struct cvmx_sli_state2_cn61xx cn68xxp1;
6279 struct cvmx_sli_state2_cn61xx cn70xx;
6280 struct cvmx_sli_state2_cn61xx cn70xxp1;
6281 struct cvmx_sli_state2_cn73xx {
6282 u64 reserved_57_63 : 7;
6283 u64 nnp1 : 8;
6284 u64 reserved_48_48 : 1;
6285 u64 rac : 1;
6286 u64 csm1 : 15;
6287 u64 csm0 : 15;
6288 u64 nnp0 : 8;
6289 u64 nnd : 9;
6290 } cn73xx;
6291 struct cvmx_sli_state2_cn73xx cn78xx;
6292 struct cvmx_sli_state2_cn73xx cn78xxp1;
6293 struct cvmx_sli_state2_cn61xx cnf71xx;
6294 struct cvmx_sli_state2_cn73xx cnf75xx;
6295};
6296
6297typedef union cvmx_sli_state2 cvmx_sli_state2_t;
6298
6299/**
6300 * cvmx_sli_state3
6301 *
6302 * This register contains state machines in SLI and is for debug.
6303 *
6304 */
6305union cvmx_sli_state3 {
6306 u64 u64;
6307 struct cvmx_sli_state3_s {
6308 u64 reserved_0_63 : 64;
6309 } s;
6310 struct cvmx_sli_state3_cn61xx {
6311 u64 reserved_56_63 : 8;
6312 u64 psm1 : 15;
6313 u64 psm0 : 15;
6314 u64 nsm1 : 13;
6315 u64 nsm0 : 13;
6316 } cn61xx;
6317 struct cvmx_sli_state3_cn61xx cn63xx;
6318 struct cvmx_sli_state3_cn61xx cn63xxp1;
6319 struct cvmx_sli_state3_cn61xx cn66xx;
6320 struct cvmx_sli_state3_cn61xx cn68xx;
6321 struct cvmx_sli_state3_cn61xx cn68xxp1;
6322 struct cvmx_sli_state3_cn61xx cn70xx;
6323 struct cvmx_sli_state3_cn61xx cn70xxp1;
6324 struct cvmx_sli_state3_cn73xx {
6325 u64 reserved_60_63 : 4;
6326 u64 psm1 : 15;
6327 u64 psm0 : 15;
6328 u64 nsm1 : 15;
6329 u64 nsm0 : 15;
6330 } cn73xx;
6331 struct cvmx_sli_state3_cn73xx cn78xx;
6332 struct cvmx_sli_state3_cn73xx cn78xxp1;
6333 struct cvmx_sli_state3_cn61xx cnf71xx;
6334 struct cvmx_sli_state3_cn73xx cnf75xx;
6335};
6336
6337typedef union cvmx_sli_state3 cvmx_sli_state3_t;
6338
6339/**
6340 * cvmx_sli_tx_pipe
6341 *
6342 * SLI_TX_PIPE = SLI Packet TX Pipe
6343 *
6344 * Contains the starting pipe number and number of pipes used by the SLI packet Output.
6345 * If a packet is recevied from PKO with an out of range PIPE number, the following occurs:
6346 * - SLI_INT_SUM[PIPE_ERR] is set.
6347 * - the out of range pipe value is used for returning credits to the PKO.
6348 * - the PCIe packet engine will treat the PIPE value to be equal to [BASE].
6349 */
6350union cvmx_sli_tx_pipe {
6351 u64 u64;
6352 struct cvmx_sli_tx_pipe_s {
6353 u64 reserved_24_63 : 40;
6354 u64 nump : 8;
6355 u64 reserved_7_15 : 9;
6356 u64 base : 7;
6357 } s;
6358 struct cvmx_sli_tx_pipe_s cn68xx;
6359 struct cvmx_sli_tx_pipe_s cn68xxp1;
6360};
6361
6362typedef union cvmx_sli_tx_pipe cvmx_sli_tx_pipe_t;
6363
6364/**
6365 * cvmx_sli_win_rd_addr
6366 *
6367 * When the LSB of this register is written, the address in this register will be read. The data
6368 * returned from this read operation is placed in the WIN_RD_DATA register. This register should
6369 * NOT
6370 * be used to read SLI_* registers.
6371 */
6372union cvmx_sli_win_rd_addr {
6373 u64 u64;
6374 struct cvmx_sli_win_rd_addr_s {
6375 u64 reserved_51_63 : 13;
6376 u64 ld_cmd : 2;
6377 u64 iobit : 1;
6378 u64 rd_addr : 48;
6379 } s;
6380 struct cvmx_sli_win_rd_addr_s cn61xx;
6381 struct cvmx_sli_win_rd_addr_s cn63xx;
6382 struct cvmx_sli_win_rd_addr_s cn63xxp1;
6383 struct cvmx_sli_win_rd_addr_s cn66xx;
6384 struct cvmx_sli_win_rd_addr_s cn68xx;
6385 struct cvmx_sli_win_rd_addr_s cn68xxp1;
6386 struct cvmx_sli_win_rd_addr_s cn70xx;
6387 struct cvmx_sli_win_rd_addr_s cn70xxp1;
6388 struct cvmx_sli_win_rd_addr_s cn73xx;
6389 struct cvmx_sli_win_rd_addr_s cn78xx;
6390 struct cvmx_sli_win_rd_addr_s cn78xxp1;
6391 struct cvmx_sli_win_rd_addr_s cnf71xx;
6392 struct cvmx_sli_win_rd_addr_s cnf75xx;
6393};
6394
6395typedef union cvmx_sli_win_rd_addr cvmx_sli_win_rd_addr_t;
6396
6397/**
6398 * cvmx_sli_win_rd_data
6399 *
6400 * This register holds the data returned when a read operation is started by the writing of the
6401 * SLI_WIN_RD_ADDR register.
6402 */
6403union cvmx_sli_win_rd_data {
6404 u64 u64;
6405 struct cvmx_sli_win_rd_data_s {
6406 u64 rd_data : 64;
6407 } s;
6408 struct cvmx_sli_win_rd_data_s cn61xx;
6409 struct cvmx_sli_win_rd_data_s cn63xx;
6410 struct cvmx_sli_win_rd_data_s cn63xxp1;
6411 struct cvmx_sli_win_rd_data_s cn66xx;
6412 struct cvmx_sli_win_rd_data_s cn68xx;
6413 struct cvmx_sli_win_rd_data_s cn68xxp1;
6414 struct cvmx_sli_win_rd_data_s cn70xx;
6415 struct cvmx_sli_win_rd_data_s cn70xxp1;
6416 struct cvmx_sli_win_rd_data_s cn73xx;
6417 struct cvmx_sli_win_rd_data_s cn78xx;
6418 struct cvmx_sli_win_rd_data_s cn78xxp1;
6419 struct cvmx_sli_win_rd_data_s cnf71xx;
6420 struct cvmx_sli_win_rd_data_s cnf75xx;
6421};
6422
6423typedef union cvmx_sli_win_rd_data cvmx_sli_win_rd_data_t;
6424
6425/**
6426 * cvmx_sli_win_wr_addr
6427 *
6428 * This register contains the address to be written to when a write operation is started by
6429 * writing the SLI_WIN_WR_DATA register.
6430 *
6431 * This register should NOT be used to write SLI_* registers.
6432 */
6433union cvmx_sli_win_wr_addr {
6434 u64 u64;
6435 struct cvmx_sli_win_wr_addr_s {
6436 u64 reserved_49_63 : 15;
6437 u64 iobit : 1;
6438 u64 wr_addr : 45;
6439 u64 reserved_0_2 : 3;
6440 } s;
6441 struct cvmx_sli_win_wr_addr_s cn61xx;
6442 struct cvmx_sli_win_wr_addr_s cn63xx;
6443 struct cvmx_sli_win_wr_addr_s cn63xxp1;
6444 struct cvmx_sli_win_wr_addr_s cn66xx;
6445 struct cvmx_sli_win_wr_addr_s cn68xx;
6446 struct cvmx_sli_win_wr_addr_s cn68xxp1;
6447 struct cvmx_sli_win_wr_addr_s cn70xx;
6448 struct cvmx_sli_win_wr_addr_s cn70xxp1;
6449 struct cvmx_sli_win_wr_addr_s cn73xx;
6450 struct cvmx_sli_win_wr_addr_s cn78xx;
6451 struct cvmx_sli_win_wr_addr_s cn78xxp1;
6452 struct cvmx_sli_win_wr_addr_s cnf71xx;
6453 struct cvmx_sli_win_wr_addr_s cnf75xx;
6454};
6455
6456typedef union cvmx_sli_win_wr_addr cvmx_sli_win_wr_addr_t;
6457
6458/**
6459 * cvmx_sli_win_wr_data
6460 *
6461 * This register contains the data to write to the address located in the SLI_WIN_WR_ADDR
6462 * register. Writing the least-significant byte of this register causes a write operation to take
6463 * place.
6464 */
6465union cvmx_sli_win_wr_data {
6466 u64 u64;
6467 struct cvmx_sli_win_wr_data_s {
6468 u64 wr_data : 64;
6469 } s;
6470 struct cvmx_sli_win_wr_data_s cn61xx;
6471 struct cvmx_sli_win_wr_data_s cn63xx;
6472 struct cvmx_sli_win_wr_data_s cn63xxp1;
6473 struct cvmx_sli_win_wr_data_s cn66xx;
6474 struct cvmx_sli_win_wr_data_s cn68xx;
6475 struct cvmx_sli_win_wr_data_s cn68xxp1;
6476 struct cvmx_sli_win_wr_data_s cn70xx;
6477 struct cvmx_sli_win_wr_data_s cn70xxp1;
6478 struct cvmx_sli_win_wr_data_s cn73xx;
6479 struct cvmx_sli_win_wr_data_s cn78xx;
6480 struct cvmx_sli_win_wr_data_s cn78xxp1;
6481 struct cvmx_sli_win_wr_data_s cnf71xx;
6482 struct cvmx_sli_win_wr_data_s cnf75xx;
6483};
6484
6485typedef union cvmx_sli_win_wr_data cvmx_sli_win_wr_data_t;
6486
6487/**
6488 * cvmx_sli_win_wr_mask
6489 *
6490 * This register contains the mask for the data in the SLI_WIN_WR_DATA register.
6491 *
6492 */
6493union cvmx_sli_win_wr_mask {
6494 u64 u64;
6495 struct cvmx_sli_win_wr_mask_s {
6496 u64 reserved_8_63 : 56;
6497 u64 wr_mask : 8;
6498 } s;
6499 struct cvmx_sli_win_wr_mask_s cn61xx;
6500 struct cvmx_sli_win_wr_mask_s cn63xx;
6501 struct cvmx_sli_win_wr_mask_s cn63xxp1;
6502 struct cvmx_sli_win_wr_mask_s cn66xx;
6503 struct cvmx_sli_win_wr_mask_s cn68xx;
6504 struct cvmx_sli_win_wr_mask_s cn68xxp1;
6505 struct cvmx_sli_win_wr_mask_s cn70xx;
6506 struct cvmx_sli_win_wr_mask_s cn70xxp1;
6507 struct cvmx_sli_win_wr_mask_s cn73xx;
6508 struct cvmx_sli_win_wr_mask_s cn78xx;
6509 struct cvmx_sli_win_wr_mask_s cn78xxp1;
6510 struct cvmx_sli_win_wr_mask_s cnf71xx;
6511 struct cvmx_sli_win_wr_mask_s cnf75xx;
6512};
6513
6514typedef union cvmx_sli_win_wr_mask cvmx_sli_win_wr_mask_t;
6515
6516/**
6517 * cvmx_sli_window_ctl
6518 *
6519 * Access to register space on the IOI (caused by window read/write operations) waits for a
6520 * period of time specified by this register before timing out.
6521 */
6522union cvmx_sli_window_ctl {
6523 u64 u64;
6524 struct cvmx_sli_window_ctl_s {
6525 u64 ocx_time : 32;
6526 u64 time : 32;
6527 } s;
6528 struct cvmx_sli_window_ctl_cn61xx {
6529 u64 reserved_32_63 : 32;
6530 u64 time : 32;
6531 } cn61xx;
6532 struct cvmx_sli_window_ctl_cn61xx cn63xx;
6533 struct cvmx_sli_window_ctl_cn61xx cn63xxp1;
6534 struct cvmx_sli_window_ctl_cn61xx cn66xx;
6535 struct cvmx_sli_window_ctl_cn61xx cn68xx;
6536 struct cvmx_sli_window_ctl_cn61xx cn68xxp1;
6537 struct cvmx_sli_window_ctl_cn61xx cn70xx;
6538 struct cvmx_sli_window_ctl_cn61xx cn70xxp1;
6539 struct cvmx_sli_window_ctl_s cn73xx;
6540 struct cvmx_sli_window_ctl_s cn78xx;
6541 struct cvmx_sli_window_ctl_s cn78xxp1;
6542 struct cvmx_sli_window_ctl_cn61xx cnf71xx;
6543 struct cvmx_sli_window_ctl_s cnf75xx;
6544};
6545
6546typedef union cvmx_sli_window_ctl cvmx_sli_window_ctl_t;
6547
6548#endif