Aaron Williams | 4fd1e55 | 2021-04-23 19:56:32 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright (C) 2020 Marvell International Ltd. |
| 4 | */ |
| 5 | |
| 6 | #ifndef __CVMX_PKO3_QUEUE_H__ |
| 7 | #define __CVMX_PKO3_QUEUE_H__ |
| 8 | |
| 9 | /** |
| 10 | * @INTERNAL |
| 11 | * |
| 12 | * Find or allocate global port/dq map table |
| 13 | * which is a named table, contains entries for |
| 14 | * all possible OCI nodes. |
| 15 | * |
| 16 | * The table global pointer is stored in core-local variable |
| 17 | * so that every core will call this function once, on first use. |
| 18 | */ |
| 19 | int __cvmx_pko3_dq_table_setup(void); |
| 20 | |
| 21 | /* |
| 22 | * Get the base Descriptor Queue number for an IPD port on the local node |
| 23 | */ |
| 24 | int cvmx_pko3_get_queue_base(int ipd_port); |
| 25 | |
| 26 | /* |
| 27 | * Get the number of Descriptor Queues assigned for an IPD port |
| 28 | */ |
| 29 | int cvmx_pko3_get_queue_num(int ipd_port); |
| 30 | |
| 31 | /** |
| 32 | * Get L1/Port Queue number assigned to interface port. |
| 33 | * |
| 34 | * @param xiface is interface number. |
| 35 | * @param index is port index. |
| 36 | */ |
| 37 | int cvmx_pko3_get_port_queue(int xiface, int index); |
| 38 | |
| 39 | /* |
| 40 | * Configure L3 through L5 Scheduler Queues and Descriptor Queues |
| 41 | * |
| 42 | * The Scheduler Queues in Levels 3 to 5 and Descriptor Queues are |
| 43 | * configured one-to-one or many-to-one to a single parent Scheduler |
| 44 | * Queues. The level of the parent SQ is specified in an argument, |
| 45 | * as well as the number of children to attach to the specific parent. |
| 46 | * The children can have fair round-robin or priority-based scheduling |
| 47 | * when multiple children are assigned a single parent. |
| 48 | * |
| 49 | * @param node is the OCI node location for the queues to be configured |
| 50 | * @param parent_level is the level of the parent queue, 2 to 5. |
| 51 | * @param parent_queue is the number of the parent Scheduler Queue |
| 52 | * @param child_base is the number of the first child SQ or DQ to assign to |
| 53 | * @param parent |
| 54 | * @param child_count is the number of consecutive children to assign |
| 55 | * @param stat_prio_count is the priority setting for the children L2 SQs |
| 56 | * |
| 57 | * If <stat_prio_count> is -1, the Ln children will have equal Round-Robin |
| 58 | * relationship with eachother. If <stat_prio_count> is 0, all Ln children |
| 59 | * will be arranged in Weighted-Round-Robin, with the first having the most |
| 60 | * precedence. If <stat_prio_count> is between 1 and 8, it indicates how |
| 61 | * many children will have static priority settings (with the first having |
| 62 | * the most precedence), with the remaining Ln children having WRR scheduling. |
| 63 | * |
| 64 | * @returns 0 on success, -1 on failure. |
| 65 | * |
| 66 | * Note: this function supports the configuration of node-local unit. |
| 67 | */ |
| 68 | int cvmx_pko3_sq_config_children(unsigned int node, unsigned int parent_level, |
| 69 | unsigned int parent_queue, unsigned int child_base, |
| 70 | unsigned int child_count, int stat_prio_count); |
| 71 | |
| 72 | /* |
| 73 | * @INTERNAL |
| 74 | * Register a range of Descriptor Queues wth an interface port |
| 75 | * |
| 76 | * This function poulates the DQ-to-IPD translation table |
| 77 | * used by the application to retrieve the DQ range (typically ordered |
| 78 | * by priority) for a given IPD-port, which is either a physical port, |
| 79 | * or a channel on a channelized interface (i.e. ILK). |
| 80 | * |
| 81 | * @param xiface is the physical interface number |
| 82 | * @param index is either a physical port on an interface |
| 83 | * @param or a channel of an ILK interface |
| 84 | * @param dq_base is the first Descriptor Queue number in a consecutive range |
| 85 | * @param dq_count is the number of consecutive Descriptor Queues leading |
| 86 | * @param the same channel or port. |
| 87 | * |
| 88 | * Only a consecurive range of Descriptor Queues can be associated with any |
| 89 | * given channel/port, and usually they are ordered from most to least |
| 90 | * in terms of scheduling priority. |
| 91 | * |
| 92 | * Note: thus function only populates the node-local translation table. |
| 93 | * |
| 94 | * @returns 0 on success, -1 on failure. |
| 95 | */ |
| 96 | int __cvmx_pko3_ipd_dq_register(int xiface, int index, unsigned int dq_base, unsigned int dq_count); |
| 97 | |
| 98 | /** |
| 99 | * @INTERNAL |
| 100 | * |
| 101 | * Unregister DQs associated with CHAN_E (IPD port) |
| 102 | */ |
| 103 | int __cvmx_pko3_ipd_dq_unregister(int xiface, int index); |
| 104 | |
| 105 | /* |
| 106 | * Map channel number in PKO |
| 107 | * |
| 108 | * @param node is to specify the node to which this configuration is applied. |
| 109 | * @param pq_num specifies the Port Queue (i.e. L1) queue number. |
| 110 | * @param l2_l3_q_num specifies L2/L3 queue number. |
| 111 | * @param channel specifies the channel number to map to the queue. |
| 112 | * |
| 113 | * The channel assignment applies to L2 or L3 Shaper Queues depending |
| 114 | * on the setting of channel credit level. |
| 115 | * |
Heinrich Schuchardt | 47b4c02 | 2022-01-19 18:05:50 +0100 | [diff] [blame] | 116 | * Return: returns none. |
Aaron Williams | 4fd1e55 | 2021-04-23 19:56:32 +0200 | [diff] [blame] | 117 | */ |
| 118 | void cvmx_pko3_map_channel(unsigned int node, unsigned int pq_num, unsigned int l2_l3_q_num, |
| 119 | u16 channel); |
| 120 | |
| 121 | int cvmx_pko3_pq_config(unsigned int node, unsigned int mac_num, unsigned int pq_num); |
| 122 | |
| 123 | int cvmx_pko3_port_cir_set(unsigned int node, unsigned int pq_num, unsigned long rate_kbips, |
| 124 | unsigned int burst_bytes, int adj_bytes); |
| 125 | int cvmx_pko3_dq_cir_set(unsigned int node, unsigned int pq_num, unsigned long rate_kbips, |
| 126 | unsigned int burst_bytes); |
| 127 | int cvmx_pko3_dq_pir_set(unsigned int node, unsigned int pq_num, unsigned long rate_kbips, |
| 128 | unsigned int burst_bytes); |
| 129 | typedef enum { |
| 130 | CVMX_PKO3_SHAPE_RED_STALL, |
| 131 | CVMX_PKO3_SHAPE_RED_DISCARD, |
| 132 | CVMX_PKO3_SHAPE_RED_PASS |
| 133 | } red_action_t; |
| 134 | |
| 135 | void cvmx_pko3_dq_red(unsigned int node, unsigned int dq_num, red_action_t red_act, |
| 136 | int8_t len_adjust); |
| 137 | |
| 138 | /** |
| 139 | * Macros to deal with short floating point numbers, |
| 140 | * where unsigned exponent, and an unsigned normalized |
| 141 | * mantissa are represented each with a defined field width. |
| 142 | * |
| 143 | */ |
| 144 | #define CVMX_SHOFT_MANT_BITS 8 |
| 145 | #define CVMX_SHOFT_EXP_BITS 4 |
| 146 | |
| 147 | /** |
| 148 | * Convert short-float to an unsigned integer |
| 149 | * Note that it will lose precision. |
| 150 | */ |
| 151 | #define CVMX_SHOFT_TO_U64(m, e) \ |
| 152 | ((((1ull << CVMX_SHOFT_MANT_BITS) | (m)) << (e)) >> CVMX_SHOFT_MANT_BITS) |
| 153 | |
| 154 | /** |
| 155 | * Convert to short-float from an unsigned integer |
| 156 | */ |
| 157 | #define CVMX_SHOFT_FROM_U64(ui, m, e) \ |
| 158 | do { \ |
| 159 | unsigned long long u; \ |
| 160 | unsigned int k; \ |
| 161 | k = (1ull << (CVMX_SHOFT_MANT_BITS + 1)) - 1; \ |
| 162 | (e) = 0; \ |
| 163 | u = (ui) << CVMX_SHOFT_MANT_BITS; \ |
| 164 | while ((u) > k) { \ |
| 165 | u >>= 1; \ |
| 166 | (e)++; \ |
| 167 | } \ |
| 168 | (m) = u & (k >> 1); \ |
| 169 | } while (0); |
| 170 | |
| 171 | #define CVMX_SHOFT_MAX() \ |
| 172 | CVMX_SHOFT_TO_U64((1 << CVMX_SHOFT_MANT_BITS) - 1, (1 << CVMX_SHOFT_EXP_BITS) - 1) |
| 173 | #define CVMX_SHOFT_MIN() CVMX_SHOFT_TO_U64(0, 0) |
| 174 | |
| 175 | #endif /* __CVMX_PKO3_QUEUE_H__ */ |