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git01.mediatek.com / filogic / uboot / c2ed2e3f81e0a3873d33eb857dc51c01a33476ca / . / dts / upstream / src / arm64 / freescale / imx8mq.dtsi
blob: e03186bbc415248a1e23c5fe83638c04bfcb9932 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2017 NXP
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
5 */
6
7#include <dt-bindings/clock/imx8mq-clock.h>
8#include <dt-bindings/power/imx8mq-power.h>
9#include <dt-bindings/reset/imx8mq-reset.h>
10#include <dt-bindings/gpio/gpio.h>
11#include "dt-bindings/input/input.h"
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include <dt-bindings/thermal/thermal.h>
14#include <dt-bindings/interconnect/imx8mq.h>
15#include "imx8mq-pinfunc.h"
16
17/ {
18 interrupt-parent = <&gpc>;
19
20 #address-cells = <2>;
21 #size-cells = <2>;
22
23 aliases {
24 ethernet0 = &fec1;
25 gpio0 = &gpio1;
26 gpio1 = &gpio2;
27 gpio2 = &gpio3;
28 gpio3 = &gpio4;
29 gpio4 = &gpio5;
30 i2c0 = &i2c1;
31 i2c1 = &i2c2;
32 i2c2 = &i2c3;
33 i2c3 = &i2c4;
34 mmc0 = &usdhc1;
35 mmc1 = &usdhc2;
36 serial0 = &uart1;
37 serial1 = &uart2;
38 serial2 = &uart3;
39 serial3 = &uart4;
40 spi0 = &ecspi1;
41 spi1 = &ecspi2;
42 spi2 = &ecspi3;
43 };
44
45 ckil: clock-ckil {
46 compatible = "fixed-clock";
47 #clock-cells = <0>;
48 clock-frequency = <32768>;
49 clock-output-names = "ckil";
50 };
51
52 osc_25m: clock-osc-25m {
53 compatible = "fixed-clock";
54 #clock-cells = <0>;
55 clock-frequency = <25000000>;
56 clock-output-names = "osc_25m";
57 };
58
59 osc_27m: clock-osc-27m {
60 compatible = "fixed-clock";
61 #clock-cells = <0>;
62 clock-frequency = <27000000>;
63 clock-output-names = "osc_27m";
64 };
65
66 hdmi_phy_27m: clock-hdmi-phy-27m {
67 compatible = "fixed-clock";
68 #clock-cells = <0>;
69 clock-frequency = <27000000>;
70 clock-output-names = "hdmi_phy_27m";
71 };
72
73 clk_ext1: clock-ext1 {
74 compatible = "fixed-clock";
75 #clock-cells = <0>;
76 clock-frequency = <133000000>;
77 clock-output-names = "clk_ext1";
78 };
79
80 clk_ext2: clock-ext2 {
81 compatible = "fixed-clock";
82 #clock-cells = <0>;
83 clock-frequency = <133000000>;
84 clock-output-names = "clk_ext2";
85 };
86
87 clk_ext3: clock-ext3 {
88 compatible = "fixed-clock";
89 #clock-cells = <0>;
90 clock-frequency = <133000000>;
91 clock-output-names = "clk_ext3";
92 };
93
94 clk_ext4: clock-ext4 {
95 compatible = "fixed-clock";
96 #clock-cells = <0>;
97 clock-frequency = <133000000>;
98 clock-output-names = "clk_ext4";
99 };
100
101 cpus {
102 #address-cells = <1>;
103 #size-cells = <0>;
104
105 A53_0: cpu@0 {
106 device_type = "cpu";
107 compatible = "arm,cortex-a53";
108 reg = <0x0>;
109 clock-latency = <61036>; /* two CLK32 periods */
110 clocks = <&clk IMX8MQ_CLK_ARM>;
111 enable-method = "psci";
112 i-cache-size = <0x8000>;
113 i-cache-line-size = <64>;
114 i-cache-sets = <256>;
115 d-cache-size = <0x8000>;
116 d-cache-line-size = <64>;
117 d-cache-sets = <128>;
118 next-level-cache = <&A53_L2>;
119 operating-points-v2 = <&a53_opp_table>;
120 #cooling-cells = <2>;
121 nvmem-cells = <&cpu_speed_grade>;
122 nvmem-cell-names = "speed_grade";
123 };
124
125 A53_1: cpu@1 {
126 device_type = "cpu";
127 compatible = "arm,cortex-a53";
128 reg = <0x1>;
129 clock-latency = <61036>; /* two CLK32 periods */
130 clocks = <&clk IMX8MQ_CLK_ARM>;
131 enable-method = "psci";
132 i-cache-size = <0x8000>;
133 i-cache-line-size = <64>;
134 i-cache-sets = <256>;
135 d-cache-size = <0x8000>;
136 d-cache-line-size = <64>;
137 d-cache-sets = <128>;
138 next-level-cache = <&A53_L2>;
139 operating-points-v2 = <&a53_opp_table>;
140 #cooling-cells = <2>;
141 };
142
143 A53_2: cpu@2 {
144 device_type = "cpu";
145 compatible = "arm,cortex-a53";
146 reg = <0x2>;
147 clock-latency = <61036>; /* two CLK32 periods */
148 clocks = <&clk IMX8MQ_CLK_ARM>;
149 enable-method = "psci";
150 i-cache-size = <0x8000>;
151 i-cache-line-size = <64>;
152 i-cache-sets = <256>;
153 d-cache-size = <0x8000>;
154 d-cache-line-size = <64>;
155 d-cache-sets = <128>;
156 next-level-cache = <&A53_L2>;
157 operating-points-v2 = <&a53_opp_table>;
158 #cooling-cells = <2>;
159 };
160
161 A53_3: cpu@3 {
162 device_type = "cpu";
163 compatible = "arm,cortex-a53";
164 reg = <0x3>;
165 clock-latency = <61036>; /* two CLK32 periods */
166 clocks = <&clk IMX8MQ_CLK_ARM>;
167 enable-method = "psci";
168 i-cache-size = <0x8000>;
169 i-cache-line-size = <64>;
170 i-cache-sets = <256>;
171 d-cache-size = <0x8000>;
172 d-cache-line-size = <64>;
173 d-cache-sets = <128>;
174 next-level-cache = <&A53_L2>;
175 operating-points-v2 = <&a53_opp_table>;
176 #cooling-cells = <2>;
177 };
178
179 A53_L2: l2-cache0 {
180 compatible = "cache";
181 cache-level = <2>;
182 cache-unified;
183 cache-size = <0x100000>;
184 cache-line-size = <64>;
185 cache-sets = <1024>;
186 };
187 };
188
189 a53_opp_table: opp-table {
190 compatible = "operating-points-v2";
191 opp-shared;
192
193 opp-800000000 {
194 opp-hz = /bits/ 64 <800000000>;
195 opp-microvolt = <900000>;
196 /* Industrial only */
197 opp-supported-hw = <0xf>, <0x4>;
198 clock-latency-ns = <150000>;
199 opp-suspend;
200 };
201
202 opp-1000000000 {
203 opp-hz = /bits/ 64 <1000000000>;
204 opp-microvolt = <900000>;
205 /* Consumer only */
206 opp-supported-hw = <0xe>, <0x3>;
207 clock-latency-ns = <150000>;
208 opp-suspend;
209 };
210
211 opp-1300000000 {
212 opp-hz = /bits/ 64 <1300000000>;
213 opp-microvolt = <1000000>;
214 opp-supported-hw = <0xc>, <0x4>;
215 clock-latency-ns = <150000>;
216 opp-suspend;
217 };
218
219 opp-1500000000 {
220 opp-hz = /bits/ 64 <1500000000>;
221 opp-microvolt = <1000000>;
222 opp-supported-hw = <0x8>, <0x3>;
223 clock-latency-ns = <150000>;
224 opp-suspend;
225 };
226 };
227
228 funnel {
229 /*
230 * non-configurable funnel don't show up on the AMBA
231 * bus. As such no need to add "arm,primecell".
232 */
233 compatible = "arm,coresight-static-funnel";
234
235 in-ports {
236 #address-cells = <1>;
237 #size-cells = <0>;
238
239 port@0 {
240 reg = <0>;
241
242 ca_funnel_in_port0: endpoint {
243 remote-endpoint = <&etm0_out_port>;
244 };
245 };
246
247 port@1 {
248 reg = <1>;
249
250 ca_funnel_in_port1: endpoint {
251 remote-endpoint = <&etm1_out_port>;
252 };
253 };
254
255 port@2 {
256 reg = <2>;
257
258 ca_funnel_in_port2: endpoint {
259 remote-endpoint = <&etm2_out_port>;
260 };
261 };
262
263 port@3 {
264 reg = <3>;
265
266 ca_funnel_in_port3: endpoint {
267 remote-endpoint = <&etm3_out_port>;
268 };
269 };
270 };
271
272 out-ports {
273 port {
274 ca_funnel_out_port0: endpoint {
275 remote-endpoint = <&hugo_funnel_in_port0>;
276 };
277 };
278 };
279 };
280
281 pmu {
282 compatible = "arm,cortex-a53-pmu";
283 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
284 interrupt-parent = <&gic>;
285 };
286
287 psci {
288 compatible = "arm,psci-1.0";
289 method = "smc";
290 };
291
292 thermal-zones {
293 cpu_thermal: cpu-thermal {
294 polling-delay-passive = <250>;
295 polling-delay = <2000>;
296 thermal-sensors = <&tmu 0>;
297
298 trips {
299 cpu_alert: cpu-alert {
300 temperature = <80000>;
301 hysteresis = <2000>;
302 type = "passive";
303 };
304
305 cpu-crit {
306 temperature = <90000>;
307 hysteresis = <2000>;
308 type = "critical";
309 };
310 };
311
312 cooling-maps {
313 map0 {
314 trip = <&cpu_alert>;
315 cooling-device =
316 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
317 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
318 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
319 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
320 };
321 };
322 };
323
324 gpu-thermal {
325 polling-delay-passive = <250>;
326 polling-delay = <2000>;
327 thermal-sensors = <&tmu 1>;
328
329 trips {
330 gpu_alert: gpu-alert {
331 temperature = <80000>;
332 hysteresis = <2000>;
333 type = "passive";
334 };
335
336 gpu-crit {
337 temperature = <90000>;
338 hysteresis = <2000>;
339 type = "critical";
340 };
341 };
342
343 cooling-maps {
344 map0 {
345 trip = <&gpu_alert>;
346 cooling-device =
347 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
348 };
349 };
350 };
351
352 vpu-thermal {
353 polling-delay-passive = <250>;
354 polling-delay = <2000>;
355 thermal-sensors = <&tmu 2>;
356
357 trips {
358 vpu-crit {
359 temperature = <90000>;
360 hysteresis = <2000>;
361 type = "critical";
362 };
363 };
364 };
365 };
366
367 timer {
368 compatible = "arm,armv8-timer";
369 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
370 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
371 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
372 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
373 interrupt-parent = <&gic>;
374 arm,no-tick-in-suspend;
375 };
376
377 soc: soc@0 {
378 compatible = "fsl,imx8mq-soc", "simple-bus";
379 #address-cells = <1>;
380 #size-cells = <1>;
381 ranges = <0x0 0x0 0x0 0x3e000000>;
382 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
383 nvmem-cells = <&imx8mq_uid>;
384 nvmem-cell-names = "soc_unique_id";
385
386 etm0: etm@28440000 {
387 compatible = "arm,coresight-etm4x", "arm,primecell";
388 reg = <0x28440000 0x1000>;
389 cpu = <&A53_0>;
390 clocks = <&clk IMX8MQ_CLK_MAIN_AXI>;
391 clock-names = "apb_pclk";
392
393 out-ports {
394 port {
395 etm0_out_port: endpoint {
396 remote-endpoint = <&ca_funnel_in_port0>;
397 };
398 };
399 };
400 };
401
402 etm1: etm@28540000 {
403 compatible = "arm,coresight-etm4x", "arm,primecell";
404 reg = <0x28540000 0x1000>;
405 cpu = <&A53_1>;
406 clocks = <&clk IMX8MQ_CLK_MAIN_AXI>;
407 clock-names = "apb_pclk";
408
409 out-ports {
410 port {
411 etm1_out_port: endpoint {
412 remote-endpoint = <&ca_funnel_in_port1>;
413 };
414 };
415 };
416 };
417
418 etm2: etm@28640000 {
419 compatible = "arm,coresight-etm4x", "arm,primecell";
420 reg = <0x28640000 0x1000>;
421 cpu = <&A53_2>;
422 clocks = <&clk IMX8MQ_CLK_MAIN_AXI>;
423 clock-names = "apb_pclk";
424
425 out-ports {
426 port {
427 etm2_out_port: endpoint {
428 remote-endpoint = <&ca_funnel_in_port2>;
429 };
430 };
431 };
432 };
433
434 etm3: etm@28740000 {
435 compatible = "arm,coresight-etm4x", "arm,primecell";
436 reg = <0x28740000 0x1000>;
437 cpu = <&A53_3>;
438 clocks = <&clk IMX8MQ_CLK_MAIN_AXI>;
439 clock-names = "apb_pclk";
440
441 out-ports {
442 port {
443 etm3_out_port: endpoint {
444 remote-endpoint = <&ca_funnel_in_port3>;
445 };
446 };
447 };
448 };
449
450 funnel@28c03000 {
451 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
452 reg = <0x28c03000 0x1000>;
453 clocks = <&clk IMX8MQ_CLK_MAIN_AXI>;
454 clock-names = "apb_pclk";
455
456 in-ports {
457 #address-cells = <1>;
458 #size-cells = <0>;
459
460 port@0 {
461 reg = <0>;
462
463 hugo_funnel_in_port0: endpoint {
464 remote-endpoint = <&ca_funnel_out_port0>;
465 };
466 };
467
468 port@1 {
469 reg = <1>;
470
471 hugo_funnel_in_port1: endpoint {
472 /* M4 input */
473 };
474 };
475 /* the other input ports are not connect to anything */
476 };
477
478 out-ports {
479 port {
480 hugo_funnel_out_port0: endpoint {
481 remote-endpoint = <&etf_in_port>;
482 };
483 };
484 };
485 };
486
487 etf@28c04000 {
488 compatible = "arm,coresight-tmc", "arm,primecell";
489 reg = <0x28c04000 0x1000>;
490 clocks = <&clk IMX8MQ_CLK_MAIN_AXI>;
491 clock-names = "apb_pclk";
492
493 in-ports {
494 port {
495 etf_in_port: endpoint {
496 remote-endpoint = <&hugo_funnel_out_port0>;
497 };
498 };
499 };
500
501 out-ports {
502 port {
503 etf_out_port: endpoint {
504 remote-endpoint = <&etr_in_port>;
505 };
506 };
507 };
508 };
509
510 etr@28c06000 {
511 compatible = "arm,coresight-tmc", "arm,primecell";
512 reg = <0x28c06000 0x1000>;
513 clocks = <&clk IMX8MQ_CLK_MAIN_AXI>;
514 clock-names = "apb_pclk";
515
516 in-ports {
517 port {
518 etr_in_port: endpoint {
519 remote-endpoint = <&etf_out_port>;
520 };
521 };
522 };
523 };
524
525 aips1: bus@30000000 { /* AIPS1 */
526 compatible = "fsl,aips-bus", "simple-bus";
527 reg = <0x30000000 0x400000>;
528 #address-cells = <1>;
529 #size-cells = <1>;
530 ranges = <0x30000000 0x30000000 0x400000>;
531
532 sai1: sai@30010000 {
533 #sound-dai-cells = <0>;
534 compatible = "fsl,imx8mq-sai";
535 reg = <0x30010000 0x10000>;
536 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
537 clocks = <&clk IMX8MQ_CLK_SAI1_IPG>,
538 <&clk IMX8MQ_CLK_SAI1_ROOT>,
539 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
540 clock-names = "bus", "mclk1", "mclk2", "mclk3";
541 dmas = <&sdma2 8 24 0>, <&sdma1 9 24 0>;
542 dma-names = "rx", "tx";
543 status = "disabled";
544 };
545
546 sai6: sai@30030000 {
547 #sound-dai-cells = <0>;
548 compatible = "fsl,imx8mq-sai";
549 reg = <0x30030000 0x10000>;
550 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
551 clocks = <&clk IMX8MQ_CLK_SAI6_IPG>,
552 <&clk IMX8MQ_CLK_SAI6_ROOT>,
553 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
554 clock-names = "bus", "mclk1", "mclk2", "mclk3";
555 dmas = <&sdma2 4 24 0>, <&sdma2 5 24 0>;
556 dma-names = "rx", "tx";
557 status = "disabled";
558 };
559
560 sai5: sai@30040000 {
561 #sound-dai-cells = <0>;
562 compatible = "fsl,imx8mq-sai";
563 reg = <0x30040000 0x10000>;
564 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
565 clocks = <&clk IMX8MQ_CLK_SAI5_IPG>,
566 <&clk IMX8MQ_CLK_SAI5_ROOT>,
567 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
568 clock-names = "bus", "mclk1", "mclk2", "mclk3";
569 dmas = <&sdma2 2 24 0>, <&sdma2 3 24 0>;
570 dma-names = "rx", "tx";
571 status = "disabled";
572 };
573
574 sai4: sai@30050000 {
575 #sound-dai-cells = <0>;
576 compatible = "fsl,imx8mq-sai";
577 reg = <0x30050000 0x10000>;
578 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
579 clocks = <&clk IMX8MQ_CLK_SAI4_IPG>,
580 <&clk IMX8MQ_CLK_SAI4_ROOT>,
581 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
582 clock-names = "bus", "mclk1", "mclk2", "mclk3";
583 dmas = <&sdma2 0 24 0>, <&sdma2 1 24 0>;
584 dma-names = "rx", "tx";
585 status = "disabled";
586 };
587
588 gpio1: gpio@30200000 {
589 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
590 reg = <0x30200000 0x10000>;
591 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
592 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
593 clocks = <&clk IMX8MQ_CLK_GPIO1_ROOT>;
594 gpio-controller;
595 #gpio-cells = <2>;
596 interrupt-controller;
597 #interrupt-cells = <2>;
598 gpio-ranges = <&iomuxc 0 10 30>;
599 };
600
601 gpio2: gpio@30210000 {
602 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
603 reg = <0x30210000 0x10000>;
604 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
605 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
606 clocks = <&clk IMX8MQ_CLK_GPIO2_ROOT>;
607 gpio-controller;
608 #gpio-cells = <2>;
609 interrupt-controller;
610 #interrupt-cells = <2>;
611 gpio-ranges = <&iomuxc 0 40 21>;
612 };
613
614 gpio3: gpio@30220000 {
615 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
616 reg = <0x30220000 0x10000>;
617 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
618 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
619 clocks = <&clk IMX8MQ_CLK_GPIO3_ROOT>;
620 gpio-controller;
621 #gpio-cells = <2>;
622 interrupt-controller;
623 #interrupt-cells = <2>;
624 gpio-ranges = <&iomuxc 0 61 26>;
625 };
626
627 gpio4: gpio@30230000 {
628 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
629 reg = <0x30230000 0x10000>;
630 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
631 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
632 clocks = <&clk IMX8MQ_CLK_GPIO4_ROOT>;
633 gpio-controller;
634 #gpio-cells = <2>;
635 interrupt-controller;
636 #interrupt-cells = <2>;
637 gpio-ranges = <&iomuxc 0 87 32>;
638 };
639
640 gpio5: gpio@30240000 {
641 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
642 reg = <0x30240000 0x10000>;
643 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
644 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
645 clocks = <&clk IMX8MQ_CLK_GPIO5_ROOT>;
646 gpio-controller;
647 #gpio-cells = <2>;
648 interrupt-controller;
649 #interrupt-cells = <2>;
650 gpio-ranges = <&iomuxc 0 119 30>;
651 };
652
653 tmu: tmu@30260000 {
654 compatible = "fsl,imx8mq-tmu";
655 reg = <0x30260000 0x10000>;
656 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
657 clocks = <&clk IMX8MQ_CLK_TMU_ROOT>;
658 little-endian;
659 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
660 fsl,tmu-calibration = <0x00000000 0x00000023>,
661 <0x00000001 0x00000029>,
662 <0x00000002 0x0000002f>,
663 <0x00000003 0x00000035>,
664 <0x00000004 0x0000003d>,
665 <0x00000005 0x00000043>,
666 <0x00000006 0x0000004b>,
667 <0x00000007 0x00000051>,
668 <0x00000008 0x00000057>,
669 <0x00000009 0x0000005f>,
670 <0x0000000a 0x00000067>,
671 <0x0000000b 0x0000006f>,
672
673 <0x00010000 0x0000001b>,
674 <0x00010001 0x00000023>,
675 <0x00010002 0x0000002b>,
676 <0x00010003 0x00000033>,
677 <0x00010004 0x0000003b>,
678 <0x00010005 0x00000043>,
679 <0x00010006 0x0000004b>,
680 <0x00010007 0x00000055>,
681 <0x00010008 0x0000005d>,
682 <0x00010009 0x00000067>,
683 <0x0001000a 0x00000070>,
684
685 <0x00020000 0x00000017>,
686 <0x00020001 0x00000023>,
687 <0x00020002 0x0000002d>,
688 <0x00020003 0x00000037>,
689 <0x00020004 0x00000041>,
690 <0x00020005 0x0000004b>,
691 <0x00020006 0x00000057>,
692 <0x00020007 0x00000063>,
693 <0x00020008 0x0000006f>,
694
695 <0x00030000 0x00000015>,
696 <0x00030001 0x00000021>,
697 <0x00030002 0x0000002d>,
698 <0x00030003 0x00000039>,
699 <0x00030004 0x00000045>,
700 <0x00030005 0x00000053>,
701 <0x00030006 0x0000005f>,
702 <0x00030007 0x00000071>;
703 #thermal-sensor-cells = <1>;
704 };
705
706 wdog1: watchdog@30280000 {
707 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
708 reg = <0x30280000 0x10000>;
709 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
710 clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
711 status = "disabled";
712 };
713
714 wdog2: watchdog@30290000 {
715 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
716 reg = <0x30290000 0x10000>;
717 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
718 clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
719 status = "disabled";
720 };
721
722 wdog3: watchdog@302a0000 {
723 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
724 reg = <0x302a0000 0x10000>;
725 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
726 clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
727 status = "disabled";
728 };
729
730 sdma2: dma-controller@302c0000 {
731 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
732 reg = <0x302c0000 0x10000>;
733 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
734 clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>,
735 <&clk IMX8MQ_CLK_SDMA2_ROOT>;
736 clock-names = "ipg", "ahb";
737 #dma-cells = <3>;
738 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
739 };
740
741 lcdif: lcd-controller@30320000 {
742 compatible = "fsl,imx8mq-lcdif", "fsl,imx6sx-lcdif";
743 reg = <0x30320000 0x10000>;
744 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
745 clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>,
746 <&clk IMX8MQ_CLK_DISP_APB_ROOT>,
747 <&clk IMX8MQ_CLK_DISP_AXI_ROOT>;
748 clock-names = "pix", "axi", "disp_axi";
749 assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
750 <&clk IMX8MQ_VIDEO_PLL1_BYPASS>,
751 <&clk IMX8MQ_CLK_LCDIF_PIXEL>,
752 <&clk IMX8MQ_VIDEO_PLL1>;
753 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
754 <&clk IMX8MQ_VIDEO_PLL1>,
755 <&clk IMX8MQ_VIDEO_PLL1_OUT>;
756 assigned-clock-rates = <0>, <0>, <0>, <594000000>;
757 status = "disabled";
758
759 port {
760 lcdif_mipi_dsi: endpoint {
761 remote-endpoint = <&mipi_dsi_lcdif_in>;
762 };
763 };
764 };
765
766 iomuxc: pinctrl@30330000 {
767 compatible = "fsl,imx8mq-iomuxc";
768 reg = <0x30330000 0x10000>;
769 };
770
771 iomuxc_gpr: syscon@30340000 {
772 compatible = "fsl,imx8mq-iomuxc-gpr", "syscon", "simple-mfd";
773 reg = <0x30340000 0x10000>;
774
775 mux: mux-controller {
776 compatible = "mmio-mux";
777 #mux-control-cells = <1>;
778 mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */
779 };
780 };
781
782 ocotp: efuse@30350000 {
783 compatible = "fsl,imx8mq-ocotp", "syscon";
784 reg = <0x30350000 0x10000>;
785 clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>;
786 #address-cells = <1>;
787 #size-cells = <1>;
788
789 /*
790 * The register address below maps to the MX8M
791 * Fusemap Description Table entries this way.
792 * Assuming
793 * reg = <ADDR SIZE>;
794 * then
795 * Fuse Address = (ADDR * 4) + 0x400
796 * Note that if SIZE is greater than 4, then
797 * each subsequent fuse is located at offset
798 * +0x10 in Fusemap Description Table (e.g.
799 * reg = <0x4 0x8> describes fuses 0x410 and
800 * 0x420).
801 */
802 imx8mq_uid: soc-uid@4 { /* 0x410-0x420 */
803 reg = <0x4 0x8>;
804 };
805
806 cpu_speed_grade: speed-grade@10 { /* 0x440 */
807 reg = <0x10 4>;
808 };
809
810 fec_mac_address: mac-address@90 { /* 0x640 */
811 reg = <0x90 6>;
812 };
813 };
814
815 anatop: clock-controller@30360000 {
816 compatible = "fsl,imx8mq-anatop";
817 reg = <0x30360000 0x10000>;
818 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
819 #clock-cells = <1>;
820 };
821
822 snvs: snvs@30370000 {
823 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
824 reg = <0x30370000 0x10000>;
825
826 snvs_rtc: snvs-rtc-lp {
827 compatible = "fsl,sec-v4.0-mon-rtc-lp";
828 regmap = <&snvs>;
829 offset = <0x34>;
830 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
831 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
832 clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>;
833 clock-names = "snvs-rtc";
834 };
835
836 snvs_pwrkey: snvs-powerkey {
837 compatible = "fsl,sec-v4.0-pwrkey";
838 regmap = <&snvs>;
839 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
840 clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>;
841 clock-names = "snvs-pwrkey";
842 linux,keycode = <KEY_POWER>;
843 wakeup-source;
844 status = "disabled";
845 };
846 };
847
848 clk: clock-controller@30380000 {
849 compatible = "fsl,imx8mq-ccm";
850 reg = <0x30380000 0x10000>;
851 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
852 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
853 #clock-cells = <1>;
854 clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
855 <&clk_ext1>, <&clk_ext2>,
856 <&clk_ext3>, <&clk_ext4>;
857 clock-names = "ckil", "osc_25m", "osc_27m",
858 "clk_ext1", "clk_ext2",
859 "clk_ext3", "clk_ext4";
860 assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>,
861 <&clk IMX8MQ_CLK_A53_CORE>,
862 <&clk IMX8MQ_CLK_NOC>,
863 <&clk IMX8MQ_CLK_AUDIO_AHB>,
864 <&clk IMX8MQ_AUDIO_PLL1_BYPASS>,
865 <&clk IMX8MQ_AUDIO_PLL2_BYPASS>,
866 <&clk IMX8MQ_AUDIO_PLL1>,
867 <&clk IMX8MQ_AUDIO_PLL2>;
868 assigned-clock-rates = <0>, <0>,
869 <800000000>,
870 <0>,
871 <0>,
872 <0>,
873 <786432000>,
874 <722534400>;
875 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>,
876 <&clk IMX8MQ_ARM_PLL_OUT>,
877 <0>,
878 <&clk IMX8MQ_SYS2_PLL_500M>,
879 <&clk IMX8MQ_AUDIO_PLL1>,
880 <&clk IMX8MQ_AUDIO_PLL2>;
881 };
882
883 src: reset-controller@30390000 {
884 compatible = "fsl,imx8mq-src", "syscon";
885 reg = <0x30390000 0x10000>;
886 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
887 #reset-cells = <1>;
888 };
889
890 gpc: gpc@303a0000 {
891 compatible = "fsl,imx8mq-gpc";
892 reg = <0x303a0000 0x10000>;
893 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
894 interrupt-parent = <&gic>;
895 interrupt-controller;
896 #interrupt-cells = <3>;
897
898 pgc {
899 #address-cells = <1>;
900 #size-cells = <0>;
901
902 pgc_mipi: power-domain@0 {
903 #power-domain-cells = <0>;
904 reg = <IMX8M_POWER_DOMAIN_MIPI>;
905 };
906
907 /*
908 * As per comment in ATF source code:
909 *
910 * PCIE1 and PCIE2 share the
911 * same reset signal, if we
912 * power down PCIE2, PCIE1
913 * will be held in reset too.
914 *
915 * So instead of creating two
916 * separate power domains for
917 * PCIE1 and PCIE2 we create a
918 * link between both and use
919 * it as a shared PCIE power
920 * domain.
921 */
922 pgc_pcie: power-domain@1 {
923 #power-domain-cells = <0>;
924 reg = <IMX8M_POWER_DOMAIN_PCIE1>;
925 power-domains = <&pgc_pcie2>;
926 };
927
928 pgc_otg1: power-domain@2 {
929 #power-domain-cells = <0>;
930 reg = <IMX8M_POWER_DOMAIN_USB_OTG1>;
931 };
932
933 pgc_otg2: power-domain@3 {
934 #power-domain-cells = <0>;
935 reg = <IMX8M_POWER_DOMAIN_USB_OTG2>;
936 };
937
938 pgc_ddr1: power-domain@4 {
939 #power-domain-cells = <0>;
940 reg = <IMX8M_POWER_DOMAIN_DDR1>;
941 };
942
943 pgc_gpu: power-domain@5 {
944 #power-domain-cells = <0>;
945 reg = <IMX8M_POWER_DOMAIN_GPU>;
946 clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
947 <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
948 <&clk IMX8MQ_CLK_GPU_AXI>,
949 <&clk IMX8MQ_CLK_GPU_AHB>;
950 };
951
952 pgc_vpu: power-domain@6 {
953 #power-domain-cells = <0>;
954 reg = <IMX8M_POWER_DOMAIN_VPU>;
955 clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>,
956 <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
957 <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
958 assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
959 <&clk IMX8MQ_CLK_VPU_G2>,
960 <&clk IMX8MQ_CLK_VPU_BUS>,
961 <&clk IMX8MQ_VPU_PLL_BYPASS>;
962 assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
963 <&clk IMX8MQ_VPU_PLL_OUT>,
964 <&clk IMX8MQ_SYS1_PLL_800M>,
965 <&clk IMX8MQ_VPU_PLL>;
966 assigned-clock-rates = <600000000>,
967 <300000000>,
968 <800000000>,
969 <0>;
970 };
971
972 pgc_disp: power-domain@7 {
973 #power-domain-cells = <0>;
974 reg = <IMX8M_POWER_DOMAIN_DISP>;
975 };
976
977 pgc_mipi_csi1: power-domain@8 {
978 #power-domain-cells = <0>;
979 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI1>;
980 };
981
982 pgc_mipi_csi2: power-domain@9 {
983 #power-domain-cells = <0>;
984 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI2>;
985 };
986
987 pgc_pcie2: power-domain@a {
988 #power-domain-cells = <0>;
989 reg = <IMX8M_POWER_DOMAIN_PCIE2>;
990 };
991 };
992 };
993 };
994
995 aips2: bus@30400000 { /* AIPS2 */
996 compatible = "fsl,aips-bus", "simple-bus";
997 reg = <0x30400000 0x400000>;
998 #address-cells = <1>;
999 #size-cells = <1>;
1000 ranges = <0x30400000 0x30400000 0x400000>;
1001
1002 pwm1: pwm@30660000 {
1003 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
1004 reg = <0x30660000 0x10000>;
1005 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1006 clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>,
1007 <&clk IMX8MQ_CLK_PWM1_ROOT>;
1008 clock-names = "ipg", "per";
1009 #pwm-cells = <3>;
1010 status = "disabled";
1011 };
1012
1013 pwm2: pwm@30670000 {
1014 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
1015 reg = <0x30670000 0x10000>;
1016 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1017 clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>,
1018 <&clk IMX8MQ_CLK_PWM2_ROOT>;
1019 clock-names = "ipg", "per";
1020 #pwm-cells = <3>;
1021 status = "disabled";
1022 };
1023
1024 pwm3: pwm@30680000 {
1025 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
1026 reg = <0x30680000 0x10000>;
1027 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1028 clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>,
1029 <&clk IMX8MQ_CLK_PWM3_ROOT>;
1030 clock-names = "ipg", "per";
1031 #pwm-cells = <3>;
1032 status = "disabled";
1033 };
1034
1035 pwm4: pwm@30690000 {
1036 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
1037 reg = <0x30690000 0x10000>;
1038 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1039 clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>,
1040 <&clk IMX8MQ_CLK_PWM4_ROOT>;
1041 clock-names = "ipg", "per";
1042 #pwm-cells = <3>;
1043 status = "disabled";
1044 };
1045
1046 system_counter: timer@306a0000 {
1047 compatible = "nxp,sysctr-timer";
1048 reg = <0x306a0000 0x20000>;
1049 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1050 clocks = <&osc_25m>;
1051 clock-names = "per";
1052 };
1053 };
1054
1055 aips3: bus@30800000 { /* AIPS3 */
1056 compatible = "fsl,aips-bus", "simple-bus";
1057 reg = <0x30800000 0x400000>;
1058 #address-cells = <1>;
1059 #size-cells = <1>;
1060 ranges = <0x30800000 0x30800000 0x400000>,
1061 <0x08000000 0x08000000 0x10000000>;
1062
1063 spdif1: spdif@30810000 {
1064 compatible = "fsl,imx35-spdif";
1065 reg = <0x30810000 0x10000>;
1066 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1067 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */
1068 <&clk IMX8MQ_CLK_25M>, /* rxtx0 */
1069 <&clk IMX8MQ_CLK_SPDIF1>, /* rxtx1 */
1070 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */
1071 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */
1072 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */
1073 <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */
1074 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */
1075 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */
1076 <&clk IMX8MQ_CLK_DUMMY>; /* spba */
1077 clock-names = "core", "rxtx0",
1078 "rxtx1", "rxtx2",
1079 "rxtx3", "rxtx4",
1080 "rxtx5", "rxtx6",
1081 "rxtx7", "spba";
1082 dmas = <&sdma1 8 18 0>, <&sdma1 9 18 0>;
1083 dma-names = "rx", "tx";
1084 status = "disabled";
1085 };
1086
1087 ecspi1: spi@30820000 {
1088 #address-cells = <1>;
1089 #size-cells = <0>;
1090 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
1091 reg = <0x30820000 0x10000>;
1092 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1093 clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>,
1094 <&clk IMX8MQ_CLK_ECSPI1_ROOT>;
1095 clock-names = "ipg", "per";
1096 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
1097 dma-names = "rx", "tx";
1098 status = "disabled";
1099 };
1100
1101 ecspi2: spi@30830000 {
1102 #address-cells = <1>;
1103 #size-cells = <0>;
1104 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
1105 reg = <0x30830000 0x10000>;
1106 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1107 clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>,
1108 <&clk IMX8MQ_CLK_ECSPI2_ROOT>;
1109 clock-names = "ipg", "per";
1110 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
1111 dma-names = "rx", "tx";
1112 status = "disabled";
1113 };
1114
1115 ecspi3: spi@30840000 {
1116 #address-cells = <1>;
1117 #size-cells = <0>;
1118 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
1119 reg = <0x30840000 0x10000>;
1120 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1121 clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>,
1122 <&clk IMX8MQ_CLK_ECSPI3_ROOT>;
1123 clock-names = "ipg", "per";
1124 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
1125 dma-names = "rx", "tx";
1126 status = "disabled";
1127 };
1128
1129 uart1: serial@30860000 {
1130 compatible = "fsl,imx8mq-uart",
1131 "fsl,imx6q-uart";
1132 reg = <0x30860000 0x10000>;
1133 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1134 clocks = <&clk IMX8MQ_CLK_UART1_ROOT>,
1135 <&clk IMX8MQ_CLK_UART1_ROOT>;
1136 clock-names = "ipg", "per";
1137 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
1138 dma-names = "rx", "tx";
1139 status = "disabled";
1140 };
1141
1142 uart3: serial@30880000 {
1143 compatible = "fsl,imx8mq-uart",
1144 "fsl,imx6q-uart";
1145 reg = <0x30880000 0x10000>;
1146 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1147 clocks = <&clk IMX8MQ_CLK_UART3_ROOT>,
1148 <&clk IMX8MQ_CLK_UART3_ROOT>;
1149 clock-names = "ipg", "per";
1150 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
1151 dma-names = "rx", "tx";
1152 status = "disabled";
1153 };
1154
1155 uart2: serial@30890000 {
1156 compatible = "fsl,imx8mq-uart",
1157 "fsl,imx6q-uart";
1158 reg = <0x30890000 0x10000>;
1159 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1160 clocks = <&clk IMX8MQ_CLK_UART2_ROOT>,
1161 <&clk IMX8MQ_CLK_UART2_ROOT>;
1162 clock-names = "ipg", "per";
1163 dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
1164 dma-names = "rx", "tx";
1165 status = "disabled";
1166 };
1167
1168 spdif2: spdif@308a0000 {
1169 compatible = "fsl,imx35-spdif";
1170 reg = <0x308a0000 0x10000>;
1171 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1172 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */
1173 <&clk IMX8MQ_CLK_25M>, /* rxtx0 */
1174 <&clk IMX8MQ_CLK_SPDIF2>, /* rxtx1 */
1175 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */
1176 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */
1177 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */
1178 <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */
1179 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */
1180 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */
1181 <&clk IMX8MQ_CLK_DUMMY>; /* spba */
1182 clock-names = "core", "rxtx0",
1183 "rxtx1", "rxtx2",
1184 "rxtx3", "rxtx4",
1185 "rxtx5", "rxtx6",
1186 "rxtx7", "spba";
1187 dmas = <&sdma1 16 18 0>, <&sdma1 17 18 0>;
1188 dma-names = "rx", "tx";
1189 status = "disabled";
1190 };
1191
1192 sai2: sai@308b0000 {
1193 #sound-dai-cells = <0>;
1194 compatible = "fsl,imx8mq-sai";
1195 reg = <0x308b0000 0x10000>;
1196 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1197 clocks = <&clk IMX8MQ_CLK_SAI2_IPG>,
1198 <&clk IMX8MQ_CLK_SAI2_ROOT>,
1199 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
1200 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1201 dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>;
1202 dma-names = "rx", "tx";
1203 status = "disabled";
1204 };
1205
1206 sai3: sai@308c0000 {
1207 #sound-dai-cells = <0>;
1208 compatible = "fsl,imx8mq-sai";
1209 reg = <0x308c0000 0x10000>;
1210 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1211 clocks = <&clk IMX8MQ_CLK_SAI3_IPG>,
1212 <&clk IMX8MQ_CLK_SAI3_ROOT>,
1213 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
1214 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1215 dmas = <&sdma1 12 24 0>, <&sdma1 13 24 0>;
1216 dma-names = "rx", "tx";
1217 status = "disabled";
1218 };
1219
1220 crypto: crypto@30900000 {
1221 compatible = "fsl,sec-v4.0";
1222 #address-cells = <1>;
1223 #size-cells = <1>;
1224 reg = <0x30900000 0x40000>;
1225 ranges = <0 0x30900000 0x40000>;
1226 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1227 clocks = <&clk IMX8MQ_CLK_AHB>,
1228 <&clk IMX8MQ_CLK_IPG_ROOT>;
1229 clock-names = "aclk", "ipg";
1230
1231 sec_jr0: jr@1000 {
1232 compatible = "fsl,sec-v4.0-job-ring";
1233 reg = <0x1000 0x1000>;
1234 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1235 status = "disabled";
1236 };
1237
1238 sec_jr1: jr@2000 {
1239 compatible = "fsl,sec-v4.0-job-ring";
1240 reg = <0x2000 0x1000>;
1241 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1242 };
1243
1244 sec_jr2: jr@3000 {
1245 compatible = "fsl,sec-v4.0-job-ring";
1246 reg = <0x3000 0x1000>;
1247 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1248 };
1249 };
1250
1251 mipi_dsi: dsi@30a00000 {
1252 compatible = "fsl,imx8mq-nwl-dsi";
1253 reg = <0x30a00000 0x300>;
1254 #address-cells = <1>;
1255 #size-cells = <0>;
1256 clocks = <&clk IMX8MQ_CLK_DSI_CORE>,
1257 <&clk IMX8MQ_CLK_DSI_AHB>,
1258 <&clk IMX8MQ_CLK_DSI_IPG_DIV>,
1259 <&clk IMX8MQ_CLK_DSI_PHY_REF>,
1260 <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
1261 clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif";
1262 assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>,
1263 <&clk IMX8MQ_CLK_DSI_CORE>,
1264 <&clk IMX8MQ_CLK_DSI_IPG_DIV>;
1265 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>,
1266 <&clk IMX8MQ_SYS1_PLL_266M>;
1267 assigned-clock-rates = <80000000>, <266000000>, <20000000>;
1268 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
1269 mux-controls = <&mux 0>;
1270 power-domains = <&pgc_mipi>;
1271 phys = <&dphy>;
1272 phy-names = "dphy";
1273 resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>,
1274 <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>,
1275 <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>,
1276 <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>;
1277 reset-names = "byte", "dpi", "esc", "pclk";
1278 status = "disabled";
1279
1280 ports {
1281 #address-cells = <1>;
1282 #size-cells = <0>;
1283
1284 port@0 {
1285 reg = <0>;
1286 #address-cells = <1>;
1287 #size-cells = <0>;
1288 mipi_dsi_lcdif_in: endpoint@0 {
1289 reg = <0>;
1290 remote-endpoint = <&lcdif_mipi_dsi>;
1291 };
1292 };
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]1293
1294 port@1 {
1295 reg = <1>;
1296
1297 mipi_dsi_out: endpoint {
1298 };
1299 };
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1300 };
1301 };
1302
1303 dphy: dphy@30a00300 {
1304 compatible = "fsl,imx8mq-mipi-dphy";
1305 reg = <0x30a00300 0x100>;
1306 clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
1307 clock-names = "phy_ref";
1308 assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
1309 <&clk IMX8MQ_VIDEO_PLL1_BYPASS>,
1310 <&clk IMX8MQ_CLK_DSI_PHY_REF>,
1311 <&clk IMX8MQ_VIDEO_PLL1>;
1312 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
1313 <&clk IMX8MQ_VIDEO_PLL1>,
1314 <&clk IMX8MQ_VIDEO_PLL1_OUT>;
1315 assigned-clock-rates = <0>, <0>, <24000000>, <594000000>;
1316 #phy-cells = <0>;
1317 power-domains = <&pgc_mipi>;
1318 status = "disabled";
1319 };
1320
1321 i2c1: i2c@30a20000 {
1322 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
1323 reg = <0x30a20000 0x10000>;
1324 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1325 clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
1326 #address-cells = <1>;
1327 #size-cells = <0>;
1328 status = "disabled";
1329 };
1330
1331 i2c2: i2c@30a30000 {
1332 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
1333 reg = <0x30a30000 0x10000>;
1334 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1335 clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
1336 #address-cells = <1>;
1337 #size-cells = <0>;
1338 status = "disabled";
1339 };
1340
1341 i2c3: i2c@30a40000 {
1342 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
1343 reg = <0x30a40000 0x10000>;
1344 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1345 clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
1346 #address-cells = <1>;
1347 #size-cells = <0>;
1348 status = "disabled";
1349 };
1350
1351 i2c4: i2c@30a50000 {
1352 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
1353 reg = <0x30a50000 0x10000>;
1354 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1355 clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
1356 #address-cells = <1>;
1357 #size-cells = <0>;
1358 status = "disabled";
1359 };
1360
1361 uart4: serial@30a60000 {
1362 compatible = "fsl,imx8mq-uart",
1363 "fsl,imx6q-uart";
1364 reg = <0x30a60000 0x10000>;
1365 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1366 clocks = <&clk IMX8MQ_CLK_UART4_ROOT>,
1367 <&clk IMX8MQ_CLK_UART4_ROOT>;
1368 clock-names = "ipg", "per";
1369 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
1370 dma-names = "rx", "tx";
1371 status = "disabled";
1372 };
1373
1374 mipi_csi1: csi@30a70000 {
1375 compatible = "fsl,imx8mq-mipi-csi2";
1376 reg = <0x30a70000 0x1000>;
1377 clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
1378 <&clk IMX8MQ_CLK_CSI1_ESC>,
1379 <&clk IMX8MQ_CLK_CSI1_PHY_REF>;
1380 clock-names = "core", "esc", "ui";
1381 assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
1382 <&clk IMX8MQ_CLK_CSI1_PHY_REF>,
1383 <&clk IMX8MQ_CLK_CSI1_ESC>;
1384 assigned-clock-rates = <266000000>, <333000000>, <66000000>;
1385 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
1386 <&clk IMX8MQ_SYS2_PLL_1000M>,
1387 <&clk IMX8MQ_SYS1_PLL_800M>;
1388 power-domains = <&pgc_mipi_csi1>;
1389 resets = <&src IMX8MQ_RESET_MIPI_CSI1_CORE_RESET>,
1390 <&src IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET>,
1391 <&src IMX8MQ_RESET_MIPI_CSI1_ESC_RESET>;
1392 fsl,mipi-phy-gpr = <&iomuxc_gpr 0x88>;
1393 interconnects = <&noc IMX8MQ_ICM_CSI1 &noc IMX8MQ_ICS_DRAM>;
1394 interconnect-names = "dram";
1395 status = "disabled";
1396
1397 ports {
1398 #address-cells = <1>;
1399 #size-cells = <0>;
1400
1401 port@1 {
1402 reg = <1>;
1403
1404 csi1_mipi_ep: endpoint {
1405 remote-endpoint = <&csi1_ep>;
1406 };
1407 };
1408 };
1409 };
1410
1411 csi1: csi@30a90000 {
1412 compatible = "fsl,imx8mq-csi";
1413 reg = <0x30a90000 0x10000>;
1414 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1415 clocks = <&clk IMX8MQ_CLK_CSI1_ROOT>;
1416 clock-names = "mclk";
1417 status = "disabled";
1418
1419 port {
1420 csi1_ep: endpoint {
1421 remote-endpoint = <&csi1_mipi_ep>;
1422 };
1423 };
1424 };
1425
1426 mipi_csi2: csi@30b60000 {
1427 compatible = "fsl,imx8mq-mipi-csi2";
1428 reg = <0x30b60000 0x1000>;
1429 clocks = <&clk IMX8MQ_CLK_CSI2_CORE>,
1430 <&clk IMX8MQ_CLK_CSI2_ESC>,
1431 <&clk IMX8MQ_CLK_CSI2_PHY_REF>;
1432 clock-names = "core", "esc", "ui";
1433 assigned-clocks = <&clk IMX8MQ_CLK_CSI2_CORE>,
1434 <&clk IMX8MQ_CLK_CSI2_PHY_REF>,
1435 <&clk IMX8MQ_CLK_CSI2_ESC>;
1436 assigned-clock-rates = <266000000>, <333000000>, <66000000>;
1437 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
1438 <&clk IMX8MQ_SYS2_PLL_1000M>,
1439 <&clk IMX8MQ_SYS1_PLL_800M>;
1440 power-domains = <&pgc_mipi_csi2>;
1441 resets = <&src IMX8MQ_RESET_MIPI_CSI2_CORE_RESET>,
1442 <&src IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET>,
1443 <&src IMX8MQ_RESET_MIPI_CSI2_ESC_RESET>;
1444 fsl,mipi-phy-gpr = <&iomuxc_gpr 0xa4>;
1445 interconnects = <&noc IMX8MQ_ICM_CSI2 &noc IMX8MQ_ICS_DRAM>;
1446 interconnect-names = "dram";
1447 status = "disabled";
1448
1449 ports {
1450 #address-cells = <1>;
1451 #size-cells = <0>;
1452
1453 port@1 {
1454 reg = <1>;
1455
1456 csi2_mipi_ep: endpoint {
1457 remote-endpoint = <&csi2_ep>;
1458 };
1459 };
1460 };
1461 };
1462
1463 csi2: csi@30b80000 {
1464 compatible = "fsl,imx8mq-csi";
1465 reg = <0x30b80000 0x10000>;
1466 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1467 clocks = <&clk IMX8MQ_CLK_CSI2_ROOT>;
1468 clock-names = "mclk";
1469 status = "disabled";
1470
1471 port {
1472 csi2_ep: endpoint {
1473 remote-endpoint = <&csi2_mipi_ep>;
1474 };
1475 };
1476 };
1477
1478 mu: mailbox@30aa0000 {
1479 compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu";
1480 reg = <0x30aa0000 0x10000>;
1481 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1482 clocks = <&clk IMX8MQ_CLK_MU_ROOT>;
1483 #mbox-cells = <2>;
1484 };
1485
1486 usdhc1: mmc@30b40000 {
1487 compatible = "fsl,imx8mq-usdhc",
1488 "fsl,imx7d-usdhc";
1489 reg = <0x30b40000 0x10000>;
1490 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1491 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
1492 <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
1493 <&clk IMX8MQ_CLK_USDHC1_ROOT>;
1494 clock-names = "ipg", "ahb", "per";
1495 fsl,tuning-start-tap = <20>;
1496 fsl,tuning-step = <2>;
1497 bus-width = <4>;
1498 status = "disabled";
1499 };
1500
1501 usdhc2: mmc@30b50000 {
1502 compatible = "fsl,imx8mq-usdhc",
1503 "fsl,imx7d-usdhc";
1504 reg = <0x30b50000 0x10000>;
1505 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1506 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
1507 <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
1508 <&clk IMX8MQ_CLK_USDHC2_ROOT>;
1509 clock-names = "ipg", "ahb", "per";
1510 fsl,tuning-start-tap = <20>;
1511 fsl,tuning-step = <2>;
1512 bus-width = <4>;
1513 status = "disabled";
1514 };
1515
1516 qspi0: spi@30bb0000 {
1517 #address-cells = <1>;
1518 #size-cells = <0>;
1519 compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi";
1520 reg = <0x30bb0000 0x10000>,
1521 <0x08000000 0x10000000>;
1522 reg-names = "QuadSPI", "QuadSPI-memory";
1523 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1524 clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>,
1525 <&clk IMX8MQ_CLK_QSPI_ROOT>;
1526 clock-names = "qspi_en", "qspi";
1527 status = "disabled";
1528 };
1529
1530 sdma1: dma-controller@30bd0000 {
1531 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
1532 reg = <0x30bd0000 0x10000>;
1533 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1534 clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>,
1535 <&clk IMX8MQ_CLK_AHB>;
1536 clock-names = "ipg", "ahb";
1537 #dma-cells = <3>;
1538 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1539 };
1540
1541 fec1: ethernet@30be0000 {
1542 compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1543 reg = <0x30be0000 0x10000>;
1544 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1545 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1546 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1547 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1548 clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
1549 <&clk IMX8MQ_CLK_ENET1_ROOT>,
1550 <&clk IMX8MQ_CLK_ENET_TIMER>,
1551 <&clk IMX8MQ_CLK_ENET_REF>,
1552 <&clk IMX8MQ_CLK_ENET_PHY_REF>;
1553 clock-names = "ipg", "ahb", "ptp",
1554 "enet_clk_ref", "enet_out";
1555 assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI>,
1556 <&clk IMX8MQ_CLK_ENET_TIMER>,
1557 <&clk IMX8MQ_CLK_ENET_REF>,
1558 <&clk IMX8MQ_CLK_ENET_PHY_REF>;
1559 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
1560 <&clk IMX8MQ_SYS2_PLL_100M>,
1561 <&clk IMX8MQ_SYS2_PLL_125M>,
1562 <&clk IMX8MQ_SYS2_PLL_50M>;
1563 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1564 fsl,num-tx-queues = <3>;
1565 fsl,num-rx-queues = <3>;
1566 nvmem-cells = <&fec_mac_address>;
1567 nvmem-cell-names = "mac-address";
1568 fsl,stop-mode = <&iomuxc_gpr 0x10 3>;
1569 status = "disabled";
1570 };
1571 };
1572
1573 noc: interconnect@32700000 {
1574 compatible = "fsl,imx8mq-noc", "fsl,imx8m-noc";
1575 reg = <0x32700000 0x100000>;
1576 clocks = <&clk IMX8MQ_CLK_NOC>;
1577 fsl,ddrc = <&ddrc>;
1578 #interconnect-cells = <1>;
1579 operating-points-v2 = <&noc_opp_table>;
1580
1581 noc_opp_table: opp-table {
1582 compatible = "operating-points-v2";
1583
1584 opp-133000000 {
1585 opp-hz = /bits/ 64 <133333333>;
1586 };
1587
1588 opp-400000000 {
1589 opp-hz = /bits/ 64 <400000000>;
1590 };
1591
1592 opp-800000000 {
1593 opp-hz = /bits/ 64 <800000000>;
1594 };
1595 };
1596 };
1597
1598 aips4: bus@32c00000 { /* AIPS4 */
1599 compatible = "fsl,aips-bus", "simple-bus";
1600 reg = <0x32c00000 0x400000>;
1601 #address-cells = <1>;
1602 #size-cells = <1>;
1603 ranges = <0x32c00000 0x32c00000 0x400000>;
1604
1605 irqsteer: interrupt-controller@32e2d000 {
1606 compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer";
1607 reg = <0x32e2d000 0x1000>;
1608 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1609 clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
1610 clock-names = "ipg";
1611 fsl,channel = <0>;
1612 fsl,num-irqs = <64>;
1613 interrupt-controller;
1614 #interrupt-cells = <1>;
1615 };
1616 };
1617
1618 gpu: gpu@38000000 {
1619 compatible = "vivante,gc";
1620 reg = <0x38000000 0x40000>;
1621 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1622 clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
1623 <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
1624 <&clk IMX8MQ_CLK_GPU_AXI>,
1625 <&clk IMX8MQ_CLK_GPU_AHB>;
1626 clock-names = "core", "shader", "bus", "reg";
1627 #cooling-cells = <2>;
1628 assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>,
1629 <&clk IMX8MQ_CLK_GPU_SHADER_SRC>,
1630 <&clk IMX8MQ_CLK_GPU_AXI>,
1631 <&clk IMX8MQ_CLK_GPU_AHB>,
1632 <&clk IMX8MQ_GPU_PLL_BYPASS>;
1633 assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>,
1634 <&clk IMX8MQ_GPU_PLL_OUT>,
1635 <&clk IMX8MQ_GPU_PLL_OUT>,
1636 <&clk IMX8MQ_GPU_PLL_OUT>,
1637 <&clk IMX8MQ_GPU_PLL>;
1638 assigned-clock-rates = <800000000>, <800000000>,
1639 <800000000>, <800000000>, <0>;
1640 power-domains = <&pgc_gpu>;
1641 };
1642
1643 usb_dwc3_0: usb@38100000 {
1644 compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
1645 reg = <0x38100000 0x10000>;
1646 clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>,
1647 <&clk IMX8MQ_CLK_USB_CORE_REF>,
1648 <&clk IMX8MQ_CLK_32K>;
1649 clock-names = "bus_early", "ref", "suspend";
1650 assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
1651 <&clk IMX8MQ_CLK_USB_CORE_REF>;
1652 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
1653 <&clk IMX8MQ_SYS1_PLL_100M>;
1654 assigned-clock-rates = <500000000>, <100000000>;
1655 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1656 phys = <&usb3_phy0>, <&usb3_phy0>;
1657 phy-names = "usb2-phy", "usb3-phy";
1658 power-domains = <&pgc_otg1>;
1659 snps,parkmode-disable-ss-quirk;
1660 status = "disabled";
1661 };
1662
1663 usb3_phy0: usb-phy@381f0040 {
1664 compatible = "fsl,imx8mq-usb-phy";
1665 reg = <0x381f0040 0x40>;
1666 clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>;
1667 clock-names = "phy";
1668 assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
1669 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
1670 assigned-clock-rates = <100000000>;
1671 #phy-cells = <0>;
1672 status = "disabled";
1673 };
1674
1675 usb_dwc3_1: usb@38200000 {
1676 compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
1677 reg = <0x38200000 0x10000>;
1678 clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>,
1679 <&clk IMX8MQ_CLK_USB_CORE_REF>,
1680 <&clk IMX8MQ_CLK_32K>;
1681 clock-names = "bus_early", "ref", "suspend";
1682 assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
1683 <&clk IMX8MQ_CLK_USB_CORE_REF>;
1684 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
1685 <&clk IMX8MQ_SYS1_PLL_100M>;
1686 assigned-clock-rates = <500000000>, <100000000>;
1687 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1688 phys = <&usb3_phy1>, <&usb3_phy1>;
1689 phy-names = "usb2-phy", "usb3-phy";
1690 power-domains = <&pgc_otg2>;
1691 snps,parkmode-disable-ss-quirk;
1692 status = "disabled";
1693 };
1694
1695 usb3_phy1: usb-phy@382f0040 {
1696 compatible = "fsl,imx8mq-usb-phy";
1697 reg = <0x382f0040 0x40>;
1698 clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>;
1699 clock-names = "phy";
1700 assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
1701 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
1702 assigned-clock-rates = <100000000>;
1703 #phy-cells = <0>;
1704 status = "disabled";
1705 };
1706
1707 vpu_g1: video-codec@38300000 {
1708 compatible = "nxp,imx8mq-vpu-g1";
1709 reg = <0x38300000 0x10000>;
1710 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1711 clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>;
1712 power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>;
1713 };
1714
1715 vpu_g2: video-codec@38310000 {
1716 compatible = "nxp,imx8mq-vpu-g2";
1717 reg = <0x38310000 0x10000>;
1718 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1719 clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
1720 power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>;
1721 };
1722
1723 vpu_blk_ctrl: blk-ctrl@38320000 {
1724 compatible = "fsl,imx8mq-vpu-blk-ctrl";
1725 reg = <0x38320000 0x100>;
1726 power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>;
1727 power-domain-names = "bus", "g1", "g2";
1728 clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
1729 <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
1730 clock-names = "g1", "g2";
1731 #power-domain-cells = <1>;
1732 };
1733
1734 pcie0: pcie@33800000 {
1735 compatible = "fsl,imx8mq-pcie";
1736 reg = <0x33800000 0x400000>,
1737 <0x1ff00000 0x80000>;
1738 reg-names = "dbi", "config";
1739 #address-cells = <3>;
1740 #size-cells = <2>;
1741 device_type = "pci";
1742 bus-range = <0x00 0xff>;
1743 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */
1744 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
1745 num-lanes = <1>;
1746 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1747 interrupt-names = "msi";
1748 #interrupt-cells = <1>;
1749 interrupt-map-mask = <0 0 0 0x7>;
1750 interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1751 <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1752 <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1753 <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1754 fsl,max-link-speed = <2>;
1755 linux,pci-domain = <0>;
1756 clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
1757 <&clk IMX8MQ_CLK_PCIE1_PHY>,
1758 <&clk IMX8MQ_CLK_PCIE1_PHY>,
1759 <&clk IMX8MQ_CLK_PCIE1_AUX>;
1760 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
1761 power-domains = <&pgc_pcie>;
1762 resets = <&src IMX8MQ_RESET_PCIEPHY>,
1763 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
1764 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
1765 reset-names = "pciephy", "apps", "turnoff";
1766 assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_CTRL>,
1767 <&clk IMX8MQ_CLK_PCIE1_PHY>,
1768 <&clk IMX8MQ_CLK_PCIE1_AUX>;
1769 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
1770 <&clk IMX8MQ_SYS2_PLL_100M>,
1771 <&clk IMX8MQ_SYS1_PLL_80M>;
1772 assigned-clock-rates = <250000000>, <100000000>,
1773 <10000000>;
1774 status = "disabled";
1775 };
1776
1777 pcie1: pcie@33c00000 {
1778 compatible = "fsl,imx8mq-pcie";
1779 reg = <0x33c00000 0x400000>,
1780 <0x27f00000 0x80000>;
1781 reg-names = "dbi", "config";
1782 #address-cells = <3>;
1783 #size-cells = <2>;
1784 device_type = "pci";
1785 bus-range = <0x00 0xff>;
1786 ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000>, /* downstream I/O 64KB */
1787 <0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
1788 num-lanes = <1>;
1789 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1790 interrupt-names = "msi";
1791 #interrupt-cells = <1>;
1792 interrupt-map-mask = <0 0 0 0x7>;
1793 interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
1794 <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
1795 <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
1796 <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1797 fsl,max-link-speed = <2>;
1798 linux,pci-domain = <1>;
1799 clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
1800 <&clk IMX8MQ_CLK_PCIE2_PHY>,
1801 <&clk IMX8MQ_CLK_PCIE2_PHY>,
1802 <&clk IMX8MQ_CLK_PCIE2_AUX>;
1803 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
1804 power-domains = <&pgc_pcie>;
1805 resets = <&src IMX8MQ_RESET_PCIEPHY2>,
1806 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,
1807 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>;
1808 reset-names = "pciephy", "apps", "turnoff";
1809 assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>,
1810 <&clk IMX8MQ_CLK_PCIE2_PHY>,
1811 <&clk IMX8MQ_CLK_PCIE2_AUX>;
1812 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
1813 <&clk IMX8MQ_SYS2_PLL_100M>,
1814 <&clk IMX8MQ_SYS1_PLL_80M>;
1815 assigned-clock-rates = <250000000>, <100000000>,
1816 <10000000>;
1817 status = "disabled";
1818 };
1819
1820 pcie1_ep: pcie-ep@33c00000 {
1821 compatible = "fsl,imx8mq-pcie-ep";
1822 reg = <0x33c00000 0x000400000>,
1823 <0x20000000 0x08000000>;
1824 reg-names = "dbi", "addr_space";
1825 num-lanes = <1>;
1826 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1827 interrupt-names = "dma";
1828 fsl,max-link-speed = <2>;
1829 clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
1830 <&clk IMX8MQ_CLK_PCIE2_PHY>,
1831 <&clk IMX8MQ_CLK_PCIE2_PHY>,
1832 <&clk IMX8MQ_CLK_PCIE2_AUX>;
1833 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
1834 power-domains = <&pgc_pcie>;
1835 resets = <&src IMX8MQ_RESET_PCIEPHY2>,
1836 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,
1837 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>;
1838 reset-names = "pciephy", "apps", "turnoff";
1839 assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>,
1840 <&clk IMX8MQ_CLK_PCIE2_PHY>,
1841 <&clk IMX8MQ_CLK_PCIE2_AUX>;
1842 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
1843 <&clk IMX8MQ_SYS2_PLL_100M>,
1844 <&clk IMX8MQ_SYS1_PLL_80M>;
1845 assigned-clock-rates = <250000000>, <100000000>,
1846 <10000000>;
1847 num-ib-windows = <4>;
1848 num-ob-windows = <4>;
1849 status = "disabled";
1850 };
1851
1852 gic: interrupt-controller@38800000 {
1853 compatible = "arm,gic-v3";
1854 reg = <0x38800000 0x10000>, /* GIC Dist */
1855 <0x38880000 0xc0000>, /* GICR */
1856 <0x31000000 0x2000>, /* GICC */
1857 <0x31010000 0x2000>, /* GICV */
1858 <0x31020000 0x2000>; /* GICH */
1859 #interrupt-cells = <3>;
1860 interrupt-controller;
1861 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1862 interrupt-parent = <&gic>;
1863 };
1864
1865 ddrc: memory-controller@3d400000 {
1866 compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc";
1867 reg = <0x3d400000 0x400000>;
1868 clock-names = "core", "pll", "alt", "apb";
1869 clocks = <&clk IMX8MQ_CLK_DRAM_CORE>,
1870 <&clk IMX8MQ_DRAM_PLL_OUT>,
1871 <&clk IMX8MQ_CLK_DRAM_ALT>,
1872 <&clk IMX8MQ_CLK_DRAM_APB>;
1873 status = "disabled";
1874 };
1875
1876 ddr-pmu@3d800000 {
1877 compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu";
1878 reg = <0x3d800000 0x400000>;
1879 interrupt-parent = <&gic>;
1880 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1881 };
1882 };
1883};