dts/upstream/Bindings/spi/spi-fsl-dspi.txt

ARM Freescale DSPI controller

Required properties:
- compatible : must be one of:
	"fsl,vf610-dspi",
	"fsl,ls1021a-v1.0-dspi",
	"fsl,ls1012a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
	"fsl,ls1028a-dspi",
	"fsl,ls1043a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
	"fsl,ls1046a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
	"fsl,ls1088a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
	"fsl,ls2080a-dspi" (optionally followed by "fsl,ls2085a-dspi"),
	"fsl,ls2085a-dspi",
	"fsl,lx2160a-dspi",
- reg : Offset and length of the register set for the device
- interrupts : Should contain SPI controller interrupt
- clocks: from common clock binding: handle to dspi clock.
- clock-names: from common clock binding: Shall be "dspi".
- pinctrl-0: pin control group to be used for this controller.
- pinctrl-names: must contain a "default" entry.
- spi-num-chipselects : the number of the chipselect signals.

Optional property:
- big-endian: If present the dspi device's registers are implemented
  in big endian mode.
- bus-num : the slave chip chipselect signal number.

Optional SPI slave node properties:
- fsl,spi-cs-sck-delay: a delay in nanoseconds between activating chip
  select and the start of clock signal, at the start of a transfer.
- fsl,spi-sck-cs-delay: a delay in nanoseconds between stopping the clock
  signal and deactivating chip select, at the end of a transfer.

Example:

dspi0@4002c000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,vf610-dspi";
	reg = <0x4002c000 0x1000>;
	interrupts = <0 67 0x04>;
	clocks = <&clks VF610_CLK_DSPI0>;
	clock-names = "dspi";
	spi-num-chipselects = <5>;
	bus-num = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_dspi0_1>;
	big-endian;

	sflash: at26df081a@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "atmel,at26df081a";
		spi-max-frequency = <16000000>;
		spi-cpol;
		spi-cpha;
		reg = <0>;
		linux,modalias = "m25p80";
		modal = "at26df081a";
		fsl,spi-cs-sck-delay = <100>;
		fsl,spi-sck-cs-delay = <50>;
	};
};