| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ |
| 3 | %YAML 1.2 |
| 4 | --- |
| 5 | $id: http://devicetree.org/schemas/soc/ti/k3-ringacc.yaml# |
| 6 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 7 | |
| 8 | title: Texas Instruments K3 NavigatorSS Ring Accelerator |
| 9 | |
| 10 | maintainers: |
| 11 | - Santosh Shilimkar <ssantosh@kernel.org> |
| 12 | - Grygorii Strashko <grygorii.strashko@ti.com> |
| 13 | |
| 14 | description: | |
| 15 | The Ring Accelerator (RA) is a machine which converts read/write accesses |
| 16 | from/to a constant address into corresponding read/write accesses from/to a |
| 17 | circular data structure in memory. The RA eliminates the need for each DMA |
| 18 | controller which needs to access ring elements from having to know the current |
| 19 | state of the ring (base address, current offset). The DMA controller |
| 20 | performs a read or write access to a specific address range (which maps to the |
| 21 | source interface on the RA) and the RA replaces the address for the transaction |
| 22 | with a new address which corresponds to the head or tail element of the ring |
| 23 | (head for reads, tail for writes). |
| 24 | |
| 25 | The Ring Accelerator is a hardware module that is responsible for accelerating |
| 26 | management of the packet queues. The K3 SoCs can have more than one RA instances |
| 27 | |
| 28 | allOf: |
| 29 | - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml# |
| 30 | |
| 31 | properties: |
| 32 | compatible: |
| 33 | items: |
| 34 | - const: ti,am654-navss-ringacc |
| 35 | |
| 36 | reg: |
| 37 | minItems: 4 |
| 38 | items: |
| 39 | - description: real time registers regions |
| 40 | - description: fifos registers regions |
| 41 | - description: proxy gcfg registers regions |
| 42 | - description: proxy target registers regions |
| 43 | - description: configuration registers region |
| 44 | |
| 45 | reg-names: |
| 46 | minItems: 4 |
| 47 | items: |
| 48 | - const: rt |
| 49 | - const: fifos |
| 50 | - const: proxy_gcfg |
| 51 | - const: proxy_target |
| 52 | - const: cfg |
| 53 | |
| 54 | msi-parent: true |
| 55 | |
| 56 | ti,num-rings: |
| 57 | $ref: /schemas/types.yaml#/definitions/uint32 |
| 58 | description: Number of rings supported by RA |
| 59 | |
| 60 | ti,sci-rm-range-gp-rings: |
| 61 | $ref: /schemas/types.yaml#/definitions/uint32 |
| 62 | description: TI-SCI RM subtype for GP ring range |
| 63 | |
| 64 | required: |
| 65 | - compatible |
| 66 | - reg |
| 67 | - reg-names |
| 68 | - msi-parent |
| 69 | - ti,num-rings |
| 70 | - ti,sci-rm-range-gp-rings |
| 71 | - ti,sci |
| 72 | - ti,sci-dev-id |
| 73 | |
| 74 | unevaluatedProperties: false |
| 75 | |
| 76 | examples: |
| 77 | - | |
| 78 | bus { |
| 79 | #address-cells = <2>; |
| 80 | #size-cells = <2>; |
| 81 | |
| 82 | ringacc: ringacc@3c000000 { |
| 83 | compatible = "ti,am654-navss-ringacc"; |
| 84 | reg = <0x0 0x3c000000 0x0 0x400000>, |
| 85 | <0x0 0x38000000 0x0 0x400000>, |
| 86 | <0x0 0x31120000 0x0 0x100>, |
| 87 | <0x0 0x33000000 0x0 0x40000>, |
| 88 | <0x0 0x31080000 0x0 0x40000>; |
| 89 | reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; |
| 90 | ti,num-rings = <818>; |
| 91 | ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */ |
| 92 | ti,sci = <&dmsc>; |
| 93 | ti,sci-dev-id = <187>; |
| 94 | msi-parent = <&inta_main_udmass>; |
| 95 | }; |
| 96 | }; |